1/* 2 * MPC8378E RDB Device Tree Source 3 * 4 * Copyright 2007, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 compatible = "fsl,mpc8378rdb"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 ethernet0 = &enet0; 21 ethernet1 = &enet1; 22 serial0 = &serial0; 23 serial1 = &serial1; 24 pci0 = &pci0; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,8378@0 { 32 device_type = "cpu"; 33 reg = <0x0>; 34 d-cache-line-size = <32>; 35 i-cache-line-size = <32>; 36 d-cache-size = <32768>; 37 i-cache-size = <32768>; 38 timebase-frequency = <0>; 39 bus-frequency = <0>; 40 clock-frequency = <0>; 41 }; 42 }; 43 44 memory { 45 device_type = "memory"; 46 reg = <0x00000000 0x10000000>; // 256MB at 0 47 }; 48 49 localbus@e0005000 { 50 #address-cells = <2>; 51 #size-cells = <1>; 52 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus"; 53 reg = <0xe0005000 0x1000>; 54 interrupts = <77 0x8>; 55 interrupt-parent = <&ipic>; 56 57 // CS0 and CS1 are swapped when 58 // booting from nand, but the 59 // addresses are the same. 60 ranges = <0x0 0x0 0xfe000000 0x00800000 61 0x1 0x0 0xe0600000 0x00008000 62 0x2 0x0 0xf0000000 0x00020000 63 0x3 0x0 0xfa000000 0x00008000>; 64 65 flash@0,0 { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 compatible = "cfi-flash"; 69 reg = <0x0 0x0 0x800000>; 70 bank-width = <2>; 71 device-width = <1>; 72 }; 73 74 nand@1,0 { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 compatible = "fsl,mpc8378-fcm-nand", 78 "fsl,elbc-fcm-nand"; 79 reg = <0x1 0x0 0x8000>; 80 81 u-boot@0 { 82 reg = <0x0 0x100000>; 83 read-only; 84 }; 85 86 kernel@100000 { 87 reg = <0x100000 0x300000>; 88 }; 89 fs@400000 { 90 reg = <0x400000 0x1c00000>; 91 }; 92 }; 93 }; 94 95 immr@e0000000 { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 device_type = "soc"; 99 compatible = "simple-bus"; 100 ranges = <0x0 0xe0000000 0x00100000>; 101 reg = <0xe0000000 0x00000200>; 102 bus-frequency = <0>; 103 104 wdt@200 { 105 device_type = "watchdog"; 106 compatible = "mpc83xx_wdt"; 107 reg = <0x200 0x100>; 108 }; 109 110 i2c@3000 { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 cell-index = <0>; 114 compatible = "fsl-i2c"; 115 reg = <0x3000 0x100>; 116 interrupts = <14 0x8>; 117 interrupt-parent = <&ipic>; 118 dfsrr; 119 rtc@68 { 120 device_type = "rtc"; 121 compatible = "dallas,ds1339"; 122 reg = <0x68>; 123 }; 124 }; 125 126 i2c@3100 { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 cell-index = <1>; 130 compatible = "fsl-i2c"; 131 reg = <0x3100 0x100>; 132 interrupts = <15 0x8>; 133 interrupt-parent = <&ipic>; 134 dfsrr; 135 }; 136 137 spi@7000 { 138 cell-index = <0>; 139 compatible = "fsl,spi"; 140 reg = <0x7000 0x1000>; 141 interrupts = <16 0x8>; 142 interrupt-parent = <&ipic>; 143 mode = "cpu"; 144 }; 145 146 dma@82a8 { 147 #address-cells = <1>; 148 #size-cells = <1>; 149 compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; 150 reg = <0x82a8 4>; 151 ranges = <0 0x8100 0x1a8>; 152 interrupt-parent = <&ipic>; 153 interrupts = <71 8>; 154 cell-index = <0>; 155 dma-channel@0 { 156 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 157 reg = <0 0x80>; 158 cell-index = <0>; 159 interrupt-parent = <&ipic>; 160 interrupts = <71 8>; 161 }; 162 dma-channel@80 { 163 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 164 reg = <0x80 0x80>; 165 cell-index = <1>; 166 interrupt-parent = <&ipic>; 167 interrupts = <71 8>; 168 }; 169 dma-channel@100 { 170 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 171 reg = <0x100 0x80>; 172 cell-index = <2>; 173 interrupt-parent = <&ipic>; 174 interrupts = <71 8>; 175 }; 176 dma-channel@180 { 177 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 178 reg = <0x180 0x28>; 179 cell-index = <3>; 180 interrupt-parent = <&ipic>; 181 interrupts = <71 8>; 182 }; 183 }; 184 185 usb@23000 { 186 compatible = "fsl-usb2-dr"; 187 reg = <0x23000 0x1000>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 interrupt-parent = <&ipic>; 191 interrupts = <38 0x8>; 192 phy_type = "ulpi"; 193 }; 194 195 mdio@24520 { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 compatible = "fsl,gianfar-mdio"; 199 reg = <0x24520 0x20>; 200 phy2: ethernet-phy@2 { 201 interrupt-parent = <&ipic>; 202 interrupts = <17 0x8>; 203 reg = <0x2>; 204 device_type = "ethernet-phy"; 205 }; 206 }; 207 208 enet0: ethernet@24000 { 209 cell-index = <0>; 210 device_type = "network"; 211 model = "eTSEC"; 212 compatible = "gianfar"; 213 reg = <0x24000 0x1000>; 214 local-mac-address = [ 00 00 00 00 00 00 ]; 215 interrupts = <32 0x8 33 0x8 34 0x8>; 216 phy-connection-type = "mii"; 217 interrupt-parent = <&ipic>; 218 phy-handle = <&phy2>; 219 }; 220 221 enet1: ethernet@25000 { 222 cell-index = <1>; 223 device_type = "network"; 224 model = "eTSEC"; 225 compatible = "gianfar"; 226 reg = <0x25000 0x1000>; 227 local-mac-address = [ 00 00 00 00 00 00 ]; 228 interrupts = <35 0x8 36 0x8 37 0x8>; 229 phy-connection-type = "mii"; 230 interrupt-parent = <&ipic>; 231 fixed-link = <1 1 1000 0 0>; 232 }; 233 234 serial0: serial@4500 { 235 cell-index = <0>; 236 device_type = "serial"; 237 compatible = "ns16550"; 238 reg = <0x4500 0x100>; 239 clock-frequency = <0>; 240 interrupts = <9 0x8>; 241 interrupt-parent = <&ipic>; 242 }; 243 244 serial1: serial@4600 { 245 cell-index = <1>; 246 device_type = "serial"; 247 compatible = "ns16550"; 248 reg = <0x4600 0x100>; 249 clock-frequency = <0>; 250 interrupts = <10 0x8>; 251 interrupt-parent = <&ipic>; 252 }; 253 254 crypto@30000 { 255 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 256 "fsl,sec2.1", "fsl,sec2.0"; 257 reg = <0x30000 0x10000>; 258 interrupts = <11 0x8>; 259 interrupt-parent = <&ipic>; 260 fsl,num-channels = <4>; 261 fsl,channel-fifo-len = <24>; 262 fsl,exec-units-mask = <0x9fe>; 263 fsl,descriptor-types-mask = <0x3ab0ebf>; 264 }; 265 266 /* IPIC 267 * interrupts cell = <intr #, sense> 268 * sense values match linux IORESOURCE_IRQ_* defines: 269 * sense == 8: Level, low assertion 270 * sense == 2: Edge, high-to-low change 271 */ 272 ipic: interrupt-controller@700 { 273 compatible = "fsl,ipic"; 274 interrupt-controller; 275 #address-cells = <0>; 276 #interrupt-cells = <2>; 277 reg = <0x700 0x100>; 278 }; 279 }; 280 281 pci0: pci@e0008500 { 282 interrupt-map-mask = <0xf800 0 0 7>; 283 interrupt-map = < 284 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 285 286 /* IDSEL AD14 IRQ6 inta */ 287 0x7000 0x0 0x0 0x1 &ipic 22 0x8 288 289 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 290 0x7800 0x0 0x0 0x1 &ipic 21 0x8 291 0x7800 0x0 0x0 0x2 &ipic 22 0x8 292 0x7800 0x0 0x0 0x4 &ipic 23 0x8 293 294 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 295 0xE000 0x0 0x0 0x1 &ipic 23 0x8 296 0xE000 0x0 0x0 0x2 &ipic 21 0x8 297 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; 298 interrupt-parent = <&ipic>; 299 interrupts = <66 0x8>; 300 bus-range = <0 0>; 301 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 302 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 303 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 304 clock-frequency = <66666666>; 305 #interrupt-cells = <1>; 306 #size-cells = <2>; 307 #address-cells = <3>; 308 reg = <0xe0008500 0x100>; 309 compatible = "fsl,mpc8349-pci"; 310 device_type = "pci"; 311 }; 312}; 313