1/* 2 * MPC8378E RDB Device Tree Source 3 * 4 * Copyright 2007, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 compatible = "fsl,mpc8378rdb"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 ethernet0 = &enet0; 21 ethernet1 = &enet1; 22 serial0 = &serial0; 23 serial1 = &serial1; 24 pci0 = &pci0; 25 pci1 = &pci1; 26 pci2 = &pci2; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 PowerPC,8378@0 { 34 device_type = "cpu"; 35 reg = <0x0>; 36 d-cache-line-size = <32>; 37 i-cache-line-size = <32>; 38 d-cache-size = <32768>; 39 i-cache-size = <32768>; 40 timebase-frequency = <0>; 41 bus-frequency = <0>; 42 clock-frequency = <0>; 43 }; 44 }; 45 46 memory { 47 device_type = "memory"; 48 reg = <0x00000000 0x10000000>; // 256MB at 0 49 }; 50 51 localbus@e0005000 { 52 #address-cells = <2>; 53 #size-cells = <1>; 54 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus"; 55 reg = <0xe0005000 0x1000>; 56 interrupts = <77 0x8>; 57 interrupt-parent = <&ipic>; 58 59 // CS0 and CS1 are swapped when 60 // booting from nand, but the 61 // addresses are the same. 62 ranges = <0x0 0x0 0xfe000000 0x00800000 63 0x1 0x0 0xe0600000 0x00008000 64 0x2 0x0 0xf0000000 0x00020000 65 0x3 0x0 0xfa000000 0x00008000>; 66 67 flash@0,0 { 68 #address-cells = <1>; 69 #size-cells = <1>; 70 compatible = "cfi-flash"; 71 reg = <0x0 0x0 0x800000>; 72 bank-width = <2>; 73 device-width = <1>; 74 }; 75 76 nand@1,0 { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 compatible = "fsl,mpc8378-fcm-nand", 80 "fsl,elbc-fcm-nand"; 81 reg = <0x1 0x0 0x8000>; 82 83 u-boot@0 { 84 reg = <0x0 0x100000>; 85 read-only; 86 }; 87 88 kernel@100000 { 89 reg = <0x100000 0x300000>; 90 }; 91 fs@400000 { 92 reg = <0x400000 0x1c00000>; 93 }; 94 }; 95 }; 96 97 immr@e0000000 { 98 #address-cells = <1>; 99 #size-cells = <1>; 100 device_type = "soc"; 101 compatible = "simple-bus"; 102 ranges = <0x0 0xe0000000 0x00100000>; 103 reg = <0xe0000000 0x00000200>; 104 bus-frequency = <0>; 105 106 wdt@200 { 107 device_type = "watchdog"; 108 compatible = "mpc83xx_wdt"; 109 reg = <0x200 0x100>; 110 }; 111 112 gpio1: gpio-controller@c00 { 113 #gpio-cells = <2>; 114 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio"; 115 reg = <0xc00 0x100>; 116 interrupts = <74 0x8>; 117 interrupt-parent = <&ipic>; 118 gpio-controller; 119 }; 120 121 gpio2: gpio-controller@d00 { 122 #gpio-cells = <2>; 123 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio"; 124 reg = <0xd00 0x100>; 125 interrupts = <75 0x8>; 126 interrupt-parent = <&ipic>; 127 gpio-controller; 128 }; 129 130 i2c@3000 { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 cell-index = <0>; 134 compatible = "fsl-i2c"; 135 reg = <0x3000 0x100>; 136 interrupts = <14 0x8>; 137 interrupt-parent = <&ipic>; 138 dfsrr; 139 140 dtt@48 { 141 compatible = "national,lm75"; 142 reg = <0x48>; 143 }; 144 145 at24@50 { 146 compatible = "at24,24c256"; 147 reg = <0x50>; 148 }; 149 150 rtc@68 { 151 compatible = "dallas,ds1339"; 152 reg = <0x68>; 153 }; 154 155 mcu_pio: mcu@a { 156 #gpio-cells = <2>; 157 compatible = "fsl,mc9s08qg8-mpc8378erdb", 158 "fsl,mcu-mpc8349emitx"; 159 reg = <0x0a>; 160 gpio-controller; 161 }; 162 }; 163 164 i2c@3100 { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 cell-index = <1>; 168 compatible = "fsl-i2c"; 169 reg = <0x3100 0x100>; 170 interrupts = <15 0x8>; 171 interrupt-parent = <&ipic>; 172 dfsrr; 173 }; 174 175 spi@7000 { 176 cell-index = <0>; 177 compatible = "fsl,spi"; 178 reg = <0x7000 0x1000>; 179 interrupts = <16 0x8>; 180 interrupt-parent = <&ipic>; 181 mode = "cpu"; 182 }; 183 184 dma@82a8 { 185 #address-cells = <1>; 186 #size-cells = <1>; 187 compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; 188 reg = <0x82a8 4>; 189 ranges = <0 0x8100 0x1a8>; 190 interrupt-parent = <&ipic>; 191 interrupts = <71 8>; 192 cell-index = <0>; 193 dma-channel@0 { 194 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 195 reg = <0 0x80>; 196 cell-index = <0>; 197 interrupt-parent = <&ipic>; 198 interrupts = <71 8>; 199 }; 200 dma-channel@80 { 201 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 202 reg = <0x80 0x80>; 203 cell-index = <1>; 204 interrupt-parent = <&ipic>; 205 interrupts = <71 8>; 206 }; 207 dma-channel@100 { 208 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 209 reg = <0x100 0x80>; 210 cell-index = <2>; 211 interrupt-parent = <&ipic>; 212 interrupts = <71 8>; 213 }; 214 dma-channel@180 { 215 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 216 reg = <0x180 0x28>; 217 cell-index = <3>; 218 interrupt-parent = <&ipic>; 219 interrupts = <71 8>; 220 }; 221 }; 222 223 usb@23000 { 224 compatible = "fsl-usb2-dr"; 225 reg = <0x23000 0x1000>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 interrupt-parent = <&ipic>; 229 interrupts = <38 0x8>; 230 phy_type = "ulpi"; 231 }; 232 233 mdio@24520 { 234 #address-cells = <1>; 235 #size-cells = <0>; 236 compatible = "fsl,gianfar-mdio"; 237 reg = <0x24520 0x20>; 238 phy2: ethernet-phy@2 { 239 interrupt-parent = <&ipic>; 240 interrupts = <17 0x8>; 241 reg = <0x2>; 242 device_type = "ethernet-phy"; 243 }; 244 tbi0: tbi-phy@11 { 245 reg = <0x11>; 246 device_type = "tbi-phy"; 247 }; 248 }; 249 250 mdio@25520 { 251 #address-cells = <1>; 252 #size-cells = <0>; 253 compatible = "fsl,gianfar-tbi"; 254 reg = <0x25520 0x20>; 255 256 tbi1: tbi-phy@11 { 257 reg = <0x11>; 258 device_type = "tbi-phy"; 259 }; 260 }; 261 262 263 enet0: ethernet@24000 { 264 cell-index = <0>; 265 device_type = "network"; 266 model = "eTSEC"; 267 compatible = "gianfar"; 268 reg = <0x24000 0x1000>; 269 local-mac-address = [ 00 00 00 00 00 00 ]; 270 interrupts = <32 0x8 33 0x8 34 0x8>; 271 phy-connection-type = "mii"; 272 interrupt-parent = <&ipic>; 273 phy-handle = <&phy2>; 274 }; 275 276 enet1: ethernet@25000 { 277 cell-index = <1>; 278 device_type = "network"; 279 model = "eTSEC"; 280 compatible = "gianfar"; 281 reg = <0x25000 0x1000>; 282 local-mac-address = [ 00 00 00 00 00 00 ]; 283 interrupts = <35 0x8 36 0x8 37 0x8>; 284 phy-connection-type = "mii"; 285 interrupt-parent = <&ipic>; 286 fixed-link = <1 1 1000 0 0>; 287 }; 288 289 serial0: serial@4500 { 290 cell-index = <0>; 291 device_type = "serial"; 292 compatible = "ns16550"; 293 reg = <0x4500 0x100>; 294 clock-frequency = <0>; 295 interrupts = <9 0x8>; 296 interrupt-parent = <&ipic>; 297 }; 298 299 serial1: serial@4600 { 300 cell-index = <1>; 301 device_type = "serial"; 302 compatible = "ns16550"; 303 reg = <0x4600 0x100>; 304 clock-frequency = <0>; 305 interrupts = <10 0x8>; 306 interrupt-parent = <&ipic>; 307 }; 308 309 crypto@30000 { 310 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 311 "fsl,sec2.1", "fsl,sec2.0"; 312 reg = <0x30000 0x10000>; 313 interrupts = <11 0x8>; 314 interrupt-parent = <&ipic>; 315 fsl,num-channels = <4>; 316 fsl,channel-fifo-len = <24>; 317 fsl,exec-units-mask = <0x9fe>; 318 fsl,descriptor-types-mask = <0x3ab0ebf>; 319 }; 320 321 sdhci@2e000 { 322 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc"; 323 reg = <0x2e000 0x1000>; 324 interrupts = <42 0x8>; 325 interrupt-parent = <&ipic>; 326 /* Filled in by U-Boot */ 327 clock-frequency = <0>; 328 }; 329 330 /* IPIC 331 * interrupts cell = <intr #, sense> 332 * sense values match linux IORESOURCE_IRQ_* defines: 333 * sense == 8: Level, low assertion 334 * sense == 2: Edge, high-to-low change 335 */ 336 ipic: interrupt-controller@700 { 337 compatible = "fsl,ipic"; 338 interrupt-controller; 339 #address-cells = <0>; 340 #interrupt-cells = <2>; 341 reg = <0x700 0x100>; 342 }; 343 }; 344 345 pci0: pci@e0008500 { 346 interrupt-map-mask = <0xf800 0 0 7>; 347 interrupt-map = < 348 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 349 350 /* IDSEL AD14 IRQ6 inta */ 351 0x7000 0x0 0x0 0x1 &ipic 22 0x8 352 353 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 354 0x7800 0x0 0x0 0x1 &ipic 21 0x8 355 0x7800 0x0 0x0 0x2 &ipic 22 0x8 356 0x7800 0x0 0x0 0x4 &ipic 23 0x8 357 358 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 359 0xE000 0x0 0x0 0x1 &ipic 23 0x8 360 0xE000 0x0 0x0 0x2 &ipic 21 0x8 361 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; 362 interrupt-parent = <&ipic>; 363 interrupts = <66 0x8>; 364 bus-range = <0 0>; 365 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 366 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 367 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 368 clock-frequency = <66666666>; 369 #interrupt-cells = <1>; 370 #size-cells = <2>; 371 #address-cells = <3>; 372 reg = <0xe0008500 0x100 /* internal registers */ 373 0xe0008300 0x8>; /* config space access registers */ 374 compatible = "fsl,mpc8349-pci"; 375 device_type = "pci"; 376 }; 377 378 pci1: pcie@e0009000 { 379 #address-cells = <3>; 380 #size-cells = <2>; 381 #interrupt-cells = <1>; 382 device_type = "pci"; 383 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; 384 reg = <0xe0009000 0x00001000>; 385 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 386 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; 387 bus-range = <0 255>; 388 interrupt-map-mask = <0xf800 0 0 7>; 389 interrupt-map = <0 0 0 1 &ipic 1 8 390 0 0 0 2 &ipic 1 8 391 0 0 0 3 &ipic 1 8 392 0 0 0 4 &ipic 1 8>; 393 clock-frequency = <0>; 394 395 pcie@0 { 396 #address-cells = <3>; 397 #size-cells = <2>; 398 device_type = "pci"; 399 reg = <0 0 0 0 0>; 400 ranges = <0x02000000 0 0xa8000000 401 0x02000000 0 0xa8000000 402 0 0x10000000 403 0x01000000 0 0x00000000 404 0x01000000 0 0x00000000 405 0 0x00800000>; 406 }; 407 }; 408 409 pci2: pcie@e000a000 { 410 #address-cells = <3>; 411 #size-cells = <2>; 412 #interrupt-cells = <1>; 413 device_type = "pci"; 414 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; 415 reg = <0xe000a000 0x00001000>; 416 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 417 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; 418 bus-range = <0 255>; 419 interrupt-map-mask = <0xf800 0 0 7>; 420 interrupt-map = <0 0 0 1 &ipic 2 8 421 0 0 0 2 &ipic 2 8 422 0 0 0 3 &ipic 2 8 423 0 0 0 4 &ipic 2 8>; 424 clock-frequency = <0>; 425 426 pcie@0 { 427 #address-cells = <3>; 428 #size-cells = <2>; 429 device_type = "pci"; 430 reg = <0 0 0 0 0>; 431 ranges = <0x02000000 0 0xc8000000 432 0x02000000 0 0xc8000000 433 0 0x10000000 434 0x01000000 0 0x00000000 435 0x01000000 0 0x00000000 436 0 0x00800000>; 437 }; 438 }; 439}; 440