1/* 2 * MPC8378E RDB Device Tree Source 3 * 4 * Copyright 2007, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 compatible = "fsl,mpc8378rdb"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 ethernet0 = &enet0; 21 ethernet1 = &enet1; 22 serial0 = &serial0; 23 serial1 = &serial1; 24 pci0 = &pci0; 25 pci1 = &pci1; 26 pci2 = &pci2; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 PowerPC,8378@0 { 34 device_type = "cpu"; 35 reg = <0x0>; 36 d-cache-line-size = <32>; 37 i-cache-line-size = <32>; 38 d-cache-size = <32768>; 39 i-cache-size = <32768>; 40 timebase-frequency = <0>; 41 bus-frequency = <0>; 42 clock-frequency = <0>; 43 }; 44 }; 45 46 memory { 47 device_type = "memory"; 48 reg = <0x00000000 0x10000000>; // 256MB at 0 49 }; 50 51 localbus@e0005000 { 52 #address-cells = <2>; 53 #size-cells = <1>; 54 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus"; 55 reg = <0xe0005000 0x1000>; 56 interrupts = <77 0x8>; 57 interrupt-parent = <&ipic>; 58 59 // CS0 and CS1 are swapped when 60 // booting from nand, but the 61 // addresses are the same. 62 ranges = <0x0 0x0 0xfe000000 0x00800000 63 0x1 0x0 0xe0600000 0x00008000 64 0x2 0x0 0xf0000000 0x00020000 65 0x3 0x0 0xfa000000 0x00008000>; 66 67 flash@0,0 { 68 #address-cells = <1>; 69 #size-cells = <1>; 70 compatible = "cfi-flash"; 71 reg = <0x0 0x0 0x800000>; 72 bank-width = <2>; 73 device-width = <1>; 74 }; 75 76 nand@1,0 { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 compatible = "fsl,mpc8378-fcm-nand", 80 "fsl,elbc-fcm-nand"; 81 reg = <0x1 0x0 0x8000>; 82 83 u-boot@0 { 84 reg = <0x0 0x100000>; 85 read-only; 86 }; 87 88 kernel@100000 { 89 reg = <0x100000 0x300000>; 90 }; 91 fs@400000 { 92 reg = <0x400000 0x1c00000>; 93 }; 94 }; 95 }; 96 97 immr@e0000000 { 98 #address-cells = <1>; 99 #size-cells = <1>; 100 device_type = "soc"; 101 compatible = "simple-bus"; 102 ranges = <0x0 0xe0000000 0x00100000>; 103 reg = <0xe0000000 0x00000200>; 104 bus-frequency = <0>; 105 106 wdt@200 { 107 device_type = "watchdog"; 108 compatible = "mpc83xx_wdt"; 109 reg = <0x200 0x100>; 110 }; 111 112 gpio1: gpio-controller@c00 { 113 #gpio-cells = <2>; 114 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio"; 115 reg = <0xc00 0x100>; 116 interrupts = <74 0x8>; 117 interrupt-parent = <&ipic>; 118 gpio-controller; 119 }; 120 121 gpio2: gpio-controller@d00 { 122 #gpio-cells = <2>; 123 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio"; 124 reg = <0xd00 0x100>; 125 interrupts = <75 0x8>; 126 interrupt-parent = <&ipic>; 127 gpio-controller; 128 }; 129 130 i2c@3000 { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 cell-index = <0>; 134 compatible = "fsl-i2c"; 135 reg = <0x3000 0x100>; 136 interrupts = <14 0x8>; 137 interrupt-parent = <&ipic>; 138 dfsrr; 139 140 at24@50 { 141 compatible = "at24,24c256"; 142 reg = <0x50>; 143 }; 144 145 rtc@68 { 146 compatible = "dallas,ds1339"; 147 reg = <0x68>; 148 }; 149 150 mcu_pio: mcu@a { 151 #gpio-cells = <2>; 152 compatible = "fsl,mc9s08qg8-mpc8378erdb", 153 "fsl,mcu-mpc8349emitx"; 154 reg = <0x0a>; 155 gpio-controller; 156 }; 157 }; 158 159 i2c@3100 { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 cell-index = <1>; 163 compatible = "fsl-i2c"; 164 reg = <0x3100 0x100>; 165 interrupts = <15 0x8>; 166 interrupt-parent = <&ipic>; 167 dfsrr; 168 }; 169 170 spi@7000 { 171 cell-index = <0>; 172 compatible = "fsl,spi"; 173 reg = <0x7000 0x1000>; 174 interrupts = <16 0x8>; 175 interrupt-parent = <&ipic>; 176 mode = "cpu"; 177 }; 178 179 dma@82a8 { 180 #address-cells = <1>; 181 #size-cells = <1>; 182 compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; 183 reg = <0x82a8 4>; 184 ranges = <0 0x8100 0x1a8>; 185 interrupt-parent = <&ipic>; 186 interrupts = <71 8>; 187 cell-index = <0>; 188 dma-channel@0 { 189 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 190 reg = <0 0x80>; 191 cell-index = <0>; 192 interrupt-parent = <&ipic>; 193 interrupts = <71 8>; 194 }; 195 dma-channel@80 { 196 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 197 reg = <0x80 0x80>; 198 cell-index = <1>; 199 interrupt-parent = <&ipic>; 200 interrupts = <71 8>; 201 }; 202 dma-channel@100 { 203 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 204 reg = <0x100 0x80>; 205 cell-index = <2>; 206 interrupt-parent = <&ipic>; 207 interrupts = <71 8>; 208 }; 209 dma-channel@180 { 210 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 211 reg = <0x180 0x28>; 212 cell-index = <3>; 213 interrupt-parent = <&ipic>; 214 interrupts = <71 8>; 215 }; 216 }; 217 218 usb@23000 { 219 compatible = "fsl-usb2-dr"; 220 reg = <0x23000 0x1000>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 interrupt-parent = <&ipic>; 224 interrupts = <38 0x8>; 225 phy_type = "ulpi"; 226 }; 227 228 mdio@24520 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 compatible = "fsl,gianfar-mdio"; 232 reg = <0x24520 0x20>; 233 phy2: ethernet-phy@2 { 234 interrupt-parent = <&ipic>; 235 interrupts = <17 0x8>; 236 reg = <0x2>; 237 device_type = "ethernet-phy"; 238 }; 239 tbi0: tbi-phy@11 { 240 reg = <0x11>; 241 device_type = "tbi-phy"; 242 }; 243 }; 244 245 mdio@25520 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 compatible = "fsl,gianfar-tbi"; 249 reg = <0x25520 0x20>; 250 251 tbi1: tbi-phy@11 { 252 reg = <0x11>; 253 device_type = "tbi-phy"; 254 }; 255 }; 256 257 258 enet0: ethernet@24000 { 259 cell-index = <0>; 260 device_type = "network"; 261 model = "eTSEC"; 262 compatible = "gianfar"; 263 reg = <0x24000 0x1000>; 264 local-mac-address = [ 00 00 00 00 00 00 ]; 265 interrupts = <32 0x8 33 0x8 34 0x8>; 266 phy-connection-type = "mii"; 267 interrupt-parent = <&ipic>; 268 phy-handle = <&phy2>; 269 }; 270 271 enet1: ethernet@25000 { 272 cell-index = <1>; 273 device_type = "network"; 274 model = "eTSEC"; 275 compatible = "gianfar"; 276 reg = <0x25000 0x1000>; 277 local-mac-address = [ 00 00 00 00 00 00 ]; 278 interrupts = <35 0x8 36 0x8 37 0x8>; 279 phy-connection-type = "mii"; 280 interrupt-parent = <&ipic>; 281 fixed-link = <1 1 1000 0 0>; 282 }; 283 284 serial0: serial@4500 { 285 cell-index = <0>; 286 device_type = "serial"; 287 compatible = "ns16550"; 288 reg = <0x4500 0x100>; 289 clock-frequency = <0>; 290 interrupts = <9 0x8>; 291 interrupt-parent = <&ipic>; 292 }; 293 294 serial1: serial@4600 { 295 cell-index = <1>; 296 device_type = "serial"; 297 compatible = "ns16550"; 298 reg = <0x4600 0x100>; 299 clock-frequency = <0>; 300 interrupts = <10 0x8>; 301 interrupt-parent = <&ipic>; 302 }; 303 304 crypto@30000 { 305 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 306 "fsl,sec2.1", "fsl,sec2.0"; 307 reg = <0x30000 0x10000>; 308 interrupts = <11 0x8>; 309 interrupt-parent = <&ipic>; 310 fsl,num-channels = <4>; 311 fsl,channel-fifo-len = <24>; 312 fsl,exec-units-mask = <0x9fe>; 313 fsl,descriptor-types-mask = <0x3ab0ebf>; 314 }; 315 316 /* IPIC 317 * interrupts cell = <intr #, sense> 318 * sense values match linux IORESOURCE_IRQ_* defines: 319 * sense == 8: Level, low assertion 320 * sense == 2: Edge, high-to-low change 321 */ 322 ipic: interrupt-controller@700 { 323 compatible = "fsl,ipic"; 324 interrupt-controller; 325 #address-cells = <0>; 326 #interrupt-cells = <2>; 327 reg = <0x700 0x100>; 328 }; 329 }; 330 331 pci0: pci@e0008500 { 332 interrupt-map-mask = <0xf800 0 0 7>; 333 interrupt-map = < 334 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 335 336 /* IDSEL AD14 IRQ6 inta */ 337 0x7000 0x0 0x0 0x1 &ipic 22 0x8 338 339 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 340 0x7800 0x0 0x0 0x1 &ipic 21 0x8 341 0x7800 0x0 0x0 0x2 &ipic 22 0x8 342 0x7800 0x0 0x0 0x4 &ipic 23 0x8 343 344 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 345 0xE000 0x0 0x0 0x1 &ipic 23 0x8 346 0xE000 0x0 0x0 0x2 &ipic 21 0x8 347 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; 348 interrupt-parent = <&ipic>; 349 interrupts = <66 0x8>; 350 bus-range = <0 0>; 351 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 352 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 353 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 354 clock-frequency = <66666666>; 355 #interrupt-cells = <1>; 356 #size-cells = <2>; 357 #address-cells = <3>; 358 reg = <0xe0008500 0x100 /* internal registers */ 359 0xe0008300 0x8>; /* config space access registers */ 360 compatible = "fsl,mpc8349-pci"; 361 device_type = "pci"; 362 }; 363 364 pci1: pcie@e0009000 { 365 #address-cells = <3>; 366 #size-cells = <2>; 367 #interrupt-cells = <1>; 368 device_type = "pci"; 369 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; 370 reg = <0xe0009000 0x00001000>; 371 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 372 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; 373 bus-range = <0 255>; 374 interrupt-map-mask = <0xf800 0 0 7>; 375 interrupt-map = <0 0 0 1 &ipic 1 8 376 0 0 0 2 &ipic 1 8 377 0 0 0 3 &ipic 1 8 378 0 0 0 4 &ipic 1 8>; 379 clock-frequency = <0>; 380 381 pcie@0 { 382 #address-cells = <3>; 383 #size-cells = <2>; 384 device_type = "pci"; 385 reg = <0 0 0 0 0>; 386 ranges = <0x02000000 0 0xa8000000 387 0x02000000 0 0xa8000000 388 0 0x10000000 389 0x01000000 0 0x00000000 390 0x01000000 0 0x00000000 391 0 0x00800000>; 392 }; 393 }; 394 395 pci2: pcie@e000a000 { 396 #address-cells = <3>; 397 #size-cells = <2>; 398 #interrupt-cells = <1>; 399 device_type = "pci"; 400 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; 401 reg = <0xe000a000 0x00001000>; 402 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 403 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; 404 bus-range = <0 255>; 405 interrupt-map-mask = <0xf800 0 0 7>; 406 interrupt-map = <0 0 0 1 &ipic 2 8 407 0 0 0 2 &ipic 2 8 408 0 0 0 3 &ipic 2 8 409 0 0 0 4 &ipic 2 8>; 410 clock-frequency = <0>; 411 412 pcie@0 { 413 #address-cells = <3>; 414 #size-cells = <2>; 415 device_type = "pci"; 416 reg = <0 0 0 0 0>; 417 ranges = <0x02000000 0 0xc8000000 418 0x02000000 0 0xc8000000 419 0 0x10000000 420 0x01000000 0 0x00000000 421 0x01000000 0 0x00000000 422 0 0x00800000>; 423 }; 424 }; 425}; 426