1/*
2 * MPC8377E WLAN Device Tree Source
3 *
4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 * Copyright 2009 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16	compatible = "fsl,mpc8377wlan";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26		pci1 = &pci1;
27		pci2 = &pci2;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		PowerPC,8377@0 {
35			device_type = "cpu";
36			reg = <0x0>;
37			d-cache-line-size = <32>;
38			i-cache-line-size = <32>;
39			d-cache-size = <32768>;
40			i-cache-size = <32768>;
41			timebase-frequency = <0>;
42			bus-frequency = <0>;
43			clock-frequency = <0>;
44		};
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x00000000 0x20000000>;	// 512MB at 0
50	};
51
52	localbus@e0005000 {
53		#address-cells = <2>;
54		#size-cells = <1>;
55		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
56		reg = <0xe0005000 0x1000>;
57		interrupts = <77 0x8>;
58		interrupt-parent = <&ipic>;
59		ranges = <0x0 0x0 0xfc000000 0x04000000>;
60
61		flash@0,0 {
62			#address-cells = <1>;
63			#size-cells = <1>;
64			compatible = "cfi-flash";
65			reg = <0x0 0x0 0x4000000>;
66			bank-width = <2>;
67			device-width = <1>;
68
69			partition@0 {
70				reg = <0 0x8000>;
71				label = "u-boot";
72				read-only;
73			};
74
75			partition@a0000 {
76				reg = <0xa0000 0x300000>;
77				label = "kernel";
78			};
79
80			partition@3a0000 {
81				reg = <0x3a0000 0x3c60000>;
82				label = "rootfs";
83			};
84		};
85	};
86
87	immr@e0000000 {
88		#address-cells = <1>;
89		#size-cells = <1>;
90		device_type = "soc";
91		compatible = "simple-bus";
92		ranges = <0x0 0xe0000000 0x00100000>;
93		reg = <0xe0000000 0x00000200>;
94		bus-frequency = <0>;
95
96		wdt@200 {
97			device_type = "watchdog";
98			compatible = "mpc83xx_wdt";
99			reg = <0x200 0x100>;
100		};
101
102		gpio1: gpio-controller@c00 {
103			#gpio-cells = <2>;
104			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
105			reg = <0xc00 0x100>;
106			interrupts = <74 0x8>;
107			interrupt-parent = <&ipic>;
108			gpio-controller;
109		};
110
111		gpio2: gpio-controller@d00 {
112			#gpio-cells = <2>;
113			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
114			reg = <0xd00 0x100>;
115			interrupts = <75 0x8>;
116			interrupt-parent = <&ipic>;
117			gpio-controller;
118		};
119
120		sleep-nexus {
121			#address-cells = <1>;
122			#size-cells = <1>;
123			compatible = "simple-bus";
124			sleep = <&pmc 0x0c000000>;
125			ranges;
126
127			i2c@3000 {
128				#address-cells = <1>;
129				#size-cells = <0>;
130				cell-index = <0>;
131				compatible = "fsl-i2c";
132				reg = <0x3000 0x100>;
133				interrupts = <14 0x8>;
134				interrupt-parent = <&ipic>;
135				dfsrr;
136
137				at24@50 {
138					compatible = "at24,24c256";
139					reg = <0x50>;
140				};
141
142				rtc@68 {
143					compatible = "dallas,ds1339";
144					reg = <0x68>;
145				};
146			};
147
148			sdhci@2e000 {
149				compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
150				reg = <0x2e000 0x1000>;
151				interrupts = <42 0x8>;
152				interrupt-parent = <&ipic>;
153				clock-frequency = <133333333>;
154			};
155		};
156
157		i2c@3100 {
158			#address-cells = <1>;
159			#size-cells = <0>;
160			cell-index = <1>;
161			compatible = "fsl-i2c";
162			reg = <0x3100 0x100>;
163			interrupts = <15 0x8>;
164			interrupt-parent = <&ipic>;
165			dfsrr;
166		};
167
168		spi@7000 {
169			cell-index = <0>;
170			compatible = "fsl,spi";
171			reg = <0x7000 0x1000>;
172			interrupts = <16 0x8>;
173			interrupt-parent = <&ipic>;
174			mode = "cpu";
175		};
176
177		dma@82a8 {
178			#address-cells = <1>;
179			#size-cells = <1>;
180			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
181			reg = <0x82a8 4>;
182			ranges = <0 0x8100 0x1a8>;
183			interrupt-parent = <&ipic>;
184			interrupts = <71 8>;
185			cell-index = <0>;
186			dma-channel@0 {
187				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
188				reg = <0 0x80>;
189				cell-index = <0>;
190				interrupt-parent = <&ipic>;
191				interrupts = <71 8>;
192			};
193			dma-channel@80 {
194				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
195				reg = <0x80 0x80>;
196				cell-index = <1>;
197				interrupt-parent = <&ipic>;
198				interrupts = <71 8>;
199			};
200			dma-channel@100 {
201				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
202				reg = <0x100 0x80>;
203				cell-index = <2>;
204				interrupt-parent = <&ipic>;
205				interrupts = <71 8>;
206			};
207			dma-channel@180 {
208				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
209				reg = <0x180 0x28>;
210				cell-index = <3>;
211				interrupt-parent = <&ipic>;
212				interrupts = <71 8>;
213			};
214		};
215
216		usb@23000 {
217			compatible = "fsl-usb2-dr";
218			reg = <0x23000 0x1000>;
219			#address-cells = <1>;
220			#size-cells = <0>;
221			interrupt-parent = <&ipic>;
222			interrupts = <38 0x8>;
223			phy_type = "ulpi";
224			sleep = <&pmc 0x00c00000>;
225		};
226
227		enet0: ethernet@24000 {
228			#address-cells = <1>;
229			#size-cells = <1>;
230			cell-index = <0>;
231			device_type = "network";
232			model = "eTSEC";
233			compatible = "gianfar";
234			reg = <0x24000 0x1000>;
235			ranges = <0x0 0x24000 0x1000>;
236			local-mac-address = [ 00 00 00 00 00 00 ];
237			interrupts = <32 0x8 33 0x8 34 0x8>;
238			phy-connection-type = "mii";
239			interrupt-parent = <&ipic>;
240			tbi-handle = <&tbi0>;
241			phy-handle = <&phy2>;
242			sleep = <&pmc 0xc0000000>;
243			fsl,magic-packet;
244
245			mdio@520 {
246				#address-cells = <1>;
247				#size-cells = <0>;
248				compatible = "fsl,gianfar-mdio";
249				reg = <0x520 0x20>;
250
251				phy2: ethernet-phy@2 {
252					interrupt-parent = <&ipic>;
253					interrupts = <17 0x8>;
254					reg = <0x2>;
255					device_type = "ethernet-phy";
256				};
257
258				phy3: ethernet-phy@3 {
259					interrupt-parent = <&ipic>;
260					interrupts = <18 0x8>;
261					reg = <0x3>;
262					device_type = "ethernet-phy";
263				};
264
265				tbi0: tbi-phy@11 {
266					reg = <0x11>;
267					device_type = "tbi-phy";
268				};
269			};
270		};
271
272		enet1: ethernet@25000 {
273			#address-cells = <1>;
274			#size-cells = <1>;
275			cell-index = <1>;
276			device_type = "network";
277			model = "eTSEC";
278			compatible = "gianfar";
279			reg = <0x25000 0x1000>;
280			ranges = <0x0 0x25000 0x1000>;
281			local-mac-address = [ 00 00 00 00 00 00 ];
282			interrupts = <35 0x8 36 0x8 37 0x8>;
283			phy-connection-type = "mii";
284			interrupt-parent = <&ipic>;
285			phy-handle = <&phy3>;
286			tbi-handle = <&tbi1>;
287			sleep = <&pmc 0x30000000>;
288			fsl,magic-packet;
289
290			mdio@520 {
291				#address-cells = <1>;
292				#size-cells = <0>;
293				compatible = "fsl,gianfar-tbi";
294				reg = <0x520 0x20>;
295
296				tbi1: tbi-phy@11 {
297					reg = <0x11>;
298					device_type = "tbi-phy";
299				};
300			};
301		};
302
303		serial0: serial@4500 {
304			cell-index = <0>;
305			device_type = "serial";
306			compatible = "ns16550";
307			reg = <0x4500 0x100>;
308			clock-frequency = <0>;
309			interrupts = <9 0x8>;
310			interrupt-parent = <&ipic>;
311		};
312
313		serial1: serial@4600 {
314			cell-index = <1>;
315			device_type = "serial";
316			compatible = "ns16550";
317			reg = <0x4600 0x100>;
318			clock-frequency = <0>;
319			interrupts = <10 0x8>;
320			interrupt-parent = <&ipic>;
321		};
322
323		crypto@30000 {
324			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
325				     "fsl,sec2.1", "fsl,sec2.0";
326			reg = <0x30000 0x10000>;
327			interrupts = <11 0x8>;
328			interrupt-parent = <&ipic>;
329			fsl,num-channels = <4>;
330			fsl,channel-fifo-len = <24>;
331			fsl,exec-units-mask = <0x9fe>;
332			fsl,descriptor-types-mask = <0x3ab0ebf>;
333			sleep = <&pmc 0x03000000>;
334		};
335
336		sata@18000 {
337			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
338			reg = <0x18000 0x1000>;
339			interrupts = <44 0x8>;
340			interrupt-parent = <&ipic>;
341			sleep = <&pmc 0x000000c0>;
342		};
343
344		sata@19000 {
345			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
346			reg = <0x19000 0x1000>;
347			interrupts = <45 0x8>;
348			interrupt-parent = <&ipic>;
349			sleep = <&pmc 0x00000030>;
350		};
351
352		/* IPIC
353		 * interrupts cell = <intr #, sense>
354		 * sense values match linux IORESOURCE_IRQ_* defines:
355		 * sense == 8: Level, low assertion
356		 * sense == 2: Edge, high-to-low change
357		 */
358		ipic: interrupt-controller@700 {
359			compatible = "fsl,ipic";
360			interrupt-controller;
361			#address-cells = <0>;
362			#interrupt-cells = <2>;
363			reg = <0x700 0x100>;
364		};
365
366		pmc: power@b00 {
367			compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
368			reg = <0xb00 0x100 0xa00 0x100>;
369			interrupts = <80 0x8>;
370			interrupt-parent = <&ipic>;
371		};
372	};
373
374	pci0: pci@e0008500 {
375		interrupt-map-mask = <0xf800 0 0 7>;
376		interrupt-map = <
377				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
378
379				/* IDSEL AD14 IRQ6 inta */
380				 0x7000 0x0 0x0 0x1 &ipic 22 0x8
381
382				/* IDSEL AD15 IRQ5 inta */
383				 0x7800 0x0 0x0 0x1 &ipic 21 0x8>;
384		interrupt-parent = <&ipic>;
385		interrupts = <66 0x8>;
386		bus-range = <0 0>;
387		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
388		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
389		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
390		sleep = <&pmc 0x00010000>;
391		clock-frequency = <66666666>;
392		#interrupt-cells = <1>;
393		#size-cells = <2>;
394		#address-cells = <3>;
395		reg = <0xe0008500 0x100		/* internal registers */
396		       0xe0008300 0x8>;		/* config space access registers */
397		compatible = "fsl,mpc8349-pci";
398		device_type = "pci";
399	};
400
401	pci1: pcie@e0009000 {
402		#address-cells = <3>;
403		#size-cells = <2>;
404		#interrupt-cells = <1>;
405		device_type = "pci";
406		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
407		reg = <0xe0009000 0x00001000>;
408		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
409		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
410		bus-range = <0 255>;
411		interrupt-map-mask = <0xf800 0 0 7>;
412		interrupt-map = <0 0 0 1 &ipic 1 8
413				 0 0 0 2 &ipic 1 8
414				 0 0 0 3 &ipic 1 8
415				 0 0 0 4 &ipic 1 8>;
416		sleep = <&pmc 0x00300000>;
417		clock-frequency = <0>;
418
419		pcie@0 {
420			#address-cells = <3>;
421			#size-cells = <2>;
422			device_type = "pci";
423			reg = <0 0 0 0 0>;
424			ranges = <0x02000000 0 0xa8000000
425				  0x02000000 0 0xa8000000
426				  0 0x10000000
427				  0x01000000 0 0x00000000
428				  0x01000000 0 0x00000000
429				  0 0x00800000>;
430		};
431	};
432
433	pci2: pcie@e000a000 {
434		#address-cells = <3>;
435		#size-cells = <2>;
436		#interrupt-cells = <1>;
437		device_type = "pci";
438		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
439		reg = <0xe000a000 0x00001000>;
440		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
441			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
442		bus-range = <0 255>;
443		interrupt-map-mask = <0xf800 0 0 7>;
444		interrupt-map = <0 0 0 1 &ipic 2 8
445				 0 0 0 2 &ipic 2 8
446				 0 0 0 3 &ipic 2 8
447				 0 0 0 4 &ipic 2 8>;
448		sleep = <&pmc 0x000c0000>;
449		clock-frequency = <0>;
450
451		pcie@0 {
452			#address-cells = <3>;
453			#size-cells = <2>;
454			device_type = "pci";
455			reg = <0 0 0 0 0>;
456			ranges = <0x02000000 0 0xc8000000
457				  0x02000000 0 0xc8000000
458				  0 0x10000000
459				  0x01000000 0 0x00000000
460				  0x01000000 0 0x00000000
461				  0 0x00800000>;
462		};
463	};
464};
465