1/*
2 * MPC8377E RDB Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	compatible = "fsl,mpc8377rdb";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		ethernet0 = &enet0;
21		ethernet1 = &enet1;
22		serial0 = &serial0;
23		serial1 = &serial1;
24		pci0 = &pci0;
25		pci1 = &pci1;
26		pci2 = &pci2;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		PowerPC,8377@0 {
34			device_type = "cpu";
35			reg = <0x0>;
36			d-cache-line-size = <32>;
37			i-cache-line-size = <32>;
38			d-cache-size = <32768>;
39			i-cache-size = <32768>;
40			timebase-frequency = <0>;
41			bus-frequency = <0>;
42			clock-frequency = <0>;
43		};
44	};
45
46	memory {
47		device_type = "memory";
48		reg = <0x00000000 0x10000000>;	// 256MB at 0
49	};
50
51	localbus@e0005000 {
52		#address-cells = <2>;
53		#size-cells = <1>;
54		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
55		reg = <0xe0005000 0x1000>;
56		interrupts = <77 0x8>;
57		interrupt-parent = <&ipic>;
58
59		// CS0 and CS1 are swapped when
60		// booting from nand, but the
61		// addresses are the same.
62		ranges = <0x0 0x0 0xfe000000 0x00800000
63		          0x1 0x0 0xe0600000 0x00008000
64		          0x2 0x0 0xf0000000 0x00020000
65		          0x3 0x0 0xfa000000 0x00008000>;
66
67		flash@0,0 {
68			#address-cells = <1>;
69			#size-cells = <1>;
70			compatible = "cfi-flash";
71			reg = <0x0 0x0 0x800000>;
72			bank-width = <2>;
73			device-width = <1>;
74		};
75
76		nand@1,0 {
77			#address-cells = <1>;
78			#size-cells = <1>;
79			compatible = "fsl,mpc8377-fcm-nand",
80			             "fsl,elbc-fcm-nand";
81			reg = <0x1 0x0 0x8000>;
82
83			u-boot@0 {
84				reg = <0x0 0x100000>;
85				read-only;
86			};
87
88			kernel@100000 {
89				reg = <0x100000 0x300000>;
90			};
91			fs@400000 {
92				reg = <0x400000 0x1c00000>;
93			};
94		};
95	};
96
97	immr@e0000000 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		device_type = "soc";
101		compatible = "simple-bus";
102		ranges = <0x0 0xe0000000 0x00100000>;
103		reg = <0xe0000000 0x00000200>;
104		bus-frequency = <0>;
105
106		wdt@200 {
107			device_type = "watchdog";
108			compatible = "mpc83xx_wdt";
109			reg = <0x200 0x100>;
110		};
111
112		i2c@3000 {
113			#address-cells = <1>;
114			#size-cells = <0>;
115			cell-index = <0>;
116			compatible = "fsl-i2c";
117			reg = <0x3000 0x100>;
118			interrupts = <14 0x8>;
119			interrupt-parent = <&ipic>;
120			dfsrr;
121
122			at24@50 {
123				compatible = "at24,24c256";
124				reg = <0x50>;
125			};
126
127			rtc@68 {
128				compatible = "dallas,ds1339";
129				reg = <0x68>;
130			};
131
132			mcu_pio: mcu@a {
133				#gpio-cells = <2>;
134				compatible = "fsl,mc9s08qg8-mpc8377erdb",
135					     "fsl,mcu-mpc8349emitx";
136				reg = <0x0a>;
137				gpio-controller;
138			};
139		};
140
141		i2c@3100 {
142			#address-cells = <1>;
143			#size-cells = <0>;
144			cell-index = <1>;
145			compatible = "fsl-i2c";
146			reg = <0x3100 0x100>;
147			interrupts = <15 0x8>;
148			interrupt-parent = <&ipic>;
149			dfsrr;
150		};
151
152		spi@7000 {
153			cell-index = <0>;
154			compatible = "fsl,spi";
155			reg = <0x7000 0x1000>;
156			interrupts = <16 0x8>;
157			interrupt-parent = <&ipic>;
158			mode = "cpu";
159		};
160
161		dma@82a8 {
162			#address-cells = <1>;
163			#size-cells = <1>;
164			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
165			reg = <0x82a8 4>;
166			ranges = <0 0x8100 0x1a8>;
167			interrupt-parent = <&ipic>;
168			interrupts = <71 8>;
169			cell-index = <0>;
170			dma-channel@0 {
171				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
172				reg = <0 0x80>;
173				cell-index = <0>;
174				interrupt-parent = <&ipic>;
175				interrupts = <71 8>;
176			};
177			dma-channel@80 {
178				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
179				reg = <0x80 0x80>;
180				cell-index = <1>;
181				interrupt-parent = <&ipic>;
182				interrupts = <71 8>;
183			};
184			dma-channel@100 {
185				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
186				reg = <0x100 0x80>;
187				cell-index = <2>;
188				interrupt-parent = <&ipic>;
189				interrupts = <71 8>;
190			};
191			dma-channel@180 {
192				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
193				reg = <0x180 0x28>;
194				cell-index = <3>;
195				interrupt-parent = <&ipic>;
196				interrupts = <71 8>;
197			};
198		};
199
200		usb@23000 {
201			compatible = "fsl-usb2-dr";
202			reg = <0x23000 0x1000>;
203			#address-cells = <1>;
204			#size-cells = <0>;
205			interrupt-parent = <&ipic>;
206			interrupts = <38 0x8>;
207			phy_type = "ulpi";
208		};
209
210		mdio@24520 {
211			#address-cells = <1>;
212			#size-cells = <0>;
213			compatible = "fsl,gianfar-mdio";
214			reg = <0x24520 0x20>;
215			phy2: ethernet-phy@2 {
216				interrupt-parent = <&ipic>;
217				interrupts = <17 0x8>;
218				reg = <0x2>;
219				device_type = "ethernet-phy";
220			};
221			tbi0: tbi-phy@11 {
222				reg = <0x11>;
223				device_type = "tbi-phy";
224			};
225		};
226
227		mdio@25520 {
228			#address-cells = <1>;
229			#size-cells = <0>;
230			compatible = "fsl,gianfar-tbi";
231			reg = <0x25520 0x20>;
232
233			tbi1: tbi-phy@11 {
234				reg = <0x11>;
235				device_type = "tbi-phy";
236			};
237		};
238
239
240		enet0: ethernet@24000 {
241			cell-index = <0>;
242			device_type = "network";
243			model = "eTSEC";
244			compatible = "gianfar";
245			reg = <0x24000 0x1000>;
246			local-mac-address = [ 00 00 00 00 00 00 ];
247			interrupts = <32 0x8 33 0x8 34 0x8>;
248			phy-connection-type = "mii";
249			interrupt-parent = <&ipic>;
250			tbi-handle = <&tbi0>;
251			phy-handle = <&phy2>;
252		};
253
254		enet1: ethernet@25000 {
255			cell-index = <1>;
256			device_type = "network";
257			model = "eTSEC";
258			compatible = "gianfar";
259			reg = <0x25000 0x1000>;
260			local-mac-address = [ 00 00 00 00 00 00 ];
261			interrupts = <35 0x8 36 0x8 37 0x8>;
262			phy-connection-type = "mii";
263			interrupt-parent = <&ipic>;
264			fixed-link = <1 1 1000 0 0>;
265			tbi-handle = <&tbi1>;
266		};
267
268		serial0: serial@4500 {
269			cell-index = <0>;
270			device_type = "serial";
271			compatible = "ns16550";
272			reg = <0x4500 0x100>;
273			clock-frequency = <0>;
274			interrupts = <9 0x8>;
275			interrupt-parent = <&ipic>;
276		};
277
278		serial1: serial@4600 {
279			cell-index = <1>;
280			device_type = "serial";
281			compatible = "ns16550";
282			reg = <0x4600 0x100>;
283			clock-frequency = <0>;
284			interrupts = <10 0x8>;
285			interrupt-parent = <&ipic>;
286		};
287
288		crypto@30000 {
289			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
290				     "fsl,sec2.1", "fsl,sec2.0";
291			reg = <0x30000 0x10000>;
292			interrupts = <11 0x8>;
293			interrupt-parent = <&ipic>;
294			fsl,num-channels = <4>;
295			fsl,channel-fifo-len = <24>;
296			fsl,exec-units-mask = <0x9fe>;
297			fsl,descriptor-types-mask = <0x3ab0ebf>;
298		};
299
300		sata@18000 {
301			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
302			reg = <0x18000 0x1000>;
303			interrupts = <44 0x8>;
304			interrupt-parent = <&ipic>;
305		};
306
307		sata@19000 {
308			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
309			reg = <0x19000 0x1000>;
310			interrupts = <45 0x8>;
311			interrupt-parent = <&ipic>;
312		};
313
314		/* IPIC
315		 * interrupts cell = <intr #, sense>
316		 * sense values match linux IORESOURCE_IRQ_* defines:
317		 * sense == 8: Level, low assertion
318		 * sense == 2: Edge, high-to-low change
319		 */
320		ipic: interrupt-controller@700 {
321			compatible = "fsl,ipic";
322			interrupt-controller;
323			#address-cells = <0>;
324			#interrupt-cells = <2>;
325			reg = <0x700 0x100>;
326		};
327	};
328
329	pci0: pci@e0008500 {
330		interrupt-map-mask = <0xf800 0 0 7>;
331		interrupt-map = <
332				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
333
334				/* IDSEL AD14 IRQ6 inta */
335				 0x7000 0x0 0x0 0x1 &ipic 22 0x8
336
337				/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
338				 0x7800 0x0 0x0 0x1 &ipic 21 0x8
339				 0x7800 0x0 0x0 0x2 &ipic 22 0x8
340				 0x7800 0x0 0x0 0x4 &ipic 23 0x8
341
342				/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
343				 0xE000 0x0 0x0 0x1 &ipic 23 0x8
344				 0xE000 0x0 0x0 0x2 &ipic 21 0x8
345				 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
346		interrupt-parent = <&ipic>;
347		interrupts = <66 0x8>;
348		bus-range = <0 0>;
349		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
350		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
351		          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
352		clock-frequency = <66666666>;
353		#interrupt-cells = <1>;
354		#size-cells = <2>;
355		#address-cells = <3>;
356		reg = <0xe0008500 0x100		/* internal registers */
357		       0xe0008300 0x8>;		/* config space access registers */
358		compatible = "fsl,mpc8349-pci";
359		device_type = "pci";
360	};
361
362	pci1: pcie@e0009000 {
363		#address-cells = <3>;
364		#size-cells = <2>;
365		#interrupt-cells = <1>;
366		device_type = "pci";
367		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
368		reg = <0xe0009000 0x00001000>;
369		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
370		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
371		bus-range = <0 255>;
372		interrupt-map-mask = <0xf800 0 0 7>;
373		interrupt-map = <0 0 0 1 &ipic 1 8
374				 0 0 0 2 &ipic 1 8
375				 0 0 0 3 &ipic 1 8
376				 0 0 0 4 &ipic 1 8>;
377		clock-frequency = <0>;
378
379		pcie@0 {
380			#address-cells = <3>;
381			#size-cells = <2>;
382			device_type = "pci";
383			reg = <0 0 0 0 0>;
384			ranges = <0x02000000 0 0xa8000000
385				  0x02000000 0 0xa8000000
386				  0 0x10000000
387				  0x01000000 0 0x00000000
388				  0x01000000 0 0x00000000
389				  0 0x00800000>;
390		};
391	};
392
393	pci2: pcie@e000a000 {
394		#address-cells = <3>;
395		#size-cells = <2>;
396		#interrupt-cells = <1>;
397		device_type = "pci";
398		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
399		reg = <0xe000a000 0x00001000>;
400		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
401			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
402		bus-range = <0 255>;
403		interrupt-map-mask = <0xf800 0 0 7>;
404		interrupt-map = <0 0 0 1 &ipic 2 8
405				 0 0 0 2 &ipic 2 8
406				 0 0 0 3 &ipic 2 8
407				 0 0 0 4 &ipic 2 8>;
408		clock-frequency = <0>;
409
410		pcie@0 {
411			#address-cells = <3>;
412			#size-cells = <2>;
413			device_type = "pci";
414			reg = <0 0 0 0 0>;
415			ranges = <0x02000000 0 0xc8000000
416				  0x02000000 0 0xc8000000
417				  0 0x10000000
418				  0x01000000 0 0x00000000
419				  0x01000000 0 0x00000000
420				  0 0x00800000>;
421		};
422	};
423};
424