1/* 2 * MPC8360E RDK Device Tree Source 3 * 4 * Copyright 2006 Freescale Semiconductor Inc. 5 * Copyright 2007-2008 MontaVista Software, Inc. 6 * 7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15/dts-v1/; 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 compatible = "fsl,mpc8360rdk"; 21 22 aliases { 23 serial0 = &serial0; 24 serial1 = &serial1; 25 serial2 = &serial2; 26 serial3 = &serial3; 27 ethernet0 = &enet0; 28 ethernet1 = &enet1; 29 ethernet2 = &enet2; 30 ethernet3 = &enet3; 31 pci0 = &pci0; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 PowerPC,8360@0 { 39 device_type = "cpu"; 40 reg = <0>; 41 d-cache-line-size = <32>; 42 i-cache-line-size = <32>; 43 d-cache-size = <32768>; 44 i-cache-size = <32768>; 45 /* filled by u-boot */ 46 timebase-frequency = <0>; 47 bus-frequency = <0>; 48 clock-frequency = <0>; 49 }; 50 }; 51 52 memory { 53 device_type = "memory"; 54 /* filled by u-boot */ 55 reg = <0 0>; 56 }; 57 58 soc@e0000000 { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 device_type = "soc"; 62 compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc", 63 "simple-bus"; 64 ranges = <0 0xe0000000 0x200000>; 65 reg = <0xe0000000 0x200>; 66 /* filled by u-boot */ 67 bus-frequency = <0>; 68 69 wdt@200 { 70 compatible = "mpc83xx_wdt"; 71 reg = <0x200 0x100>; 72 }; 73 74 i2c@3000 { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 cell-index = <0>; 78 compatible = "fsl-i2c"; 79 reg = <0x3000 0x100>; 80 interrupts = <14 8>; 81 interrupt-parent = <&ipic>; 82 dfsrr; 83 }; 84 85 i2c@3100 { 86 #address-cells = <1>; 87 #size-cells = <0>; 88 cell-index = <1>; 89 compatible = "fsl-i2c"; 90 reg = <0x3100 0x100>; 91 interrupts = <16 8>; 92 interrupt-parent = <&ipic>; 93 dfsrr; 94 }; 95 96 serial0: serial@4500 { 97 device_type = "serial"; 98 compatible = "ns16550"; 99 reg = <0x4500 0x100>; 100 interrupts = <9 8>; 101 interrupt-parent = <&ipic>; 102 /* filled by u-boot */ 103 clock-frequency = <0>; 104 }; 105 106 serial1: serial@4600 { 107 device_type = "serial"; 108 compatible = "ns16550"; 109 reg = <0x4600 0x100>; 110 interrupts = <10 8>; 111 interrupt-parent = <&ipic>; 112 /* filled by u-boot */ 113 clock-frequency = <0>; 114 }; 115 116 dma@82a8 { 117 #address-cells = <1>; 118 #size-cells = <1>; 119 compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; 120 reg = <0x82a8 4>; 121 ranges = <0 0x8100 0x1a8>; 122 interrupt-parent = <&ipic>; 123 interrupts = <71 8>; 124 cell-index = <0>; 125 dma-channel@0 { 126 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 127 reg = <0 0x80>; 128 interrupt-parent = <&ipic>; 129 interrupts = <71 8>; 130 }; 131 dma-channel@80 { 132 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 133 reg = <0x80 0x80>; 134 interrupt-parent = <&ipic>; 135 interrupts = <71 8>; 136 }; 137 dma-channel@100 { 138 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 139 reg = <0x100 0x80>; 140 interrupt-parent = <&ipic>; 141 interrupts = <71 8>; 142 }; 143 dma-channel@180 { 144 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 145 reg = <0x180 0x28>; 146 interrupt-parent = <&ipic>; 147 interrupts = <71 8>; 148 }; 149 }; 150 151 crypto@30000 { 152 compatible = "fsl,sec2.0"; 153 reg = <0x30000 0x10000>; 154 interrupts = <11 0x8>; 155 interrupt-parent = <&ipic>; 156 fsl,num-channels = <4>; 157 fsl,channel-fifo-len = <24>; 158 fsl,exec-units-mask = <0x7e>; 159 fsl,descriptor-types-mask = <0x01010ebf>; 160 }; 161 162 ipic: interrupt-controller@700 { 163 #address-cells = <0>; 164 #interrupt-cells = <2>; 165 compatible = "fsl,pq2pro-pic", "fsl,ipic"; 166 interrupt-controller; 167 reg = <0x700 0x100>; 168 }; 169 170 qe_pio_b: gpio-controller@1418 { 171 #gpio-cells = <2>; 172 compatible = "fsl,mpc8360-qe-pario-bank", 173 "fsl,mpc8323-qe-pario-bank"; 174 reg = <0x1418 0x18>; 175 gpio-controller; 176 }; 177 178 qe_pio_e: gpio-controller@1460 { 179 #gpio-cells = <2>; 180 compatible = "fsl,mpc8360-qe-pario-bank", 181 "fsl,mpc8323-qe-pario-bank"; 182 reg = <0x1460 0x18>; 183 gpio-controller; 184 }; 185 186 qe@100000 { 187 #address-cells = <1>; 188 #size-cells = <1>; 189 device_type = "qe"; 190 compatible = "fsl,qe", "simple-bus"; 191 ranges = <0 0x100000 0x100000>; 192 reg = <0x100000 0x480>; 193 /* filled by u-boot */ 194 clock-frequency = <0>; 195 bus-frequency = <0>; 196 brg-frequency = <0>; 197 198 muram@10000 { 199 #address-cells = <1>; 200 #size-cells = <1>; 201 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 202 ranges = <0 0x10000 0xc000>; 203 204 data-only@0 { 205 compatible = "fsl,qe-muram-data", 206 "fsl,cpm-muram-data"; 207 reg = <0 0xc000>; 208 }; 209 }; 210 211 timer@440 { 212 compatible = "fsl,mpc8360-qe-gtm", 213 "fsl,qe-gtm", "fsl,gtm"; 214 reg = <0x440 0x40>; 215 interrupts = <12 13 14 15>; 216 interrupt-parent = <&qeic>; 217 /* filled by u-boot */ 218 clock-frequency = <0>; 219 }; 220 221 spi@4c0 { 222 cell-index = <0>; 223 compatible = "fsl,spi"; 224 reg = <0x4c0 0x40>; 225 interrupts = <2>; 226 interrupt-parent = <&qeic>; 227 mode = "cpu-qe"; 228 }; 229 230 spi@500 { 231 cell-index = <1>; 232 compatible = "fsl,spi"; 233 reg = <0x500 0x40>; 234 interrupts = <1>; 235 interrupt-parent = <&qeic>; 236 mode = "cpu-qe"; 237 }; 238 239 enet0: ucc@2000 { 240 device_type = "network"; 241 compatible = "ucc_geth"; 242 cell-index = <1>; 243 reg = <0x2000 0x200>; 244 interrupts = <32>; 245 interrupt-parent = <&qeic>; 246 rx-clock-name = "none"; 247 tx-clock-name = "clk9"; 248 phy-handle = <&phy2>; 249 phy-connection-type = "rgmii-rxid"; 250 /* filled by u-boot */ 251 local-mac-address = [ 00 00 00 00 00 00 ]; 252 }; 253 254 enet1: ucc@3000 { 255 device_type = "network"; 256 compatible = "ucc_geth"; 257 cell-index = <2>; 258 reg = <0x3000 0x200>; 259 interrupts = <33>; 260 interrupt-parent = <&qeic>; 261 rx-clock-name = "none"; 262 tx-clock-name = "clk4"; 263 phy-handle = <&phy4>; 264 phy-connection-type = "rgmii-rxid"; 265 /* filled by u-boot */ 266 local-mac-address = [ 00 00 00 00 00 00 ]; 267 }; 268 269 enet2: ucc@2600 { 270 device_type = "network"; 271 compatible = "ucc_geth"; 272 cell-index = <7>; 273 reg = <0x2600 0x200>; 274 interrupts = <42>; 275 interrupt-parent = <&qeic>; 276 rx-clock-name = "clk20"; 277 tx-clock-name = "clk19"; 278 phy-handle = <&phy1>; 279 phy-connection-type = "mii"; 280 /* filled by u-boot */ 281 local-mac-address = [ 00 00 00 00 00 00 ]; 282 }; 283 284 enet3: ucc@3200 { 285 device_type = "network"; 286 compatible = "ucc_geth"; 287 cell-index = <4>; 288 reg = <0x3200 0x200>; 289 interrupts = <35>; 290 interrupt-parent = <&qeic>; 291 rx-clock-name = "clk8"; 292 tx-clock-name = "clk7"; 293 phy-handle = <&phy3>; 294 phy-connection-type = "mii"; 295 /* filled by u-boot */ 296 local-mac-address = [ 00 00 00 00 00 00 ]; 297 }; 298 299 mdio@2120 { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 compatible = "fsl,ucc-mdio"; 303 reg = <0x2120 0x18>; 304 305 phy1: ethernet-phy@1 { 306 device_type = "ethernet-phy"; 307 compatible = "national,DP83848VV"; 308 reg = <1>; 309 }; 310 311 phy2: ethernet-phy@2 { 312 device_type = "ethernet-phy"; 313 compatible = "broadcom,BCM5481UA2KMLG"; 314 reg = <2>; 315 }; 316 317 phy3: ethernet-phy@3 { 318 device_type = "ethernet-phy"; 319 compatible = "national,DP83848VV"; 320 reg = <3>; 321 }; 322 323 phy4: ethernet-phy@4 { 324 device_type = "ethernet-phy"; 325 compatible = "broadcom,BCM5481UA2KMLG"; 326 reg = <4>; 327 }; 328 }; 329 330 serial2: ucc@2400 { 331 device_type = "serial"; 332 compatible = "ucc_uart"; 333 reg = <0x2400 0x200>; 334 cell-index = <5>; 335 port-number = <0>; 336 rx-clock-name = "brg7"; 337 tx-clock-name = "brg8"; 338 interrupts = <40>; 339 interrupt-parent = <&qeic>; 340 soft-uart; 341 }; 342 343 serial3: ucc@3400 { 344 device_type = "serial"; 345 compatible = "ucc_uart"; 346 reg = <0x3400 0x200>; 347 cell-index = <6>; 348 port-number = <1>; 349 rx-clock-name = "brg13"; 350 tx-clock-name = "brg14"; 351 interrupts = <41>; 352 interrupt-parent = <&qeic>; 353 soft-uart; 354 }; 355 356 qeic: interrupt-controller@80 { 357 #address-cells = <0>; 358 #interrupt-cells = <1>; 359 compatible = "fsl,qe-ic"; 360 interrupt-controller; 361 reg = <0x80 0x80>; 362 big-endian; 363 interrupts = <32 8 33 8>; 364 interrupt-parent = <&ipic>; 365 }; 366 }; 367 }; 368 369 localbus@e0005000 { 370 #address-cells = <2>; 371 #size-cells = <1>; 372 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", 373 "simple-bus"; 374 reg = <0xe0005000 0xd8>; 375 ranges = <0 0 0xff800000 0x0800000 376 1 0 0x60000000 0x0001000 377 2 0 0x70000000 0x4000000>; 378 379 flash@0,0 { 380 compatible = "intel,PC28F640P30T85", "cfi-flash"; 381 reg = <0 0 0x800000>; 382 bank-width = <2>; 383 device-width = <1>; 384 }; 385 386 display@2,0 { 387 device_type = "display"; 388 compatible = "fujitsu,MB86277", "fujitsu,mint"; 389 reg = <2 0 0x4000000>; 390 fujitsu,sh3; 391 little-endian; 392 /* filled by u-boot */ 393 address = <0>; 394 depth = <0>; 395 width = <0>; 396 height = <0>; 397 linebytes = <0>; 398 /* linux,opened; - added by uboot */ 399 }; 400 }; 401 402 pci0: pci@e0008500 { 403 #address-cells = <3>; 404 #size-cells = <2>; 405 #interrupt-cells = <1>; 406 device_type = "pci"; 407 compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci"; 408 reg = <0xe0008500 0x100>; 409 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 410 0x42000000 0 0x80000000 0x80000000 0 0x10000000 411 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>; 412 interrupts = <66 8>; 413 interrupt-parent = <&ipic>; 414 interrupt-map-mask = <0xf800 0 0 7>; 415 interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */ 416 0xa000 0 0 1 &ipic 18 8 417 0xa000 0 0 2 &ipic 19 8 418 419 /* PCI1 IDSEL 0x15 AD21 */ 420 0xa800 0 0 1 &ipic 19 8 421 0xa800 0 0 2 &ipic 20 8 422 0xa800 0 0 3 &ipic 21 8 423 0xa800 0 0 4 &ipic 18 8>; 424 /* filled by u-boot */ 425 bus-range = <0 0>; 426 clock-frequency = <0>; 427 }; 428}; 429