1/*
2 * MPC8360E RDK Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2007-2008 MontaVista Software, Inc.
6 *
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 *
9 * This program is free software; you can redistribute  it and/or modify it
10 * under  the terms of  the GNU General  Public License as published by the
11 * Free Software Foundation;  either version 2 of the  License, or (at your
12 * option) any later version.
13 */
14
15/dts-v1/;
16
17/ {
18	#address-cells = <1>;
19	#size-cells = <1>;
20	compatible = "fsl,mpc8360rdk";
21
22	aliases {
23		serial0 = &serial0;
24		serial1 = &serial1;
25		serial2 = &serial2;
26		serial3 = &serial3;
27		ethernet0 = &enet0;
28		ethernet1 = &enet1;
29		ethernet2 = &enet2;
30		ethernet3 = &enet3;
31		pci0 = &pci0;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		PowerPC,8360@0 {
39			device_type = "cpu";
40			reg = <0>;
41			d-cache-line-size = <32>;
42			i-cache-line-size = <32>;
43			d-cache-size = <32768>;
44			i-cache-size = <32768>;
45			/* filled by u-boot */
46			timebase-frequency = <0>;
47			bus-frequency = <0>;
48			clock-frequency = <0>;
49		};
50	};
51
52	memory {
53		device_type = "memory";
54		/* filled by u-boot */
55		reg = <0 0>;
56	};
57
58	soc@e0000000 {
59		#address-cells = <1>;
60		#size-cells = <1>;
61		device_type = "soc";
62		compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc",
63			     "simple-bus";
64		ranges = <0 0xe0000000 0x200000>;
65		reg = <0xe0000000 0x200>;
66		/* filled by u-boot */
67		bus-frequency = <0>;
68
69		wdt@200 {
70			compatible = "mpc83xx_wdt";
71			reg = <0x200 0x100>;
72		};
73
74		i2c@3000 {
75			#address-cells = <1>;
76			#size-cells = <0>;
77			cell-index = <0>;
78			compatible = "fsl-i2c";
79			reg = <0x3000 0x100>;
80			interrupts = <14 8>;
81			interrupt-parent = <&ipic>;
82			dfsrr;
83		};
84
85		i2c@3100 {
86			#address-cells = <1>;
87			#size-cells = <0>;
88			cell-index = <1>;
89			compatible = "fsl-i2c";
90			reg = <0x3100 0x100>;
91			interrupts = <16 8>;
92			interrupt-parent = <&ipic>;
93			dfsrr;
94		};
95
96		serial0: serial@4500 {
97			device_type = "serial";
98			compatible = "ns16550";
99			reg = <0x4500 0x100>;
100			interrupts = <9 8>;
101			interrupt-parent = <&ipic>;
102			/* filled by u-boot */
103			clock-frequency = <0>;
104		};
105
106		serial1: serial@4600 {
107			device_type = "serial";
108			compatible = "ns16550";
109			reg = <0x4600 0x100>;
110			interrupts = <10 8>;
111			interrupt-parent = <&ipic>;
112			/* filled by u-boot */
113			clock-frequency = <0>;
114		};
115
116		crypto@30000 {
117			compatible = "fsl,sec2-crypto";
118			reg = <0x30000 0x10000>;
119			interrupts = <11 8>;
120			interrupt-parent = <&ipic>;
121			num-channels = <4>;
122			channel-fifo-len = <24>;
123			exec-units-mask = <0x7e>;
124			/*
125			 * desc mask is for rev1.x, we need runtime fixup
126			 * for >=2.x
127			 */
128			descriptor-types-mask = <0x1010ebf>;
129		};
130
131		ipic: interrupt-controller@700 {
132			#address-cells = <0>;
133			#interrupt-cells = <2>;
134			compatible = "fsl,pq2pro-pic", "fsl,ipic";
135			interrupt-controller;
136			reg = <0x700 0x100>;
137		};
138
139		qe_pio_b: gpio-controller@1418 {
140			#gpio-cells = <2>;
141			compatible = "fsl,mpc8360-qe-pario-bank",
142				     "fsl,mpc8323-qe-pario-bank";
143			reg = <0x1418 0x18>;
144			gpio-controller;
145		};
146
147		qe_pio_e: gpio-controller@1460 {
148			#gpio-cells = <2>;
149			compatible = "fsl,mpc8360-qe-pario-bank",
150				     "fsl,mpc8323-qe-pario-bank";
151			reg = <0x1460 0x18>;
152			gpio-controller;
153		};
154
155		qe@100000 {
156			#address-cells = <1>;
157			#size-cells = <1>;
158			device_type = "qe";
159			compatible = "fsl,qe", "simple-bus";
160			ranges = <0 0x100000 0x100000>;
161			reg = <0x100000 0x480>;
162			/* filled by u-boot */
163			clock-frequency = <0>;
164			bus-frequency = <0>;
165			brg-frequency = <0>;
166
167			muram@10000 {
168				#address-cells = <1>;
169				#size-cells = <1>;
170				compatible = "fsl,qe-muram", "fsl,cpm-muram";
171				ranges = <0 0x10000 0xc000>;
172
173				data-only@0 {
174					compatible = "fsl,qe-muram-data",
175						     "fsl,cpm-muram-data";
176					reg = <0 0xc000>;
177				};
178			};
179
180			timer@440 {
181				compatible = "fsl,mpc8360-qe-gtm",
182					     "fsl,qe-gtm", "fsl,gtm";
183				reg = <0x440 0x40>;
184				interrupts = <12 13 14 15>;
185				interrupt-parent = <&qeic>;
186				/* filled by u-boot */
187				clock-frequency = <0>;
188			};
189
190			spi@4c0 {
191				cell-index = <0>;
192				compatible = "fsl,spi";
193				reg = <0x4c0 0x40>;
194				interrupts = <2>;
195				interrupt-parent = <&qeic>;
196				mode = "cpu-qe";
197			};
198
199			spi@500 {
200				cell-index = <1>;
201				compatible = "fsl,spi";
202				reg = <0x500 0x40>;
203				interrupts = <1>;
204				interrupt-parent = <&qeic>;
205				mode = "cpu-qe";
206			};
207
208			enet0: ucc@2000 {
209				device_type = "network";
210				compatible = "ucc_geth";
211				cell-index = <1>;
212				reg = <0x2000 0x200>;
213				interrupts = <32>;
214				interrupt-parent = <&qeic>;
215				rx-clock-name = "none";
216				tx-clock-name = "clk9";
217				phy-handle = <&phy2>;
218				phy-connection-type = "rgmii-rxid";
219				/* filled by u-boot */
220				local-mac-address = [ 00 00 00 00 00 00 ];
221			};
222
223			enet1: ucc@3000 {
224				device_type = "network";
225				compatible = "ucc_geth";
226				cell-index = <2>;
227				reg = <0x3000 0x200>;
228				interrupts = <33>;
229				interrupt-parent = <&qeic>;
230				rx-clock-name = "none";
231				tx-clock-name = "clk4";
232				phy-handle = <&phy4>;
233				phy-connection-type = "rgmii-rxid";
234				/* filled by u-boot */
235				local-mac-address = [ 00 00 00 00 00 00 ];
236			};
237
238			enet2: ucc@2600 {
239				device_type = "network";
240				compatible = "ucc_geth";
241				cell-index = <7>;
242				reg = <0x2600 0x200>;
243				interrupts = <42>;
244				interrupt-parent = <&qeic>;
245				rx-clock-name = "clk20";
246				tx-clock-name = "clk19";
247				phy-handle = <&phy1>;
248				phy-connection-type = "mii";
249				/* filled by u-boot */
250				local-mac-address = [ 00 00 00 00 00 00 ];
251			};
252
253			enet3: ucc@3200 {
254				device_type = "network";
255				compatible = "ucc_geth";
256				cell-index = <4>;
257				reg = <0x3200 0x200>;
258				interrupts = <35>;
259				interrupt-parent = <&qeic>;
260				rx-clock-name = "clk8";
261				tx-clock-name = "clk7";
262				phy-handle = <&phy3>;
263				phy-connection-type = "mii";
264				/* filled by u-boot */
265				local-mac-address = [ 00 00 00 00 00 00 ];
266			};
267
268			mdio@2120 {
269				#address-cells = <1>;
270				#size-cells = <0>;
271				compatible = "fsl,ucc-mdio";
272				reg = <0x2120 0x18>;
273
274				phy1: ethernet-phy@1 {
275					device_type = "ethernet-phy";
276					compatible = "national,DP83848VV";
277					reg = <1>;
278				};
279
280				phy2: ethernet-phy@2 {
281					device_type = "ethernet-phy";
282					compatible = "broadcom,BCM5481UA2KMLG";
283					reg = <2>;
284				};
285
286				phy3: ethernet-phy@3 {
287					device_type = "ethernet-phy";
288					compatible = "national,DP83848VV";
289					reg = <3>;
290				};
291
292				phy4: ethernet-phy@4 {
293					device_type = "ethernet-phy";
294					compatible = "broadcom,BCM5481UA2KMLG";
295					reg = <4>;
296				};
297			};
298
299			serial2: ucc@2400 {
300				device_type = "serial";
301				compatible = "ucc_uart";
302				reg = <0x2400 0x200>;
303				cell-index = <5>;
304				port-number = <0>;
305				rx-clock-name = "brg7";
306				tx-clock-name = "brg8";
307				interrupts = <40>;
308				interrupt-parent = <&qeic>;
309				soft-uart;
310			};
311
312			serial3: ucc@3400 {
313				device_type = "serial";
314				compatible = "ucc_uart";
315				reg = <0x3400 0x200>;
316				cell-index = <6>;
317				port-number = <1>;
318				rx-clock-name = "brg13";
319				tx-clock-name = "brg14";
320				interrupts = <41>;
321				interrupt-parent = <&qeic>;
322				soft-uart;
323			};
324
325			qeic: interrupt-controller@80 {
326				#address-cells = <0>;
327				#interrupt-cells = <1>;
328				compatible = "fsl,qe-ic";
329				interrupt-controller;
330				reg = <0x80 0x80>;
331				big-endian;
332				interrupts = <32 8 33 8>;
333				interrupt-parent = <&ipic>;
334			};
335		};
336	};
337
338	localbus@e0005000 {
339		#address-cells = <2>;
340		#size-cells = <1>;
341		compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
342			     "simple-bus";
343		reg = <0xe0005000 0xd8>;
344		ranges = <0 0 0xff800000 0x0800000
345			  1 0 0x60000000 0x0001000
346			  2 0 0x70000000 0x4000000>;
347
348		flash@0,0 {
349			compatible = "intel,PC28F640P30T85", "cfi-flash";
350			reg = <0 0 0x800000>;
351			bank-width = <2>;
352			device-width = <1>;
353		};
354
355		display@2,0 {
356			device_type = "display";
357			compatible = "fujitsu,MB86277", "fujitsu,mint";
358			reg = <2 0 0x4000000>;
359			fujitsu,sh3;
360			little-endian;
361			/* filled by u-boot */
362			address = <0>;
363			depth = <0>;
364			width = <0>;
365			height = <0>;
366			linebytes = <0>;
367			/* linux,opened; - added by uboot */
368		};
369	};
370
371	pci0: pci@e0008500 {
372		#address-cells = <3>;
373		#size-cells = <2>;
374		#interrupt-cells = <1>;
375		device_type = "pci";
376		compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci";
377		reg = <0xe0008500 0x100>;
378		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
379			  0x42000000 0 0x80000000 0x80000000 0 0x10000000
380			  0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>;
381		interrupts = <66 8>;
382		interrupt-parent = <&ipic>;
383		interrupt-map-mask = <0xf800 0 0 7>;
384		interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */
385				 0xa000 0 0 1 &ipic 18 8
386				 0xa000 0 0 2 &ipic 19 8
387
388				 /* PCI1 IDSEL 0x15 AD21 */
389				 0xa800 0 0 1 &ipic 19 8
390				 0xa800 0 0 2 &ipic 20 8
391				 0xa800 0 0 3 &ipic 21 8
392				 0xa800 0 0 4 &ipic 18 8>;
393		/* filled by u-boot */
394		bus-range = <0 0>;
395		clock-frequency = <0>;
396	};
397};
398