1/*
2 * MPC8360E RDK Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2007-2008 MontaVista Software, Inc.
6 *
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 *
9 * This program is free software; you can redistribute  it and/or modify it
10 * under  the terms of  the GNU General  Public License as published by the
11 * Free Software Foundation;  either version 2 of the  License, or (at your
12 * option) any later version.
13 */
14
15/dts-v1/;
16
17/ {
18	#address-cells = <1>;
19	#size-cells = <1>;
20	compatible = "fsl,mpc8360rdk";
21
22	aliases {
23		serial0 = &serial0;
24		serial1 = &serial1;
25		serial2 = &serial2;
26		serial3 = &serial3;
27		ethernet0 = &enet0;
28		ethernet1 = &enet1;
29		ethernet2 = &enet2;
30		ethernet3 = &enet3;
31		pci0 = &pci0;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		PowerPC,8360@0 {
39			device_type = "cpu";
40			reg = <0>;
41			d-cache-line-size = <32>;
42			i-cache-line-size = <32>;
43			d-cache-size = <32768>;
44			i-cache-size = <32768>;
45			/* filled by u-boot */
46			timebase-frequency = <0>;
47			bus-frequency = <0>;
48			clock-frequency = <0>;
49		};
50	};
51
52	memory {
53		device_type = "memory";
54		/* filled by u-boot */
55		reg = <0 0>;
56	};
57
58	soc@e0000000 {
59		#address-cells = <1>;
60		#size-cells = <1>;
61		device_type = "soc";
62		compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc",
63			     "simple-bus";
64		ranges = <0 0xe0000000 0x200000>;
65		reg = <0xe0000000 0x200>;
66		/* filled by u-boot */
67		bus-frequency = <0>;
68
69		wdt@200 {
70			compatible = "mpc83xx_wdt";
71			reg = <0x200 0x100>;
72		};
73
74		i2c@3000 {
75			#address-cells = <1>;
76			#size-cells = <0>;
77			cell-index = <0>;
78			compatible = "fsl-i2c";
79			reg = <0x3000 0x100>;
80			interrupts = <14 8>;
81			interrupt-parent = <&ipic>;
82			dfsrr;
83		};
84
85		i2c@3100 {
86			#address-cells = <1>;
87			#size-cells = <0>;
88			cell-index = <1>;
89			compatible = "fsl-i2c";
90			reg = <0x3100 0x100>;
91			interrupts = <16 8>;
92			interrupt-parent = <&ipic>;
93			dfsrr;
94		};
95
96		serial0: serial@4500 {
97			device_type = "serial";
98			compatible = "ns16550";
99			reg = <0x4500 0x100>;
100			interrupts = <9 8>;
101			interrupt-parent = <&ipic>;
102			/* filled by u-boot */
103			clock-frequency = <0>;
104		};
105
106		serial1: serial@4600 {
107			device_type = "serial";
108			compatible = "ns16550";
109			reg = <0x4600 0x100>;
110			interrupts = <10 8>;
111			interrupt-parent = <&ipic>;
112			/* filled by u-boot */
113			clock-frequency = <0>;
114		};
115
116		dma@82a8 {
117			#address-cells = <1>;
118			#size-cells = <1>;
119			compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
120			reg = <0x82a8 4>;
121			ranges = <0 0x8100 0x1a8>;
122			interrupt-parent = <&ipic>;
123			interrupts = <71 8>;
124			cell-index = <0>;
125			dma-channel@0 {
126				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
127				reg = <0 0x80>;
128				cell-index = <0>;
129				interrupt-parent = <&ipic>;
130				interrupts = <71 8>;
131			};
132			dma-channel@80 {
133				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
134				reg = <0x80 0x80>;
135				cell-index = <1>;
136				interrupt-parent = <&ipic>;
137				interrupts = <71 8>;
138			};
139			dma-channel@100 {
140				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
141				reg = <0x100 0x80>;
142				cell-index = <2>;
143				interrupt-parent = <&ipic>;
144				interrupts = <71 8>;
145			};
146			dma-channel@180 {
147				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
148				reg = <0x180 0x28>;
149				cell-index = <3>;
150				interrupt-parent = <&ipic>;
151				interrupts = <71 8>;
152			};
153		};
154
155		crypto@30000 {
156			compatible = "fsl,sec2.0";
157			reg = <0x30000 0x10000>;
158			interrupts = <11 0x8>;
159			interrupt-parent = <&ipic>;
160			fsl,num-channels = <4>;
161			fsl,channel-fifo-len = <24>;
162			fsl,exec-units-mask = <0x7e>;
163			fsl,descriptor-types-mask = <0x01010ebf>;
164		};
165
166		ipic: interrupt-controller@700 {
167			#address-cells = <0>;
168			#interrupt-cells = <2>;
169			compatible = "fsl,pq2pro-pic", "fsl,ipic";
170			interrupt-controller;
171			reg = <0x700 0x100>;
172		};
173
174		qe_pio_b: gpio-controller@1418 {
175			#gpio-cells = <2>;
176			compatible = "fsl,mpc8360-qe-pario-bank",
177				     "fsl,mpc8323-qe-pario-bank";
178			reg = <0x1418 0x18>;
179			gpio-controller;
180		};
181
182		qe_pio_e: gpio-controller@1460 {
183			#gpio-cells = <2>;
184			compatible = "fsl,mpc8360-qe-pario-bank",
185				     "fsl,mpc8323-qe-pario-bank";
186			reg = <0x1460 0x18>;
187			gpio-controller;
188		};
189
190		qe@100000 {
191			#address-cells = <1>;
192			#size-cells = <1>;
193			device_type = "qe";
194			compatible = "fsl,qe", "simple-bus";
195			ranges = <0 0x100000 0x100000>;
196			reg = <0x100000 0x480>;
197			/* filled by u-boot */
198			clock-frequency = <0>;
199			bus-frequency = <0>;
200			brg-frequency = <0>;
201			fsl,qe-num-riscs = <2>;
202			fsl,qe-num-snums = <28>;
203
204			muram@10000 {
205				#address-cells = <1>;
206				#size-cells = <1>;
207				compatible = "fsl,qe-muram", "fsl,cpm-muram";
208				ranges = <0 0x10000 0xc000>;
209
210				data-only@0 {
211					compatible = "fsl,qe-muram-data",
212						     "fsl,cpm-muram-data";
213					reg = <0 0xc000>;
214				};
215			};
216
217			timer@440 {
218				compatible = "fsl,mpc8360-qe-gtm",
219					     "fsl,qe-gtm", "fsl,gtm";
220				reg = <0x440 0x40>;
221				interrupts = <12 13 14 15>;
222				interrupt-parent = <&qeic>;
223				clock-frequency = <166666666>;
224			};
225
226			usb@6c0 {
227				compatible = "fsl,mpc8360-qe-usb",
228					     "fsl,mpc8323-qe-usb";
229				reg = <0x6c0 0x40 0x8b00 0x100>;
230				interrupts = <11>;
231				interrupt-parent = <&qeic>;
232				fsl,fullspeed-clock = "clk21";
233				gpios = <&qe_pio_b  2 0 /* USBOE */
234					 &qe_pio_b  3 0 /* USBTP */
235					 &qe_pio_b  8 0 /* USBTN */
236					 &qe_pio_b  9 0 /* USBRP */
237					 &qe_pio_b 11 0 /* USBRN */
238					 &qe_pio_e 20 0 /* SPEED */
239					 &qe_pio_e 21 1 /* POWER */>;
240			};
241
242			spi@4c0 {
243				cell-index = <0>;
244				compatible = "fsl,spi";
245				reg = <0x4c0 0x40>;
246				interrupts = <2>;
247				interrupt-parent = <&qeic>;
248				mode = "cpu-qe";
249			};
250
251			spi@500 {
252				cell-index = <1>;
253				compatible = "fsl,spi";
254				reg = <0x500 0x40>;
255				interrupts = <1>;
256				interrupt-parent = <&qeic>;
257				mode = "cpu-qe";
258			};
259
260			enet0: ucc@2000 {
261				device_type = "network";
262				compatible = "ucc_geth";
263				cell-index = <1>;
264				reg = <0x2000 0x200>;
265				interrupts = <32>;
266				interrupt-parent = <&qeic>;
267				rx-clock-name = "none";
268				tx-clock-name = "clk9";
269				phy-handle = <&phy2>;
270				phy-connection-type = "rgmii-rxid";
271				/* filled by u-boot */
272				local-mac-address = [ 00 00 00 00 00 00 ];
273			};
274
275			enet1: ucc@3000 {
276				device_type = "network";
277				compatible = "ucc_geth";
278				cell-index = <2>;
279				reg = <0x3000 0x200>;
280				interrupts = <33>;
281				interrupt-parent = <&qeic>;
282				rx-clock-name = "none";
283				tx-clock-name = "clk4";
284				phy-handle = <&phy4>;
285				phy-connection-type = "rgmii-rxid";
286				/* filled by u-boot */
287				local-mac-address = [ 00 00 00 00 00 00 ];
288			};
289
290			enet2: ucc@2600 {
291				device_type = "network";
292				compatible = "ucc_geth";
293				cell-index = <7>;
294				reg = <0x2600 0x200>;
295				interrupts = <42>;
296				interrupt-parent = <&qeic>;
297				rx-clock-name = "clk20";
298				tx-clock-name = "clk19";
299				phy-handle = <&phy1>;
300				phy-connection-type = "mii";
301				/* filled by u-boot */
302				local-mac-address = [ 00 00 00 00 00 00 ];
303			};
304
305			enet3: ucc@3200 {
306				device_type = "network";
307				compatible = "ucc_geth";
308				cell-index = <4>;
309				reg = <0x3200 0x200>;
310				interrupts = <35>;
311				interrupt-parent = <&qeic>;
312				rx-clock-name = "clk8";
313				tx-clock-name = "clk7";
314				phy-handle = <&phy3>;
315				phy-connection-type = "mii";
316				/* filled by u-boot */
317				local-mac-address = [ 00 00 00 00 00 00 ];
318			};
319
320			mdio@2120 {
321				#address-cells = <1>;
322				#size-cells = <0>;
323				compatible = "fsl,ucc-mdio";
324				reg = <0x2120 0x18>;
325
326				phy1: ethernet-phy@1 {
327					device_type = "ethernet-phy";
328					compatible = "national,DP83848VV";
329					reg = <1>;
330				};
331
332				phy2: ethernet-phy@2 {
333					device_type = "ethernet-phy";
334					compatible = "broadcom,BCM5481UA2KMLG";
335					reg = <2>;
336				};
337
338				phy3: ethernet-phy@3 {
339					device_type = "ethernet-phy";
340					compatible = "national,DP83848VV";
341					reg = <3>;
342				};
343
344				phy4: ethernet-phy@4 {
345					device_type = "ethernet-phy";
346					compatible = "broadcom,BCM5481UA2KMLG";
347					reg = <4>;
348				};
349			};
350
351			serial2: ucc@2400 {
352				device_type = "serial";
353				compatible = "ucc_uart";
354				reg = <0x2400 0x200>;
355				cell-index = <5>;
356				port-number = <0>;
357				rx-clock-name = "brg7";
358				tx-clock-name = "brg8";
359				interrupts = <40>;
360				interrupt-parent = <&qeic>;
361				soft-uart;
362			};
363
364			serial3: ucc@3400 {
365				device_type = "serial";
366				compatible = "ucc_uart";
367				reg = <0x3400 0x200>;
368				cell-index = <6>;
369				port-number = <1>;
370				rx-clock-name = "brg13";
371				tx-clock-name = "brg14";
372				interrupts = <41>;
373				interrupt-parent = <&qeic>;
374				soft-uart;
375			};
376
377			qeic: interrupt-controller@80 {
378				#address-cells = <0>;
379				#interrupt-cells = <1>;
380				compatible = "fsl,qe-ic";
381				interrupt-controller;
382				reg = <0x80 0x80>;
383				big-endian;
384				interrupts = <32 8 33 8>;
385				interrupt-parent = <&ipic>;
386			};
387		};
388	};
389
390	localbus@e0005000 {
391		#address-cells = <2>;
392		#size-cells = <1>;
393		compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
394			     "simple-bus";
395		reg = <0xe0005000 0xd8>;
396		ranges = <0 0 0xff800000 0x0800000
397			  1 0 0x60000000 0x0001000
398			  2 0 0x70000000 0x4000000>;
399
400		flash@0,0 {
401			compatible = "intel,PC28F640P30T85", "cfi-flash";
402			reg = <0 0 0x800000>;
403			bank-width = <2>;
404			device-width = <1>;
405		};
406
407		upm@1,0 {
408			compatible = "fsl,upm-nand";
409			reg = <1 0 1>;
410			fsl,upm-addr-offset = <16>;
411			fsl,upm-cmd-offset = <8>;
412			gpios = <&qe_pio_e 18 0>;
413
414			flash {
415				compatible = "stm,nand512-a";
416			};
417		};
418
419		display@2,0 {
420			device_type = "display";
421			compatible = "fujitsu,MB86277", "fujitsu,mint";
422			reg = <2 0 0x4000000>;
423			fujitsu,sh3;
424			little-endian;
425			/* filled by u-boot */
426			address = <0>;
427			depth = <0>;
428			width = <0>;
429			height = <0>;
430			linebytes = <0>;
431			/* linux,opened; - added by uboot */
432		};
433	};
434
435	pci0: pci@e0008500 {
436		#address-cells = <3>;
437		#size-cells = <2>;
438		#interrupt-cells = <1>;
439		device_type = "pci";
440		compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci";
441		reg = <0xe0008500 0x100		/* internal registers */
442		       0xe0008300 0x8>;		/* config space access registers */
443		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
444			  0x42000000 0 0x80000000 0x80000000 0 0x10000000
445			  0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>;
446		interrupts = <66 8>;
447		interrupt-parent = <&ipic>;
448		interrupt-map-mask = <0xf800 0 0 7>;
449		interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */
450				 0xa000 0 0 1 &ipic 18 8
451				 0xa000 0 0 2 &ipic 19 8
452
453				 /* PCI1 IDSEL 0x15 AD21 */
454				 0xa800 0 0 1 &ipic 19 8
455				 0xa800 0 0 2 &ipic 20 8
456				 0xa800 0 0 3 &ipic 21 8
457				 0xa800 0 0 4 &ipic 18 8>;
458		/* filled by u-boot */
459		bus-range = <0 0>;
460		clock-frequency = <0>;
461	};
462};
463