1/* 2 * MPC8349E-mITX Device Tree Source 3 * 4 * Copyright 2006 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "MPC8349EMITX"; 16 compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 pci1 = &pci1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 PowerPC,8349@0 { 34 device_type = "cpu"; 35 reg = <0x0>; 36 d-cache-line-size = <32>; 37 i-cache-line-size = <32>; 38 d-cache-size = <32768>; 39 i-cache-size = <32768>; 40 timebase-frequency = <0>; // from bootloader 41 bus-frequency = <0>; // from bootloader 42 clock-frequency = <0>; // from bootloader 43 }; 44 }; 45 46 memory { 47 device_type = "memory"; 48 reg = <0x00000000 0x10000000>; 49 }; 50 51 soc8349@e0000000 { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 device_type = "soc"; 55 compatible = "simple-bus"; 56 ranges = <0x0 0xe0000000 0x00100000>; 57 reg = <0xe0000000 0x00000200>; 58 bus-frequency = <0>; // from bootloader 59 60 wdt@200 { 61 device_type = "watchdog"; 62 compatible = "mpc83xx_wdt"; 63 reg = <0x200 0x100>; 64 }; 65 66 i2c@3000 { 67 #address-cells = <1>; 68 #size-cells = <0>; 69 cell-index = <0>; 70 compatible = "fsl-i2c"; 71 reg = <0x3000 0x100>; 72 interrupts = <14 0x8>; 73 interrupt-parent = <&ipic>; 74 dfsrr; 75 }; 76 77 i2c@3100 { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 cell-index = <1>; 81 compatible = "fsl-i2c"; 82 reg = <0x3100 0x100>; 83 interrupts = <15 0x8>; 84 interrupt-parent = <&ipic>; 85 dfsrr; 86 87 rtc@68 { 88 compatible = "dallas,ds1339"; 89 reg = <0x68>; 90 interrupts = <18 0x8>; 91 interrupt-parent = <&ipic>; 92 }; 93 }; 94 95 spi@7000 { 96 cell-index = <0>; 97 compatible = "fsl,spi"; 98 reg = <0x7000 0x1000>; 99 interrupts = <16 0x8>; 100 interrupt-parent = <&ipic>; 101 mode = "cpu"; 102 }; 103 104 dma@82a8 { 105 #address-cells = <1>; 106 #size-cells = <1>; 107 compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; 108 reg = <0x82a8 4>; 109 ranges = <0 0x8100 0x1a8>; 110 interrupt-parent = <&ipic>; 111 interrupts = <71 8>; 112 cell-index = <0>; 113 dma-channel@0 { 114 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 115 reg = <0 0x80>; 116 cell-index = <0>; 117 interrupt-parent = <&ipic>; 118 interrupts = <71 8>; 119 }; 120 dma-channel@80 { 121 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 122 reg = <0x80 0x80>; 123 cell-index = <1>; 124 interrupt-parent = <&ipic>; 125 interrupts = <71 8>; 126 }; 127 dma-channel@100 { 128 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 129 reg = <0x100 0x80>; 130 cell-index = <2>; 131 interrupt-parent = <&ipic>; 132 interrupts = <71 8>; 133 }; 134 dma-channel@180 { 135 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 136 reg = <0x180 0x28>; 137 cell-index = <3>; 138 interrupt-parent = <&ipic>; 139 interrupts = <71 8>; 140 }; 141 142 mcu_pio: mcu@a { 143 #gpio-cells = <2>; 144 compatible = "fsl,mc9s08qg8-mpc8349emitx", 145 "fsl,mcu-mpc8349emitx"; 146 reg = <0x0a>; 147 gpio-controller; 148 }; 149 }; 150 151 usb@22000 { 152 compatible = "fsl-usb2-mph"; 153 reg = <0x22000 0x1000>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 interrupt-parent = <&ipic>; 157 interrupts = <39 0x8>; 158 phy_type = "ulpi"; 159 port1; 160 }; 161 162 usb@23000 { 163 compatible = "fsl-usb2-dr"; 164 reg = <0x23000 0x1000>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 interrupt-parent = <&ipic>; 168 interrupts = <38 0x8>; 169 dr_mode = "peripheral"; 170 phy_type = "ulpi"; 171 }; 172 173 mdio@24520 { 174 #address-cells = <1>; 175 #size-cells = <0>; 176 compatible = "fsl,gianfar-mdio"; 177 reg = <0x24520 0x20>; 178 179 /* Vitesse 8201 */ 180 phy1c: ethernet-phy@1c { 181 interrupt-parent = <&ipic>; 182 interrupts = <18 0x8>; 183 reg = <0x1c>; 184 device_type = "ethernet-phy"; 185 }; 186 }; 187 188 enet0: ethernet@24000 { 189 cell-index = <0>; 190 device_type = "network"; 191 model = "TSEC"; 192 compatible = "gianfar"; 193 reg = <0x24000 0x1000>; 194 local-mac-address = [ 00 00 00 00 00 00 ]; 195 interrupts = <32 0x8 33 0x8 34 0x8>; 196 interrupt-parent = <&ipic>; 197 phy-handle = <&phy1c>; 198 linux,network-index = <0>; 199 }; 200 201 enet1: ethernet@25000 { 202 cell-index = <1>; 203 device_type = "network"; 204 model = "TSEC"; 205 compatible = "gianfar"; 206 reg = <0x25000 0x1000>; 207 local-mac-address = [ 00 00 00 00 00 00 ]; 208 interrupts = <35 0x8 36 0x8 37 0x8>; 209 interrupt-parent = <&ipic>; 210 /* Vitesse 7385 isn't on the MDIO bus */ 211 fixed-link = <1 1 1000 0 0>; 212 linux,network-index = <1>; 213 }; 214 215 serial0: serial@4500 { 216 cell-index = <0>; 217 device_type = "serial"; 218 compatible = "ns16550"; 219 reg = <0x4500 0x100>; 220 clock-frequency = <0>; // from bootloader 221 interrupts = <9 0x8>; 222 interrupt-parent = <&ipic>; 223 }; 224 225 serial1: serial@4600 { 226 cell-index = <1>; 227 device_type = "serial"; 228 compatible = "ns16550"; 229 reg = <0x4600 0x100>; 230 clock-frequency = <0>; // from bootloader 231 interrupts = <10 0x8>; 232 interrupt-parent = <&ipic>; 233 }; 234 235 crypto@30000 { 236 compatible = "fsl,sec2.0"; 237 reg = <0x30000 0x10000>; 238 interrupts = <11 0x8>; 239 interrupt-parent = <&ipic>; 240 fsl,num-channels = <4>; 241 fsl,channel-fifo-len = <24>; 242 fsl,exec-units-mask = <0x7e>; 243 fsl,descriptor-types-mask = <0x01010ebf>; 244 }; 245 246 ipic: pic@700 { 247 interrupt-controller; 248 #address-cells = <0>; 249 #interrupt-cells = <2>; 250 reg = <0x700 0x100>; 251 device_type = "ipic"; 252 }; 253 }; 254 255 pci0: pci@e0008500 { 256 cell-index = <1>; 257 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 258 interrupt-map = < 259 /* IDSEL 0x10 - SATA */ 260 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */ 261 >; 262 interrupt-parent = <&ipic>; 263 interrupts = <66 0x8>; 264 bus-range = <0x0 0x0>; 265 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 266 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 267 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>; 268 clock-frequency = <66666666>; 269 #interrupt-cells = <1>; 270 #size-cells = <2>; 271 #address-cells = <3>; 272 reg = <0xe0008500 0x100 /* internal registers */ 273 0xe0008300 0x8>; /* config space access registers */ 274 compatible = "fsl,mpc8349-pci"; 275 device_type = "pci"; 276 }; 277 278 pci1: pci@e0008600 { 279 cell-index = <2>; 280 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 281 interrupt-map = < 282 /* IDSEL 0x0E - MiniPCI Slot */ 283 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */ 284 285 /* IDSEL 0x0F - PCI Slot */ 286 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */ 287 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */ 288 >; 289 interrupt-parent = <&ipic>; 290 interrupts = <67 0x8>; 291 bus-range = <0x0 0x0>; 292 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 293 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 294 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>; 295 clock-frequency = <66666666>; 296 #interrupt-cells = <1>; 297 #size-cells = <2>; 298 #address-cells = <3>; 299 reg = <0xe0008600 0x100 /* internal registers */ 300 0xe0008380 0x8>; /* config space access registers */ 301 compatible = "fsl,mpc8349-pci"; 302 device_type = "pci"; 303 }; 304 305 localbus@e0005000 { 306 #address-cells = <2>; 307 #size-cells = <1>; 308 compatible = "fsl,mpc8349e-localbus", 309 "fsl,pq2pro-localbus"; 310 reg = <0xe0005000 0xd8>; 311 ranges = <0x3 0x0 0xf0000000 0x210>; 312 313 pata@3,0 { 314 compatible = "fsl,mpc8349emitx-pata", "ata-generic"; 315 reg = <0x3 0x0 0x10 0x3 0x20c 0x4>; 316 reg-shift = <1>; 317 pio-mode = <6>; 318 interrupts = <23 0x8>; 319 interrupt-parent = <&ipic>; 320 }; 321 }; 322}; 323