1/* 2 * MPC832x RDB Device Tree Source 3 * 4 * Copyright 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/ { 13 model = "MPC8323ERDB"; 14 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 PowerPC,8323@0 { 23 device_type = "cpu"; 24 reg = <0>; 25 d-cache-line-size = <20>; // 32 bytes 26 i-cache-line-size = <20>; // 32 bytes 27 d-cache-size = <4000>; // L1, 16K 28 i-cache-size = <4000>; // L1, 16K 29 timebase-frequency = <0>; 30 bus-frequency = <0>; 31 clock-frequency = <0>; 32 }; 33 }; 34 35 memory { 36 device_type = "memory"; 37 reg = <00000000 04000000>; 38 }; 39 40 soc8323@e0000000 { 41 #address-cells = <1>; 42 #size-cells = <1>; 43 device_type = "soc"; 44 ranges = <0 e0000000 00100000>; 45 reg = <e0000000 00000200>; 46 bus-frequency = <0>; 47 48 wdt@200 { 49 device_type = "watchdog"; 50 compatible = "mpc83xx_wdt"; 51 reg = <200 100>; 52 }; 53 54 i2c@3000 { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 cell-index = <0>; 58 compatible = "fsl-i2c"; 59 reg = <3000 100>; 60 interrupts = <e 8>; 61 interrupt-parent = <&pic>; 62 dfsrr; 63 }; 64 65 serial@4500 { 66 device_type = "serial"; 67 compatible = "ns16550"; 68 reg = <4500 100>; 69 clock-frequency = <0>; 70 interrupts = <9 8>; 71 interrupt-parent = <&pic>; 72 }; 73 74 serial@4600 { 75 device_type = "serial"; 76 compatible = "ns16550"; 77 reg = <4600 100>; 78 clock-frequency = <0>; 79 interrupts = <a 8>; 80 interrupt-parent = <&pic>; 81 }; 82 83 crypto@30000 { 84 device_type = "crypto"; 85 model = "SEC2"; 86 compatible = "talitos"; 87 reg = <30000 7000>; 88 interrupts = <b 8>; 89 interrupt-parent = <&pic>; 90 /* Rev. 2.2 */ 91 num-channels = <1>; 92 channel-fifo-len = <18>; 93 exec-units-mask = <0000004c>; 94 descriptor-types-mask = <0122003f>; 95 }; 96 97 pic:pic@700 { 98 interrupt-controller; 99 #address-cells = <0>; 100 #interrupt-cells = <2>; 101 reg = <700 100>; 102 device_type = "ipic"; 103 }; 104 105 par_io@1400 { 106 reg = <1400 100>; 107 device_type = "par_io"; 108 num-ports = <7>; 109 110 ucc2pio:ucc_pin@02 { 111 pio-map = < 112 /* port pin dir open_drain assignment has_irq */ 113 3 4 3 0 2 0 /* MDIO */ 114 3 5 1 0 2 0 /* MDC */ 115 3 15 2 0 1 0 /* RX_CLK (CLK16) */ 116 3 17 2 0 1 0 /* TX_CLK (CLK3) */ 117 0 12 1 0 1 0 /* TxD0 */ 118 0 13 1 0 1 0 /* TxD1 */ 119 0 14 1 0 1 0 /* TxD2 */ 120 0 15 1 0 1 0 /* TxD3 */ 121 0 16 2 0 1 0 /* RxD0 */ 122 0 17 2 0 1 0 /* RxD1 */ 123 0 18 2 0 1 0 /* RxD2 */ 124 0 19 2 0 1 0 /* RxD3 */ 125 0 1a 2 0 1 0 /* RX_ER */ 126 0 1b 1 0 1 0 /* TX_ER */ 127 0 1c 2 0 1 0 /* RX_DV */ 128 0 1d 2 0 1 0 /* COL */ 129 0 1e 1 0 1 0 /* TX_EN */ 130 0 1f 2 0 1 0>; /* CRS */ 131 }; 132 ucc3pio:ucc_pin@03 { 133 pio-map = < 134 /* port pin dir open_drain assignment has_irq */ 135 0 d 2 0 1 0 /* RX_CLK (CLK9) */ 136 3 18 2 0 1 0 /* TX_CLK (CLK10) */ 137 1 0 1 0 1 0 /* TxD0 */ 138 1 1 1 0 1 0 /* TxD1 */ 139 1 2 1 0 1 0 /* TxD2 */ 140 1 3 1 0 1 0 /* TxD3 */ 141 1 4 2 0 1 0 /* RxD0 */ 142 1 5 2 0 1 0 /* RxD1 */ 143 1 6 2 0 1 0 /* RxD2 */ 144 1 7 2 0 1 0 /* RxD3 */ 145 1 8 2 0 1 0 /* RX_ER */ 146 1 9 1 0 1 0 /* TX_ER */ 147 1 a 2 0 1 0 /* RX_DV */ 148 1 b 2 0 1 0 /* COL */ 149 1 c 1 0 1 0 /* TX_EN */ 150 1 d 2 0 1 0>; /* CRS */ 151 }; 152 }; 153 }; 154 155 qe@e0100000 { 156 #address-cells = <1>; 157 #size-cells = <1>; 158 device_type = "qe"; 159 model = "QE"; 160 ranges = <0 e0100000 00100000>; 161 reg = <e0100000 480>; 162 brg-frequency = <0>; 163 bus-frequency = <BCD3D80>; 164 165 muram@10000 { 166 device_type = "muram"; 167 ranges = <0 00010000 00004000>; 168 169 data-only@0 { 170 reg = <0 4000>; 171 }; 172 }; 173 174 spi@4c0 { 175 device_type = "spi"; 176 compatible = "fsl_spi"; 177 reg = <4c0 40>; 178 interrupts = <2>; 179 interrupt-parent = <&qeic>; 180 mode = "cpu-qe"; 181 }; 182 183 spi@500 { 184 device_type = "spi"; 185 compatible = "fsl_spi"; 186 reg = <500 40>; 187 interrupts = <1>; 188 interrupt-parent = <&qeic>; 189 mode = "cpu"; 190 }; 191 192 enet0: ucc@3000 { 193 device_type = "network"; 194 compatible = "ucc_geth"; 195 model = "UCC"; 196 cell-index = <2>; 197 device-id = <2>; 198 reg = <3000 200>; 199 interrupts = <21>; 200 interrupt-parent = <&qeic>; 201 local-mac-address = [ 00 00 00 00 00 00 ]; 202 rx-clock = <20>; 203 tx-clock = <13>; 204 phy-handle = <&phy00>; 205 pio-handle = <&ucc2pio>; 206 }; 207 208 enet1: ucc@2200 { 209 device_type = "network"; 210 compatible = "ucc_geth"; 211 model = "UCC"; 212 cell-index = <3>; 213 device-id = <3>; 214 reg = <2200 200>; 215 interrupts = <22>; 216 interrupt-parent = <&qeic>; 217 local-mac-address = [ 00 00 00 00 00 00 ]; 218 rx-clock = <19>; 219 tx-clock = <1a>; 220 phy-handle = <&phy04>; 221 pio-handle = <&ucc3pio>; 222 }; 223 224 mdio@3120 { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 reg = <3120 18>; 228 device_type = "mdio"; 229 compatible = "ucc_geth_phy"; 230 231 phy00:ethernet-phy@00 { 232 interrupt-parent = <&pic>; 233 interrupts = <0>; 234 reg = <0>; 235 device_type = "ethernet-phy"; 236 }; 237 phy04:ethernet-phy@04 { 238 interrupt-parent = <&pic>; 239 interrupts = <0>; 240 reg = <4>; 241 device_type = "ethernet-phy"; 242 }; 243 }; 244 245 qeic:qeic@80 { 246 interrupt-controller; 247 device_type = "qeic"; 248 #address-cells = <0>; 249 #interrupt-cells = <1>; 250 reg = <80 80>; 251 big-endian; 252 interrupts = <20 8 21 8>; //high:32 low:33 253 interrupt-parent = <&pic>; 254 }; 255 }; 256 257 pci@e0008500 { 258 interrupt-map-mask = <f800 0 0 7>; 259 interrupt-map = < 260 /* IDSEL 0x10 AD16 (USB) */ 261 8000 0 0 1 &pic 11 8 262 263 /* IDSEL 0x11 AD17 (Mini1)*/ 264 8800 0 0 1 &pic 12 8 265 8800 0 0 2 &pic 13 8 266 8800 0 0 3 &pic 14 8 267 8800 0 0 4 &pic 30 8 268 269 /* IDSEL 0x12 AD18 (PCI/Mini2) */ 270 9000 0 0 1 &pic 13 8 271 9000 0 0 2 &pic 14 8 272 9000 0 0 3 &pic 30 8 273 9000 0 0 4 &pic 11 8>; 274 275 interrupt-parent = <&pic>; 276 interrupts = <42 8>; 277 bus-range = <0 0>; 278 ranges = <42000000 0 80000000 80000000 0 10000000 279 02000000 0 90000000 90000000 0 10000000 280 01000000 0 d0000000 d0000000 0 04000000>; 281 clock-frequency = <0>; 282 #interrupt-cells = <1>; 283 #size-cells = <2>; 284 #address-cells = <3>; 285 reg = <e0008500 100>; 286 compatible = "fsl,mpc8349-pci"; 287 device_type = "pci"; 288 }; 289}; 290