1/* 2 * MPC832x RDB Device Tree Source 3 * 4 * Copyright 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "MPC8323ERDB"; 16 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,8323@0 { 33 device_type = "cpu"; 34 reg = <0x0>; 35 d-cache-line-size = <0x20>; // 32 bytes 36 i-cache-line-size = <0x20>; // 32 bytes 37 d-cache-size = <16384>; // L1, 16K 38 i-cache-size = <16384>; // L1, 16K 39 timebase-frequency = <0>; 40 bus-frequency = <0>; 41 clock-frequency = <0>; 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x00000000 0x04000000>; 48 }; 49 50 soc8323@e0000000 { 51 #address-cells = <1>; 52 #size-cells = <1>; 53 device_type = "soc"; 54 ranges = <0x0 0xe0000000 0x00100000>; 55 reg = <0xe0000000 0x00000200>; 56 bus-frequency = <0>; 57 58 wdt@200 { 59 device_type = "watchdog"; 60 compatible = "mpc83xx_wdt"; 61 reg = <0x200 0x100>; 62 }; 63 64 i2c@3000 { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 cell-index = <0>; 68 compatible = "fsl-i2c"; 69 reg = <0x3000 0x100>; 70 interrupts = <14 0x8>; 71 interrupt-parent = <&ipic>; 72 dfsrr; 73 }; 74 75 serial0: serial@4500 { 76 cell-index = <0>; 77 device_type = "serial"; 78 compatible = "ns16550"; 79 reg = <0x4500 0x100>; 80 clock-frequency = <0>; 81 interrupts = <9 0x8>; 82 interrupt-parent = <&ipic>; 83 }; 84 85 serial1: serial@4600 { 86 cell-index = <1>; 87 device_type = "serial"; 88 compatible = "ns16550"; 89 reg = <0x4600 0x100>; 90 clock-frequency = <0>; 91 interrupts = <10 0x8>; 92 interrupt-parent = <&ipic>; 93 }; 94 95 dma@82a8 { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; 99 reg = <0x82a8 4>; 100 ranges = <0 0x8100 0x1a8>; 101 interrupt-parent = <&ipic>; 102 interrupts = <71 8>; 103 cell-index = <0>; 104 dma-channel@0 { 105 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 106 reg = <0 0x80>; 107 interrupt-parent = <&ipic>; 108 interrupts = <71 8>; 109 }; 110 dma-channel@80 { 111 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 112 reg = <0x80 0x80>; 113 interrupt-parent = <&ipic>; 114 interrupts = <71 8>; 115 }; 116 dma-channel@100 { 117 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 118 reg = <0x100 0x80>; 119 interrupt-parent = <&ipic>; 120 interrupts = <71 8>; 121 }; 122 dma-channel@180 { 123 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 124 reg = <0x180 0x28>; 125 interrupt-parent = <&ipic>; 126 interrupts = <71 8>; 127 }; 128 }; 129 130 crypto@30000 { 131 device_type = "crypto"; 132 model = "SEC2"; 133 compatible = "talitos"; 134 reg = <0x30000 0x7000>; 135 interrupts = <11 0x8>; 136 interrupt-parent = <&ipic>; 137 /* Rev. 2.2 */ 138 num-channels = <1>; 139 channel-fifo-len = <24>; 140 exec-units-mask = <0x0000004c>; 141 descriptor-types-mask = <0x0122003f>; 142 }; 143 144 ipic:pic@700 { 145 interrupt-controller; 146 #address-cells = <0>; 147 #interrupt-cells = <2>; 148 reg = <0x700 0x100>; 149 device_type = "ipic"; 150 }; 151 152 par_io@1400 { 153 reg = <0x1400 0x100>; 154 device_type = "par_io"; 155 num-ports = <7>; 156 157 ucc2pio:ucc_pin@02 { 158 pio-map = < 159 /* port pin dir open_drain assignment has_irq */ 160 3 4 3 0 2 0 /* MDIO */ 161 3 5 1 0 2 0 /* MDC */ 162 3 21 2 0 1 0 /* RX_CLK (CLK16) */ 163 3 23 2 0 1 0 /* TX_CLK (CLK3) */ 164 0 18 1 0 1 0 /* TxD0 */ 165 0 19 1 0 1 0 /* TxD1 */ 166 0 20 1 0 1 0 /* TxD2 */ 167 0 21 1 0 1 0 /* TxD3 */ 168 0 22 2 0 1 0 /* RxD0 */ 169 0 23 2 0 1 0 /* RxD1 */ 170 0 24 2 0 1 0 /* RxD2 */ 171 0 25 2 0 1 0 /* RxD3 */ 172 0 26 2 0 1 0 /* RX_ER */ 173 0 27 1 0 1 0 /* TX_ER */ 174 0 28 2 0 1 0 /* RX_DV */ 175 0 29 2 0 1 0 /* COL */ 176 0 30 1 0 1 0 /* TX_EN */ 177 0 31 2 0 1 0>; /* CRS */ 178 }; 179 ucc3pio:ucc_pin@03 { 180 pio-map = < 181 /* port pin dir open_drain assignment has_irq */ 182 0 13 2 0 1 0 /* RX_CLK (CLK9) */ 183 3 24 2 0 1 0 /* TX_CLK (CLK10) */ 184 1 0 1 0 1 0 /* TxD0 */ 185 1 1 1 0 1 0 /* TxD1 */ 186 1 2 1 0 1 0 /* TxD2 */ 187 1 3 1 0 1 0 /* TxD3 */ 188 1 4 2 0 1 0 /* RxD0 */ 189 1 5 2 0 1 0 /* RxD1 */ 190 1 6 2 0 1 0 /* RxD2 */ 191 1 7 2 0 1 0 /* RxD3 */ 192 1 8 2 0 1 0 /* RX_ER */ 193 1 9 1 0 1 0 /* TX_ER */ 194 1 10 2 0 1 0 /* RX_DV */ 195 1 11 2 0 1 0 /* COL */ 196 1 12 1 0 1 0 /* TX_EN */ 197 1 13 2 0 1 0>; /* CRS */ 198 }; 199 }; 200 }; 201 202 qe@e0100000 { 203 #address-cells = <1>; 204 #size-cells = <1>; 205 device_type = "qe"; 206 compatible = "fsl,qe"; 207 ranges = <0x0 0xe0100000 0x00100000>; 208 reg = <0xe0100000 0x480>; 209 brg-frequency = <0>; 210 bus-frequency = <198000000>; 211 212 muram@10000 { 213 #address-cells = <1>; 214 #size-cells = <1>; 215 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 216 ranges = <0x0 0x00010000 0x00004000>; 217 218 data-only@0 { 219 compatible = "fsl,qe-muram-data", 220 "fsl,cpm-muram-data"; 221 reg = <0x0 0x4000>; 222 }; 223 }; 224 225 spi@4c0 { 226 cell-index = <0>; 227 compatible = "fsl,spi"; 228 reg = <0x4c0 0x40>; 229 interrupts = <2>; 230 interrupt-parent = <&qeic>; 231 mode = "cpu-qe"; 232 }; 233 234 spi@500 { 235 cell-index = <1>; 236 compatible = "fsl,spi"; 237 reg = <0x500 0x40>; 238 interrupts = <1>; 239 interrupt-parent = <&qeic>; 240 mode = "cpu"; 241 }; 242 243 enet0: ucc@3000 { 244 device_type = "network"; 245 compatible = "ucc_geth"; 246 cell-index = <2>; 247 reg = <0x3000 0x200>; 248 interrupts = <33>; 249 interrupt-parent = <&qeic>; 250 local-mac-address = [ 00 00 00 00 00 00 ]; 251 rx-clock-name = "clk16"; 252 tx-clock-name = "clk3"; 253 phy-handle = <&phy00>; 254 pio-handle = <&ucc2pio>; 255 }; 256 257 enet1: ucc@2200 { 258 device_type = "network"; 259 compatible = "ucc_geth"; 260 cell-index = <3>; 261 reg = <0x2200 0x200>; 262 interrupts = <34>; 263 interrupt-parent = <&qeic>; 264 local-mac-address = [ 00 00 00 00 00 00 ]; 265 rx-clock-name = "clk9"; 266 tx-clock-name = "clk10"; 267 phy-handle = <&phy04>; 268 pio-handle = <&ucc3pio>; 269 }; 270 271 mdio@3120 { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 reg = <0x3120 0x18>; 275 compatible = "fsl,ucc-mdio"; 276 277 phy00:ethernet-phy@00 { 278 interrupt-parent = <&ipic>; 279 interrupts = <0>; 280 reg = <0x0>; 281 device_type = "ethernet-phy"; 282 }; 283 phy04:ethernet-phy@04 { 284 interrupt-parent = <&ipic>; 285 interrupts = <0>; 286 reg = <0x4>; 287 device_type = "ethernet-phy"; 288 }; 289 }; 290 291 qeic:interrupt-controller@80 { 292 interrupt-controller; 293 compatible = "fsl,qe-ic"; 294 #address-cells = <0>; 295 #interrupt-cells = <1>; 296 reg = <0x80 0x80>; 297 big-endian; 298 interrupts = <32 0x8 33 0x8>; //high:32 low:33 299 interrupt-parent = <&ipic>; 300 }; 301 }; 302 303 pci0: pci@e0008500 { 304 cell-index = <1>; 305 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 306 interrupt-map = < 307 /* IDSEL 0x10 AD16 (USB) */ 308 0x8000 0x0 0x0 0x1 &ipic 17 0x8 309 310 /* IDSEL 0x11 AD17 (Mini1)*/ 311 0x8800 0x0 0x0 0x1 &ipic 18 0x8 312 0x8800 0x0 0x0 0x2 &ipic 19 0x8 313 0x8800 0x0 0x0 0x3 &ipic 20 0x8 314 0x8800 0x0 0x0 0x4 &ipic 48 0x8 315 316 /* IDSEL 0x12 AD18 (PCI/Mini2) */ 317 0x9000 0x0 0x0 0x1 &ipic 19 0x8 318 0x9000 0x0 0x0 0x2 &ipic 20 0x8 319 0x9000 0x0 0x0 0x3 &ipic 48 0x8 320 0x9000 0x0 0x0 0x4 &ipic 17 0x8>; 321 322 interrupt-parent = <&ipic>; 323 interrupts = <66 0x8>; 324 bus-range = <0x0 0x0>; 325 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 326 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 327 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>; 328 clock-frequency = <0>; 329 #interrupt-cells = <1>; 330 #size-cells = <2>; 331 #address-cells = <3>; 332 reg = <0xe0008500 0x100>; 333 compatible = "fsl,mpc8349-pci"; 334 device_type = "pci"; 335 }; 336}; 337