1/*
2 * MPC832x RDB Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "MPC8323ERDB";
16	compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,8323@0 {
33			device_type = "cpu";
34			reg = <0x0>;
35			d-cache-line-size = <0x20>;	// 32 bytes
36			i-cache-line-size = <0x20>;	// 32 bytes
37			d-cache-size = <16384>;	// L1, 16K
38			i-cache-size = <16384>;	// L1, 16K
39			timebase-frequency = <0>;
40			bus-frequency = <0>;
41			clock-frequency = <0>;
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x04000000>;
48	};
49
50	soc8323@e0000000 {
51		#address-cells = <1>;
52		#size-cells = <1>;
53		device_type = "soc";
54		compatible = "simple-bus";
55		ranges = <0x0 0xe0000000 0x00100000>;
56		reg = <0xe0000000 0x00000200>;
57		bus-frequency = <0>;
58
59		wdt@200 {
60			device_type = "watchdog";
61			compatible = "mpc83xx_wdt";
62			reg = <0x200 0x100>;
63		};
64
65		i2c@3000 {
66			#address-cells = <1>;
67			#size-cells = <0>;
68			cell-index = <0>;
69			compatible = "fsl-i2c";
70			reg = <0x3000 0x100>;
71			interrupts = <14 0x8>;
72			interrupt-parent = <&ipic>;
73			dfsrr;
74		};
75
76		serial0: serial@4500 {
77			cell-index = <0>;
78			device_type = "serial";
79			compatible = "ns16550";
80			reg = <0x4500 0x100>;
81			clock-frequency = <0>;
82			interrupts = <9 0x8>;
83			interrupt-parent = <&ipic>;
84		};
85
86		serial1: serial@4600 {
87			cell-index = <1>;
88			device_type = "serial";
89			compatible = "ns16550";
90			reg = <0x4600 0x100>;
91			clock-frequency = <0>;
92			interrupts = <10 0x8>;
93			interrupt-parent = <&ipic>;
94		};
95
96		dma@82a8 {
97			#address-cells = <1>;
98			#size-cells = <1>;
99			compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
100			reg = <0x82a8 4>;
101			ranges = <0 0x8100 0x1a8>;
102			interrupt-parent = <&ipic>;
103			interrupts = <71 8>;
104			cell-index = <0>;
105			dma-channel@0 {
106				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
107				reg = <0 0x80>;
108				interrupt-parent = <&ipic>;
109				interrupts = <71 8>;
110			};
111			dma-channel@80 {
112				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
113				reg = <0x80 0x80>;
114				interrupt-parent = <&ipic>;
115				interrupts = <71 8>;
116			};
117			dma-channel@100 {
118				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
119				reg = <0x100 0x80>;
120				interrupt-parent = <&ipic>;
121				interrupts = <71 8>;
122			};
123			dma-channel@180 {
124				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
125				reg = <0x180 0x28>;
126				interrupt-parent = <&ipic>;
127				interrupts = <71 8>;
128			};
129		};
130
131		crypto@30000 {
132			compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
133			reg = <0x30000 0x10000>;
134			interrupts = <11 0x8>;
135			interrupt-parent = <&ipic>;
136			fsl,num-channels = <1>;
137			fsl,channel-fifo-len = <24>;
138			fsl,exec-units-mask = <0x4c>;
139			fsl,descriptor-types-mask = <0x0122003f>;
140		};
141
142		ipic:pic@700 {
143			interrupt-controller;
144			#address-cells = <0>;
145			#interrupt-cells = <2>;
146			reg = <0x700 0x100>;
147			device_type = "ipic";
148		};
149
150		par_io@1400 {
151			reg = <0x1400 0x100>;
152			device_type = "par_io";
153			num-ports = <7>;
154
155			ucc2pio:ucc_pin@02 {
156				pio-map = <
157			/* port  pin  dir  open_drain  assignment  has_irq */
158					3  4  3  0  2  0 	/* MDIO */
159					3  5  1  0  2  0 	/* MDC */
160					3 21  2  0  1  0 	/* RX_CLK (CLK16) */
161					3 23  2  0  1  0 	/* TX_CLK (CLK3) */
162					0 18  1  0  1  0 	/* TxD0 */
163					0 19  1  0  1  0 	/* TxD1 */
164					0 20  1  0  1  0 	/* TxD2 */
165					0 21  1  0  1  0 	/* TxD3 */
166					0 22  2  0  1  0 	/* RxD0 */
167					0 23  2  0  1  0 	/* RxD1 */
168					0 24  2  0  1  0 	/* RxD2 */
169					0 25  2  0  1  0 	/* RxD3 */
170					0 26  2  0  1  0 	/* RX_ER */
171					0 27  1  0  1  0 	/* TX_ER */
172					0 28  2  0  1  0 	/* RX_DV */
173					0 29  2  0  1  0 	/* COL */
174					0 30  1  0  1  0 	/* TX_EN */
175					0 31  2  0  1  0>;      /* CRS */
176			};
177			ucc3pio:ucc_pin@03 {
178				pio-map = <
179			/* port  pin  dir  open_drain  assignment  has_irq */
180					0 13  2  0  1  0 	/* RX_CLK (CLK9) */
181					3 24  2  0  1  0 	/* TX_CLK (CLK10) */
182					1  0  1  0  1  0 	/* TxD0 */
183					1  1  1  0  1  0 	/* TxD1 */
184					1  2  1  0  1  0 	/* TxD2 */
185					1  3  1  0  1  0 	/* TxD3 */
186					1  4  2  0  1  0 	/* RxD0 */
187					1  5  2  0  1  0 	/* RxD1 */
188					1  6  2  0  1  0 	/* RxD2 */
189					1  7  2  0  1  0 	/* RxD3 */
190					1  8  2  0  1  0 	/* RX_ER */
191					1  9  1  0  1  0 	/* TX_ER */
192					1 10  2  0  1  0 	/* RX_DV */
193					1 11  2  0  1  0 	/* COL */
194					1 12  1  0  1  0 	/* TX_EN */
195					1 13  2  0  1  0>;      /* CRS */
196			};
197		};
198	};
199
200	qe@e0100000 {
201		#address-cells = <1>;
202		#size-cells = <1>;
203		device_type = "qe";
204		compatible = "fsl,qe";
205		ranges = <0x0 0xe0100000 0x00100000>;
206		reg = <0xe0100000 0x480>;
207		brg-frequency = <0>;
208		bus-frequency = <198000000>;
209
210		muram@10000 {
211 			#address-cells = <1>;
212 			#size-cells = <1>;
213			compatible = "fsl,qe-muram", "fsl,cpm-muram";
214			ranges = <0x0 0x00010000 0x00004000>;
215
216			data-only@0 {
217				compatible = "fsl,qe-muram-data",
218					     "fsl,cpm-muram-data";
219				reg = <0x0 0x4000>;
220			};
221		};
222
223		spi@4c0 {
224			cell-index = <0>;
225			compatible = "fsl,spi";
226			reg = <0x4c0 0x40>;
227			interrupts = <2>;
228			interrupt-parent = <&qeic>;
229			mode = "cpu-qe";
230		};
231
232		spi@500 {
233			cell-index = <1>;
234			compatible = "fsl,spi";
235			reg = <0x500 0x40>;
236			interrupts = <1>;
237			interrupt-parent = <&qeic>;
238			mode = "cpu";
239		};
240
241		enet0: ucc@3000 {
242			device_type = "network";
243			compatible = "ucc_geth";
244			cell-index = <2>;
245			reg = <0x3000 0x200>;
246			interrupts = <33>;
247			interrupt-parent = <&qeic>;
248			local-mac-address = [ 00 00 00 00 00 00 ];
249			rx-clock-name = "clk16";
250			tx-clock-name = "clk3";
251			phy-handle = <&phy00>;
252			pio-handle = <&ucc2pio>;
253		};
254
255		enet1: ucc@2200 {
256			device_type = "network";
257			compatible = "ucc_geth";
258			cell-index = <3>;
259			reg = <0x2200 0x200>;
260			interrupts = <34>;
261			interrupt-parent = <&qeic>;
262			local-mac-address = [ 00 00 00 00 00 00 ];
263			rx-clock-name = "clk9";
264			tx-clock-name = "clk10";
265			phy-handle = <&phy04>;
266			pio-handle = <&ucc3pio>;
267		};
268
269		mdio@3120 {
270			#address-cells = <1>;
271			#size-cells = <0>;
272			reg = <0x3120 0x18>;
273			compatible = "fsl,ucc-mdio";
274
275			phy00:ethernet-phy@00 {
276				interrupt-parent = <&ipic>;
277				interrupts = <0>;
278				reg = <0x0>;
279				device_type = "ethernet-phy";
280			};
281			phy04:ethernet-phy@04 {
282				interrupt-parent = <&ipic>;
283				interrupts = <0>;
284				reg = <0x4>;
285				device_type = "ethernet-phy";
286			};
287		};
288
289		qeic:interrupt-controller@80 {
290			interrupt-controller;
291			compatible = "fsl,qe-ic";
292			#address-cells = <0>;
293			#interrupt-cells = <1>;
294			reg = <0x80 0x80>;
295			big-endian;
296			interrupts = <32 0x8 33 0x8>; //high:32 low:33
297			interrupt-parent = <&ipic>;
298		};
299	};
300
301	pci0: pci@e0008500 {
302		cell-index = <1>;
303		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
304		interrupt-map = <
305				/* IDSEL 0x10 AD16 (USB) */
306				 0x8000 0x0 0x0 0x1 &ipic 17 0x8
307
308				/* IDSEL 0x11 AD17 (Mini1)*/
309				 0x8800 0x0 0x0 0x1 &ipic 18 0x8
310				 0x8800 0x0 0x0 0x2 &ipic 19 0x8
311				 0x8800 0x0 0x0 0x3 &ipic 20 0x8
312				 0x8800 0x0 0x0 0x4 &ipic 48 0x8
313
314				/* IDSEL 0x12 AD18 (PCI/Mini2) */
315				 0x9000 0x0 0x0 0x1 &ipic 19 0x8
316				 0x9000 0x0 0x0 0x2 &ipic 20 0x8
317				 0x9000 0x0 0x0 0x3 &ipic 48 0x8
318				 0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
319
320		interrupt-parent = <&ipic>;
321		interrupts = <66 0x8>;
322		bus-range = <0x0 0x0>;
323		ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
324			  0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
325			  0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
326		clock-frequency = <0>;
327		#interrupt-cells = <1>;
328		#size-cells = <2>;
329		#address-cells = <3>;
330		reg = <0xe0008500 0x100>;
331		compatible = "fsl,mpc8349-pci";
332		device_type = "pci";
333	};
334};
335