1/* 2 * MPC832x RDB Device Tree Source 3 * 4 * Copyright 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "MPC8323ERDB"; 16 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,8323@0 { 33 device_type = "cpu"; 34 reg = <0x0>; 35 d-cache-line-size = <0x20>; // 32 bytes 36 i-cache-line-size = <0x20>; // 32 bytes 37 d-cache-size = <16384>; // L1, 16K 38 i-cache-size = <16384>; // L1, 16K 39 timebase-frequency = <0>; 40 bus-frequency = <0>; 41 clock-frequency = <0>; 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x00000000 0x04000000>; 48 }; 49 50 soc8323@e0000000 { 51 #address-cells = <1>; 52 #size-cells = <1>; 53 device_type = "soc"; 54 compatible = "simple-bus"; 55 ranges = <0x0 0xe0000000 0x00100000>; 56 reg = <0xe0000000 0x00000200>; 57 bus-frequency = <0>; 58 59 wdt@200 { 60 device_type = "watchdog"; 61 compatible = "mpc83xx_wdt"; 62 reg = <0x200 0x100>; 63 }; 64 65 i2c@3000 { 66 #address-cells = <1>; 67 #size-cells = <0>; 68 cell-index = <0>; 69 compatible = "fsl-i2c"; 70 reg = <0x3000 0x100>; 71 interrupts = <14 0x8>; 72 interrupt-parent = <&ipic>; 73 dfsrr; 74 }; 75 76 serial0: serial@4500 { 77 cell-index = <0>; 78 device_type = "serial"; 79 compatible = "ns16550"; 80 reg = <0x4500 0x100>; 81 clock-frequency = <0>; 82 interrupts = <9 0x8>; 83 interrupt-parent = <&ipic>; 84 }; 85 86 serial1: serial@4600 { 87 cell-index = <1>; 88 device_type = "serial"; 89 compatible = "ns16550"; 90 reg = <0x4600 0x100>; 91 clock-frequency = <0>; 92 interrupts = <10 0x8>; 93 interrupt-parent = <&ipic>; 94 }; 95 96 dma@82a8 { 97 #address-cells = <1>; 98 #size-cells = <1>; 99 compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; 100 reg = <0x82a8 4>; 101 ranges = <0 0x8100 0x1a8>; 102 interrupt-parent = <&ipic>; 103 interrupts = <71 8>; 104 cell-index = <0>; 105 dma-channel@0 { 106 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 107 reg = <0 0x80>; 108 cell-index = <0>; 109 interrupt-parent = <&ipic>; 110 interrupts = <71 8>; 111 }; 112 dma-channel@80 { 113 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 114 reg = <0x80 0x80>; 115 cell-index = <1>; 116 interrupt-parent = <&ipic>; 117 interrupts = <71 8>; 118 }; 119 dma-channel@100 { 120 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 121 reg = <0x100 0x80>; 122 cell-index = <2>; 123 interrupt-parent = <&ipic>; 124 interrupts = <71 8>; 125 }; 126 dma-channel@180 { 127 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 128 reg = <0x180 0x28>; 129 cell-index = <3>; 130 interrupt-parent = <&ipic>; 131 interrupts = <71 8>; 132 }; 133 }; 134 135 crypto@30000 { 136 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; 137 reg = <0x30000 0x10000>; 138 interrupts = <11 0x8>; 139 interrupt-parent = <&ipic>; 140 fsl,num-channels = <1>; 141 fsl,channel-fifo-len = <24>; 142 fsl,exec-units-mask = <0x4c>; 143 fsl,descriptor-types-mask = <0x0122003f>; 144 }; 145 146 ipic:pic@700 { 147 interrupt-controller; 148 #address-cells = <0>; 149 #interrupt-cells = <2>; 150 reg = <0x700 0x100>; 151 device_type = "ipic"; 152 }; 153 154 par_io@1400 { 155 reg = <0x1400 0x100>; 156 device_type = "par_io"; 157 num-ports = <7>; 158 159 ucc2pio:ucc_pin@02 { 160 pio-map = < 161 /* port pin dir open_drain assignment has_irq */ 162 3 4 3 0 2 0 /* MDIO */ 163 3 5 1 0 2 0 /* MDC */ 164 3 21 2 0 1 0 /* RX_CLK (CLK16) */ 165 3 23 2 0 1 0 /* TX_CLK (CLK3) */ 166 0 18 1 0 1 0 /* TxD0 */ 167 0 19 1 0 1 0 /* TxD1 */ 168 0 20 1 0 1 0 /* TxD2 */ 169 0 21 1 0 1 0 /* TxD3 */ 170 0 22 2 0 1 0 /* RxD0 */ 171 0 23 2 0 1 0 /* RxD1 */ 172 0 24 2 0 1 0 /* RxD2 */ 173 0 25 2 0 1 0 /* RxD3 */ 174 0 26 2 0 1 0 /* RX_ER */ 175 0 27 1 0 1 0 /* TX_ER */ 176 0 28 2 0 1 0 /* RX_DV */ 177 0 29 2 0 1 0 /* COL */ 178 0 30 1 0 1 0 /* TX_EN */ 179 0 31 2 0 1 0>; /* CRS */ 180 }; 181 ucc3pio:ucc_pin@03 { 182 pio-map = < 183 /* port pin dir open_drain assignment has_irq */ 184 0 13 2 0 1 0 /* RX_CLK (CLK9) */ 185 3 24 2 0 1 0 /* TX_CLK (CLK10) */ 186 1 0 1 0 1 0 /* TxD0 */ 187 1 1 1 0 1 0 /* TxD1 */ 188 1 2 1 0 1 0 /* TxD2 */ 189 1 3 1 0 1 0 /* TxD3 */ 190 1 4 2 0 1 0 /* RxD0 */ 191 1 5 2 0 1 0 /* RxD1 */ 192 1 6 2 0 1 0 /* RxD2 */ 193 1 7 2 0 1 0 /* RxD3 */ 194 1 8 2 0 1 0 /* RX_ER */ 195 1 9 1 0 1 0 /* TX_ER */ 196 1 10 2 0 1 0 /* RX_DV */ 197 1 11 2 0 1 0 /* COL */ 198 1 12 1 0 1 0 /* TX_EN */ 199 1 13 2 0 1 0>; /* CRS */ 200 }; 201 }; 202 }; 203 204 qe@e0100000 { 205 #address-cells = <1>; 206 #size-cells = <1>; 207 device_type = "qe"; 208 compatible = "fsl,qe"; 209 ranges = <0x0 0xe0100000 0x00100000>; 210 reg = <0xe0100000 0x480>; 211 brg-frequency = <0>; 212 bus-frequency = <198000000>; 213 214 muram@10000 { 215 #address-cells = <1>; 216 #size-cells = <1>; 217 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 218 ranges = <0x0 0x00010000 0x00004000>; 219 220 data-only@0 { 221 compatible = "fsl,qe-muram-data", 222 "fsl,cpm-muram-data"; 223 reg = <0x0 0x4000>; 224 }; 225 }; 226 227 spi@4c0 { 228 cell-index = <0>; 229 compatible = "fsl,spi"; 230 reg = <0x4c0 0x40>; 231 interrupts = <2>; 232 interrupt-parent = <&qeic>; 233 mode = "cpu-qe"; 234 }; 235 236 spi@500 { 237 cell-index = <1>; 238 compatible = "fsl,spi"; 239 reg = <0x500 0x40>; 240 interrupts = <1>; 241 interrupt-parent = <&qeic>; 242 mode = "cpu"; 243 }; 244 245 enet0: ucc@3000 { 246 device_type = "network"; 247 compatible = "ucc_geth"; 248 cell-index = <2>; 249 reg = <0x3000 0x200>; 250 interrupts = <33>; 251 interrupt-parent = <&qeic>; 252 local-mac-address = [ 00 00 00 00 00 00 ]; 253 rx-clock-name = "clk16"; 254 tx-clock-name = "clk3"; 255 phy-handle = <&phy00>; 256 pio-handle = <&ucc2pio>; 257 }; 258 259 enet1: ucc@2200 { 260 device_type = "network"; 261 compatible = "ucc_geth"; 262 cell-index = <3>; 263 reg = <0x2200 0x200>; 264 interrupts = <34>; 265 interrupt-parent = <&qeic>; 266 local-mac-address = [ 00 00 00 00 00 00 ]; 267 rx-clock-name = "clk9"; 268 tx-clock-name = "clk10"; 269 phy-handle = <&phy04>; 270 pio-handle = <&ucc3pio>; 271 }; 272 273 mdio@3120 { 274 #address-cells = <1>; 275 #size-cells = <0>; 276 reg = <0x3120 0x18>; 277 compatible = "fsl,ucc-mdio"; 278 279 phy00:ethernet-phy@00 { 280 interrupt-parent = <&ipic>; 281 interrupts = <0>; 282 reg = <0x0>; 283 device_type = "ethernet-phy"; 284 }; 285 phy04:ethernet-phy@04 { 286 interrupt-parent = <&ipic>; 287 interrupts = <0>; 288 reg = <0x4>; 289 device_type = "ethernet-phy"; 290 }; 291 }; 292 293 qeic:interrupt-controller@80 { 294 interrupt-controller; 295 compatible = "fsl,qe-ic"; 296 #address-cells = <0>; 297 #interrupt-cells = <1>; 298 reg = <0x80 0x80>; 299 big-endian; 300 interrupts = <32 0x8 33 0x8>; //high:32 low:33 301 interrupt-parent = <&ipic>; 302 }; 303 }; 304 305 pci0: pci@e0008500 { 306 cell-index = <1>; 307 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 308 interrupt-map = < 309 /* IDSEL 0x10 AD16 (USB) */ 310 0x8000 0x0 0x0 0x1 &ipic 17 0x8 311 312 /* IDSEL 0x11 AD17 (Mini1)*/ 313 0x8800 0x0 0x0 0x1 &ipic 18 0x8 314 0x8800 0x0 0x0 0x2 &ipic 19 0x8 315 0x8800 0x0 0x0 0x3 &ipic 20 0x8 316 0x8800 0x0 0x0 0x4 &ipic 48 0x8 317 318 /* IDSEL 0x12 AD18 (PCI/Mini2) */ 319 0x9000 0x0 0x0 0x1 &ipic 19 0x8 320 0x9000 0x0 0x0 0x2 &ipic 20 0x8 321 0x9000 0x0 0x0 0x3 &ipic 48 0x8 322 0x9000 0x0 0x0 0x4 &ipic 17 0x8>; 323 324 interrupt-parent = <&ipic>; 325 interrupts = <66 0x8>; 326 bus-range = <0x0 0x0>; 327 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 328 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 329 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>; 330 clock-frequency = <0>; 331 #interrupt-cells = <1>; 332 #size-cells = <2>; 333 #address-cells = <3>; 334 reg = <0xe0008500 0x100>; 335 compatible = "fsl,mpc8349-pci"; 336 device_type = "pci"; 337 }; 338}; 339