1/* 2 * MPC832x RDB Device Tree Source 3 * 4 * Copyright 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/ { 13 model = "MPC8323ERDB"; 14 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 aliases { 19 ethernet0 = &enet0; 20 ethernet1 = &enet1; 21 serial0 = &serial0; 22 serial1 = &serial1; 23 pci0 = &pci0; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 PowerPC,8323@0 { 31 device_type = "cpu"; 32 reg = <0>; 33 d-cache-line-size = <20>; // 32 bytes 34 i-cache-line-size = <20>; // 32 bytes 35 d-cache-size = <4000>; // L1, 16K 36 i-cache-size = <4000>; // L1, 16K 37 timebase-frequency = <0>; 38 bus-frequency = <0>; 39 clock-frequency = <0>; 40 }; 41 }; 42 43 memory { 44 device_type = "memory"; 45 reg = <00000000 04000000>; 46 }; 47 48 soc8323@e0000000 { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 device_type = "soc"; 52 ranges = <0 e0000000 00100000>; 53 reg = <e0000000 00000200>; 54 bus-frequency = <0>; 55 56 wdt@200 { 57 device_type = "watchdog"; 58 compatible = "mpc83xx_wdt"; 59 reg = <200 100>; 60 }; 61 62 i2c@3000 { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 cell-index = <0>; 66 compatible = "fsl-i2c"; 67 reg = <3000 100>; 68 interrupts = <e 8>; 69 interrupt-parent = <&pic>; 70 dfsrr; 71 }; 72 73 serial0: serial@4500 { 74 cell-index = <0>; 75 device_type = "serial"; 76 compatible = "ns16550"; 77 reg = <4500 100>; 78 clock-frequency = <0>; 79 interrupts = <9 8>; 80 interrupt-parent = <&pic>; 81 }; 82 83 serial1: serial@4600 { 84 cell-index = <1>; 85 device_type = "serial"; 86 compatible = "ns16550"; 87 reg = <4600 100>; 88 clock-frequency = <0>; 89 interrupts = <a 8>; 90 interrupt-parent = <&pic>; 91 }; 92 93 crypto@30000 { 94 device_type = "crypto"; 95 model = "SEC2"; 96 compatible = "talitos"; 97 reg = <30000 7000>; 98 interrupts = <b 8>; 99 interrupt-parent = <&pic>; 100 /* Rev. 2.2 */ 101 num-channels = <1>; 102 channel-fifo-len = <18>; 103 exec-units-mask = <0000004c>; 104 descriptor-types-mask = <0122003f>; 105 }; 106 107 pic:pic@700 { 108 interrupt-controller; 109 #address-cells = <0>; 110 #interrupt-cells = <2>; 111 reg = <700 100>; 112 device_type = "ipic"; 113 }; 114 115 par_io@1400 { 116 reg = <1400 100>; 117 device_type = "par_io"; 118 num-ports = <7>; 119 120 ucc2pio:ucc_pin@02 { 121 pio-map = < 122 /* port pin dir open_drain assignment has_irq */ 123 3 4 3 0 2 0 /* MDIO */ 124 3 5 1 0 2 0 /* MDC */ 125 3 15 2 0 1 0 /* RX_CLK (CLK16) */ 126 3 17 2 0 1 0 /* TX_CLK (CLK3) */ 127 0 12 1 0 1 0 /* TxD0 */ 128 0 13 1 0 1 0 /* TxD1 */ 129 0 14 1 0 1 0 /* TxD2 */ 130 0 15 1 0 1 0 /* TxD3 */ 131 0 16 2 0 1 0 /* RxD0 */ 132 0 17 2 0 1 0 /* RxD1 */ 133 0 18 2 0 1 0 /* RxD2 */ 134 0 19 2 0 1 0 /* RxD3 */ 135 0 1a 2 0 1 0 /* RX_ER */ 136 0 1b 1 0 1 0 /* TX_ER */ 137 0 1c 2 0 1 0 /* RX_DV */ 138 0 1d 2 0 1 0 /* COL */ 139 0 1e 1 0 1 0 /* TX_EN */ 140 0 1f 2 0 1 0>; /* CRS */ 141 }; 142 ucc3pio:ucc_pin@03 { 143 pio-map = < 144 /* port pin dir open_drain assignment has_irq */ 145 0 d 2 0 1 0 /* RX_CLK (CLK9) */ 146 3 18 2 0 1 0 /* TX_CLK (CLK10) */ 147 1 0 1 0 1 0 /* TxD0 */ 148 1 1 1 0 1 0 /* TxD1 */ 149 1 2 1 0 1 0 /* TxD2 */ 150 1 3 1 0 1 0 /* TxD3 */ 151 1 4 2 0 1 0 /* RxD0 */ 152 1 5 2 0 1 0 /* RxD1 */ 153 1 6 2 0 1 0 /* RxD2 */ 154 1 7 2 0 1 0 /* RxD3 */ 155 1 8 2 0 1 0 /* RX_ER */ 156 1 9 1 0 1 0 /* TX_ER */ 157 1 a 2 0 1 0 /* RX_DV */ 158 1 b 2 0 1 0 /* COL */ 159 1 c 1 0 1 0 /* TX_EN */ 160 1 d 2 0 1 0>; /* CRS */ 161 }; 162 }; 163 }; 164 165 qe@e0100000 { 166 #address-cells = <1>; 167 #size-cells = <1>; 168 device_type = "qe"; 169 model = "QE"; 170 ranges = <0 e0100000 00100000>; 171 reg = <e0100000 480>; 172 brg-frequency = <0>; 173 bus-frequency = <BCD3D80>; 174 175 muram@10000 { 176 device_type = "muram"; 177 ranges = <0 00010000 00004000>; 178 179 data-only@0 { 180 reg = <0 4000>; 181 }; 182 }; 183 184 spi@4c0 { 185 device_type = "spi"; 186 compatible = "fsl_spi"; 187 reg = <4c0 40>; 188 interrupts = <2>; 189 interrupt-parent = <&qeic>; 190 mode = "cpu-qe"; 191 }; 192 193 spi@500 { 194 device_type = "spi"; 195 compatible = "fsl_spi"; 196 reg = <500 40>; 197 interrupts = <1>; 198 interrupt-parent = <&qeic>; 199 mode = "cpu"; 200 }; 201 202 enet0: ucc@3000 { 203 device_type = "network"; 204 compatible = "ucc_geth"; 205 model = "UCC"; 206 cell-index = <2>; 207 device-id = <2>; 208 reg = <3000 200>; 209 interrupts = <21>; 210 interrupt-parent = <&qeic>; 211 local-mac-address = [ 00 00 00 00 00 00 ]; 212 rx-clock-name = "clk16"; 213 tx-clock-name = "clk3"; 214 phy-handle = <&phy00>; 215 pio-handle = <&ucc2pio>; 216 }; 217 218 enet1: ucc@2200 { 219 device_type = "network"; 220 compatible = "ucc_geth"; 221 model = "UCC"; 222 cell-index = <3>; 223 device-id = <3>; 224 reg = <2200 200>; 225 interrupts = <22>; 226 interrupt-parent = <&qeic>; 227 local-mac-address = [ 00 00 00 00 00 00 ]; 228 rx-clock-name = "clk9"; 229 tx-clock-name = "clk10"; 230 phy-handle = <&phy04>; 231 pio-handle = <&ucc3pio>; 232 }; 233 234 mdio@3120 { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 reg = <3120 18>; 238 device_type = "mdio"; 239 compatible = "ucc_geth_phy"; 240 241 phy00:ethernet-phy@00 { 242 interrupt-parent = <&pic>; 243 interrupts = <0>; 244 reg = <0>; 245 device_type = "ethernet-phy"; 246 }; 247 phy04:ethernet-phy@04 { 248 interrupt-parent = <&pic>; 249 interrupts = <0>; 250 reg = <4>; 251 device_type = "ethernet-phy"; 252 }; 253 }; 254 255 qeic:qeic@80 { 256 interrupt-controller; 257 device_type = "qeic"; 258 #address-cells = <0>; 259 #interrupt-cells = <1>; 260 reg = <80 80>; 261 big-endian; 262 interrupts = <20 8 21 8>; //high:32 low:33 263 interrupt-parent = <&pic>; 264 }; 265 }; 266 267 pci0: pci@e0008500 { 268 cell-index = <1>; 269 interrupt-map-mask = <f800 0 0 7>; 270 interrupt-map = < 271 /* IDSEL 0x10 AD16 (USB) */ 272 8000 0 0 1 &pic 11 8 273 274 /* IDSEL 0x11 AD17 (Mini1)*/ 275 8800 0 0 1 &pic 12 8 276 8800 0 0 2 &pic 13 8 277 8800 0 0 3 &pic 14 8 278 8800 0 0 4 &pic 30 8 279 280 /* IDSEL 0x12 AD18 (PCI/Mini2) */ 281 9000 0 0 1 &pic 13 8 282 9000 0 0 2 &pic 14 8 283 9000 0 0 3 &pic 30 8 284 9000 0 0 4 &pic 11 8>; 285 286 interrupt-parent = <&pic>; 287 interrupts = <42 8>; 288 bus-range = <0 0>; 289 ranges = <42000000 0 80000000 80000000 0 10000000 290 02000000 0 90000000 90000000 0 10000000 291 01000000 0 d0000000 d0000000 0 04000000>; 292 clock-frequency = <0>; 293 #interrupt-cells = <1>; 294 #size-cells = <2>; 295 #address-cells = <3>; 296 reg = <e0008500 100>; 297 compatible = "fsl,mpc8349-pci"; 298 device_type = "pci"; 299 }; 300}; 301