1/*
2 * MPC832x RDB Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "MPC8323ERDB";
16	compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,8323@0 {
33			device_type = "cpu";
34			reg = <0x0>;
35			d-cache-line-size = <0x20>;	// 32 bytes
36			i-cache-line-size = <0x20>;	// 32 bytes
37			d-cache-size = <16384>;	// L1, 16K
38			i-cache-size = <16384>;	// L1, 16K
39			timebase-frequency = <0>;
40			bus-frequency = <0>;
41			clock-frequency = <0>;
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x04000000>;
48	};
49
50	soc8323@e0000000 {
51		#address-cells = <1>;
52		#size-cells = <1>;
53		device_type = "soc";
54		ranges = <0x0 0xe0000000 0x00100000>;
55		reg = <0xe0000000 0x00000200>;
56		bus-frequency = <0>;
57
58		wdt@200 {
59			device_type = "watchdog";
60			compatible = "mpc83xx_wdt";
61			reg = <0x200 0x100>;
62		};
63
64		i2c@3000 {
65			#address-cells = <1>;
66			#size-cells = <0>;
67			cell-index = <0>;
68			compatible = "fsl-i2c";
69			reg = <0x3000 0x100>;
70			interrupts = <14 0x8>;
71			interrupt-parent = <&ipic>;
72			dfsrr;
73		};
74
75		serial0: serial@4500 {
76			cell-index = <0>;
77			device_type = "serial";
78			compatible = "ns16550";
79			reg = <0x4500 0x100>;
80			clock-frequency = <0>;
81			interrupts = <9 0x8>;
82			interrupt-parent = <&ipic>;
83		};
84
85		serial1: serial@4600 {
86			cell-index = <1>;
87			device_type = "serial";
88			compatible = "ns16550";
89			reg = <0x4600 0x100>;
90			clock-frequency = <0>;
91			interrupts = <10 0x8>;
92			interrupt-parent = <&ipic>;
93		};
94
95		dma@82a8 {
96			#address-cells = <1>;
97			#size-cells = <1>;
98			compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
99			reg = <0x82a8 4>;
100			ranges = <0 0x8100 0x1a8>;
101			interrupt-parent = <&ipic>;
102			interrupts = <71 8>;
103			cell-index = <0>;
104			dma-channel@0 {
105				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
106				reg = <0 0x80>;
107				interrupt-parent = <&ipic>;
108				interrupts = <71 8>;
109			};
110			dma-channel@80 {
111				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
112				reg = <0x80 0x80>;
113				interrupt-parent = <&ipic>;
114				interrupts = <71 8>;
115			};
116			dma-channel@100 {
117				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
118				reg = <0x100 0x80>;
119				interrupt-parent = <&ipic>;
120				interrupts = <71 8>;
121			};
122			dma-channel@180 {
123				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
124				reg = <0x180 0x28>;
125				interrupt-parent = <&ipic>;
126				interrupts = <71 8>;
127			};
128		};
129
130		crypto@30000 {
131			compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
132			reg = <0x30000 0x10000>;
133			interrupts = <11 0x8>;
134			interrupt-parent = <&ipic>;
135			fsl,num-channels = <1>;
136			fsl,channel-fifo-len = <24>;
137			fsl,exec-units-mask = <0x4c>;
138			fsl,descriptor-types-mask = <0x0122003f>;
139		};
140
141		ipic:pic@700 {
142			interrupt-controller;
143			#address-cells = <0>;
144			#interrupt-cells = <2>;
145			reg = <0x700 0x100>;
146			device_type = "ipic";
147		};
148
149		par_io@1400 {
150			reg = <0x1400 0x100>;
151			device_type = "par_io";
152			num-ports = <7>;
153
154			ucc2pio:ucc_pin@02 {
155				pio-map = <
156			/* port  pin  dir  open_drain  assignment  has_irq */
157					3  4  3  0  2  0 	/* MDIO */
158					3  5  1  0  2  0 	/* MDC */
159					3 21  2  0  1  0 	/* RX_CLK (CLK16) */
160					3 23  2  0  1  0 	/* TX_CLK (CLK3) */
161					0 18  1  0  1  0 	/* TxD0 */
162					0 19  1  0  1  0 	/* TxD1 */
163					0 20  1  0  1  0 	/* TxD2 */
164					0 21  1  0  1  0 	/* TxD3 */
165					0 22  2  0  1  0 	/* RxD0 */
166					0 23  2  0  1  0 	/* RxD1 */
167					0 24  2  0  1  0 	/* RxD2 */
168					0 25  2  0  1  0 	/* RxD3 */
169					0 26  2  0  1  0 	/* RX_ER */
170					0 27  1  0  1  0 	/* TX_ER */
171					0 28  2  0  1  0 	/* RX_DV */
172					0 29  2  0  1  0 	/* COL */
173					0 30  1  0  1  0 	/* TX_EN */
174					0 31  2  0  1  0>;      /* CRS */
175			};
176			ucc3pio:ucc_pin@03 {
177				pio-map = <
178			/* port  pin  dir  open_drain  assignment  has_irq */
179					0 13  2  0  1  0 	/* RX_CLK (CLK9) */
180					3 24  2  0  1  0 	/* TX_CLK (CLK10) */
181					1  0  1  0  1  0 	/* TxD0 */
182					1  1  1  0  1  0 	/* TxD1 */
183					1  2  1  0  1  0 	/* TxD2 */
184					1  3  1  0  1  0 	/* TxD3 */
185					1  4  2  0  1  0 	/* RxD0 */
186					1  5  2  0  1  0 	/* RxD1 */
187					1  6  2  0  1  0 	/* RxD2 */
188					1  7  2  0  1  0 	/* RxD3 */
189					1  8  2  0  1  0 	/* RX_ER */
190					1  9  1  0  1  0 	/* TX_ER */
191					1 10  2  0  1  0 	/* RX_DV */
192					1 11  2  0  1  0 	/* COL */
193					1 12  1  0  1  0 	/* TX_EN */
194					1 13  2  0  1  0>;      /* CRS */
195			};
196		};
197	};
198
199	qe@e0100000 {
200		#address-cells = <1>;
201		#size-cells = <1>;
202		device_type = "qe";
203		compatible = "fsl,qe";
204		ranges = <0x0 0xe0100000 0x00100000>;
205		reg = <0xe0100000 0x480>;
206		brg-frequency = <0>;
207		bus-frequency = <198000000>;
208
209		muram@10000 {
210 			#address-cells = <1>;
211 			#size-cells = <1>;
212			compatible = "fsl,qe-muram", "fsl,cpm-muram";
213			ranges = <0x0 0x00010000 0x00004000>;
214
215			data-only@0 {
216				compatible = "fsl,qe-muram-data",
217					     "fsl,cpm-muram-data";
218				reg = <0x0 0x4000>;
219			};
220		};
221
222		spi@4c0 {
223			cell-index = <0>;
224			compatible = "fsl,spi";
225			reg = <0x4c0 0x40>;
226			interrupts = <2>;
227			interrupt-parent = <&qeic>;
228			mode = "cpu-qe";
229		};
230
231		spi@500 {
232			cell-index = <1>;
233			compatible = "fsl,spi";
234			reg = <0x500 0x40>;
235			interrupts = <1>;
236			interrupt-parent = <&qeic>;
237			mode = "cpu";
238		};
239
240		enet0: ucc@3000 {
241			device_type = "network";
242			compatible = "ucc_geth";
243			cell-index = <2>;
244			reg = <0x3000 0x200>;
245			interrupts = <33>;
246			interrupt-parent = <&qeic>;
247			local-mac-address = [ 00 00 00 00 00 00 ];
248			rx-clock-name = "clk16";
249			tx-clock-name = "clk3";
250			phy-handle = <&phy00>;
251			pio-handle = <&ucc2pio>;
252		};
253
254		enet1: ucc@2200 {
255			device_type = "network";
256			compatible = "ucc_geth";
257			cell-index = <3>;
258			reg = <0x2200 0x200>;
259			interrupts = <34>;
260			interrupt-parent = <&qeic>;
261			local-mac-address = [ 00 00 00 00 00 00 ];
262			rx-clock-name = "clk9";
263			tx-clock-name = "clk10";
264			phy-handle = <&phy04>;
265			pio-handle = <&ucc3pio>;
266		};
267
268		mdio@3120 {
269			#address-cells = <1>;
270			#size-cells = <0>;
271			reg = <0x3120 0x18>;
272			compatible = "fsl,ucc-mdio";
273
274			phy00:ethernet-phy@00 {
275				interrupt-parent = <&ipic>;
276				interrupts = <0>;
277				reg = <0x0>;
278				device_type = "ethernet-phy";
279			};
280			phy04:ethernet-phy@04 {
281				interrupt-parent = <&ipic>;
282				interrupts = <0>;
283				reg = <0x4>;
284				device_type = "ethernet-phy";
285			};
286		};
287
288		qeic:interrupt-controller@80 {
289			interrupt-controller;
290			compatible = "fsl,qe-ic";
291			#address-cells = <0>;
292			#interrupt-cells = <1>;
293			reg = <0x80 0x80>;
294			big-endian;
295			interrupts = <32 0x8 33 0x8>; //high:32 low:33
296			interrupt-parent = <&ipic>;
297		};
298	};
299
300	pci0: pci@e0008500 {
301		cell-index = <1>;
302		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
303		interrupt-map = <
304				/* IDSEL 0x10 AD16 (USB) */
305				 0x8000 0x0 0x0 0x1 &ipic 17 0x8
306
307				/* IDSEL 0x11 AD17 (Mini1)*/
308				 0x8800 0x0 0x0 0x1 &ipic 18 0x8
309				 0x8800 0x0 0x0 0x2 &ipic 19 0x8
310				 0x8800 0x0 0x0 0x3 &ipic 20 0x8
311				 0x8800 0x0 0x0 0x4 &ipic 48 0x8
312
313				/* IDSEL 0x12 AD18 (PCI/Mini2) */
314				 0x9000 0x0 0x0 0x1 &ipic 19 0x8
315				 0x9000 0x0 0x0 0x2 &ipic 20 0x8
316				 0x9000 0x0 0x0 0x3 &ipic 48 0x8
317				 0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
318
319		interrupt-parent = <&ipic>;
320		interrupts = <66 0x8>;
321		bus-range = <0x0 0x0>;
322		ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
323			  0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
324			  0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
325		clock-frequency = <0>;
326		#interrupt-cells = <1>;
327		#size-cells = <2>;
328		#address-cells = <3>;
329		reg = <0xe0008500 0x100>;
330		compatible = "fsl,mpc8349-pci";
331		device_type = "pci";
332	};
333};
334