1/*
2 * MPC832x RDB Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/ {
13	model = "MPC8323ERDB";
14	compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
15	#address-cells = <1>;
16	#size-cells = <1>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		PowerPC,8323@0 {
23			device_type = "cpu";
24			reg = <0>;
25			d-cache-line-size = <20>;	// 32 bytes
26			i-cache-line-size = <20>;	// 32 bytes
27			d-cache-size = <4000>;		// L1, 16K
28			i-cache-size = <4000>;		// L1, 16K
29			timebase-frequency = <0>;
30			bus-frequency = <0>;
31			clock-frequency = <0>;
32		};
33	};
34
35	memory {
36		device_type = "memory";
37		reg = <00000000 04000000>;
38	};
39
40	soc8323@e0000000 {
41		#address-cells = <1>;
42		#size-cells = <1>;
43		device_type = "soc";
44		ranges = <0 e0000000 00100000>;
45		reg = <e0000000 00000200>;
46		bus-frequency = <0>;
47
48		wdt@200 {
49			device_type = "watchdog";
50			compatible = "mpc83xx_wdt";
51			reg = <200 100>;
52		};
53
54		i2c@3000 {
55			device_type = "i2c";
56			compatible = "fsl-i2c";
57			reg = <3000 100>;
58			interrupts = <e 8>;
59			interrupt-parent = <&pic>;
60			dfsrr;
61		};
62
63		serial@4500 {
64			device_type = "serial";
65			compatible = "ns16550";
66			reg = <4500 100>;
67			clock-frequency = <0>;
68			interrupts = <9 8>;
69			interrupt-parent = <&pic>;
70		};
71
72		serial@4600 {
73			device_type = "serial";
74			compatible = "ns16550";
75			reg = <4600 100>;
76			clock-frequency = <0>;
77			interrupts = <a 8>;
78			interrupt-parent = <&pic>;
79		};
80
81		crypto@30000 {
82			device_type = "crypto";
83			model = "SEC2";
84			compatible = "talitos";
85			reg = <30000 7000>;
86			interrupts = <b 8>;
87			interrupt-parent = <&pic>;
88			/* Rev. 2.2 */
89			num-channels = <1>;
90			channel-fifo-len = <18>;
91			exec-units-mask = <0000004c>;
92			descriptor-types-mask = <0122003f>;
93		};
94
95		pic:pic@700 {
96			interrupt-controller;
97			#address-cells = <0>;
98			#interrupt-cells = <2>;
99			reg = <700 100>;
100			device_type = "ipic";
101		};
102
103		par_io@1400 {
104			reg = <1400 100>;
105			device_type = "par_io";
106			num-ports = <7>;
107
108			ucc2pio:ucc_pin@02 {
109				pio-map = <
110			/* port  pin  dir  open_drain  assignment  has_irq */
111					3  4  3  0  2  0 	/* MDIO */
112					3  5  1  0  2  0 	/* MDC */
113					3 15  2  0  1  0 	/* RX_CLK (CLK16) */
114					3 17  2  0  1  0 	/* TX_CLK (CLK3) */
115					0 12  1  0  1  0 	/* TxD0 */
116					0 13  1  0  1  0 	/* TxD1 */
117					0 14  1  0  1  0 	/* TxD2 */
118					0 15  1  0  1  0 	/* TxD3 */
119					0 16  2  0  1  0 	/* RxD0 */
120					0 17  2  0  1  0 	/* RxD1 */
121					0 18  2  0  1  0 	/* RxD2 */
122					0 19  2  0  1  0 	/* RxD3 */
123					0 1a  2  0  1  0 	/* RX_ER */
124					0 1b  1  0  1  0 	/* TX_ER */
125					0 1c  2  0  1  0 	/* RX_DV */
126					0 1d  2  0  1  0 	/* COL */
127					0 1e  1  0  1  0 	/* TX_EN */
128					0 1f  2  0  1  0>;      /* CRS */
129			};
130			ucc3pio:ucc_pin@03 {
131				pio-map = <
132			/* port  pin  dir  open_drain  assignment  has_irq */
133					0  d  2  0  1  0 	/* RX_CLK (CLK9) */
134					3 18  2  0  1  0 	/* TX_CLK (CLK10) */
135					1  0  1  0  1  0 	/* TxD0 */
136					1  1  1  0  1  0 	/* TxD1 */
137					1  2  1  0  1  0 	/* TxD2 */
138					1  3  1  0  1  0 	/* TxD3 */
139					1  4  2  0  1  0 	/* RxD0 */
140					1  5  2  0  1  0 	/* RxD1 */
141					1  6  2  0  1  0 	/* RxD2 */
142					1  7  2  0  1  0 	/* RxD3 */
143					1  8  2  0  1  0 	/* RX_ER */
144					1  9  1  0  1  0 	/* TX_ER */
145					1  a  2  0  1  0 	/* RX_DV */
146					1  b  2  0  1  0 	/* COL */
147					1  c  1  0  1  0 	/* TX_EN */
148					1  d  2  0  1  0>;      /* CRS */
149			};
150		};
151	};
152
153	qe@e0100000 {
154		#address-cells = <1>;
155		#size-cells = <1>;
156		device_type = "qe";
157		model = "QE";
158		ranges = <0 e0100000 00100000>;
159		reg = <e0100000 480>;
160		brg-frequency = <0>;
161		bus-frequency = <BCD3D80>;
162
163		muram@10000 {
164			device_type = "muram";
165			ranges = <0 00010000 00004000>;
166
167			data-only@0 {
168				reg = <0 4000>;
169			};
170		};
171
172		spi@4c0 {
173			device_type = "spi";
174			compatible = "fsl_spi";
175			reg = <4c0 40>;
176			interrupts = <2>;
177			interrupt-parent = <&qeic>;
178			mode = "cpu";
179		};
180
181		spi@500 {
182			device_type = "spi";
183			compatible = "fsl_spi";
184			reg = <500 40>;
185			interrupts = <1>;
186			interrupt-parent = <&qeic>;
187			mode = "cpu";
188		};
189
190		ucc@3000 {
191			device_type = "network";
192			compatible = "ucc_geth";
193			model = "UCC";
194			device-id = <2>;
195			reg = <3000 200>;
196			interrupts = <21>;
197			interrupt-parent = <&qeic>;
198			/*
199			 * mac-address is deprecated and will be removed
200			 * in 2.6.25.  Only recent versions of
201			 * U-Boot support local-mac-address, however.
202			 */
203			mac-address = [ 00 00 00 00 00 00 ];
204			local-mac-address = [ 00 00 00 00 00 00 ];
205			rx-clock = <20>;
206			tx-clock = <13>;
207			phy-handle = <&phy00>;
208			pio-handle = <&ucc2pio>;
209		};
210
211		ucc@2200 {
212			device_type = "network";
213			compatible = "ucc_geth";
214			model = "UCC";
215			device-id = <3>;
216			reg = <2200 200>;
217			interrupts = <22>;
218			interrupt-parent = <&qeic>;
219			/*
220			 * mac-address is deprecated and will be removed
221			 * in 2.6.25.  Only recent versions of
222			 * U-Boot support local-mac-address, however.
223			 */
224			mac-address = [ 00 00 00 00 00 00 ];
225			local-mac-address = [ 00 00 00 00 00 00 ];
226			rx-clock = <19>;
227			tx-clock = <1a>;
228			phy-handle = <&phy04>;
229			pio-handle = <&ucc3pio>;
230		};
231
232		mdio@3120 {
233			#address-cells = <1>;
234			#size-cells = <0>;
235			reg = <3120 18>;
236			device_type = "mdio";
237			compatible = "ucc_geth_phy";
238
239			phy00:ethernet-phy@00 {
240				interrupt-parent = <&pic>;
241				interrupts = <0>;
242				reg = <0>;
243				device_type = "ethernet-phy";
244			};
245			phy04:ethernet-phy@04 {
246				interrupt-parent = <&pic>;
247				interrupts = <0>;
248				reg = <4>;
249				device_type = "ethernet-phy";
250			};
251		};
252
253		qeic:qeic@80 {
254			interrupt-controller;
255			device_type = "qeic";
256			#address-cells = <0>;
257			#interrupt-cells = <1>;
258			reg = <80 80>;
259			big-endian;
260			interrupts = <20 8 21 8>; //high:32 low:33
261			interrupt-parent = <&pic>;
262		};
263	};
264
265	pci@e0008500 {
266		interrupt-map-mask = <f800 0 0 7>;
267		interrupt-map = <
268				/* IDSEL 0x10 AD16 (USB) */
269				 8000 0 0 1 &pic 11 8
270
271				/* IDSEL 0x11 AD17 (Mini1)*/
272				 8800 0 0 1 &pic 12 8
273				 8800 0 0 2 &pic 13 8
274				 8800 0 0 3 &pic 14 8
275				 8800 0 0 4 &pic 30 8
276
277				/* IDSEL 0x12 AD18 (PCI/Mini2) */
278				 9000 0 0 1 &pic 13 8
279				 9000 0 0 2 &pic 14 8
280				 9000 0 0 3 &pic 30 8
281				 9000 0 0 4 &pic 11 8>;
282
283		interrupt-parent = <&pic>;
284		interrupts = <42 8>;
285		bus-range = <0 0>;
286		ranges = <42000000 0 80000000 80000000 0 10000000
287			  02000000 0 90000000 90000000 0 10000000
288			  01000000 0 d0000000 d0000000 0 04000000>;
289		clock-frequency = <0>;
290		#interrupt-cells = <1>;
291		#size-cells = <2>;
292		#address-cells = <3>;
293		reg = <e0008500 100>;
294		compatible = "fsl,mpc8349-pci";
295		device_type = "pci";
296	};
297};
298