1/* 2 * MPC8313E RDB Device Tree Source 3 * 4 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/ { 13 model = "MPC8313ERDB"; 14 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 aliases { 19 ethernet0 = &enet0; 20 ethernet1 = &enet1; 21 serial0 = &serial0; 22 serial1 = &serial1; 23 pci0 = &pci0; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 PowerPC,8313@0 { 31 device_type = "cpu"; 32 reg = <0>; 33 d-cache-line-size = <20>; // 32 bytes 34 i-cache-line-size = <20>; // 32 bytes 35 d-cache-size = <4000>; // L1, 16K 36 i-cache-size = <4000>; // L1, 16K 37 timebase-frequency = <0>; // from bootloader 38 bus-frequency = <0>; // from bootloader 39 clock-frequency = <0>; // from bootloader 40 }; 41 }; 42 43 memory { 44 device_type = "memory"; 45 reg = <00000000 08000000>; // 128MB at 0 46 }; 47 48 localbus@e0005000 { 49 #address-cells = <2>; 50 #size-cells = <1>; 51 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus"; 52 reg = <e0005000 1000>; 53 interrupts = <d#77 8>; 54 interrupt-parent = <&ipic>; 55 56 // CS0 and CS1 are swapped when 57 // booting from nand, but the 58 // addresses are the same. 59 ranges = <0 0 fe000000 00800000 60 1 0 e2800000 00008000 61 2 0 f0000000 00020000 62 3 0 fa000000 00008000>; 63 64 nand@1,0 { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 compatible = "fsl,mpc8313-fcm-nand", 68 "fsl,elbc-fcm-nand"; 69 reg = <1 0 2000>; 70 71 u-boot@0 { 72 reg = <0 100000>; 73 read-only; 74 }; 75 76 kernel@100000 { 77 reg = <100000 300000>; 78 }; 79 80 fs@400000 { 81 reg = <400000 1c00000>; 82 }; 83 }; 84 }; 85 86 soc8313@e0000000 { 87 #address-cells = <1>; 88 #size-cells = <1>; 89 device_type = "soc"; 90 compatible = "simple-bus"; 91 ranges = <0 e0000000 00100000>; 92 reg = <e0000000 00000200>; 93 bus-frequency = <0>; 94 95 wdt@200 { 96 device_type = "watchdog"; 97 compatible = "mpc83xx_wdt"; 98 reg = <200 100>; 99 }; 100 101 i2c@3000 { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 cell-index = <0>; 105 compatible = "fsl-i2c"; 106 reg = <3000 100>; 107 interrupts = <e 8>; 108 interrupt-parent = < &ipic >; 109 dfsrr; 110 }; 111 112 i2c@3100 { 113 #address-cells = <1>; 114 #size-cells = <0>; 115 cell-index = <1>; 116 compatible = "fsl-i2c"; 117 reg = <3100 100>; 118 interrupts = <f 8>; 119 interrupt-parent = < &ipic >; 120 dfsrr; 121 }; 122 123 spi@7000 { 124 device_type = "spi"; 125 compatible = "fsl_spi"; 126 reg = <7000 1000>; 127 interrupts = <10 8>; 128 interrupt-parent = < &ipic >; 129 mode = "cpu"; 130 }; 131 132 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 133 usb@23000 { 134 compatible = "fsl-usb2-dr"; 135 reg = <23000 1000>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 interrupt-parent = < &ipic >; 139 interrupts = <26 8>; 140 phy_type = "utmi_wide"; 141 }; 142 143 mdio@24520 { 144 #address-cells = <1>; 145 #size-cells = <0>; 146 compatible = "fsl,gianfar-mdio"; 147 reg = <24520 20>; 148 phy1: ethernet-phy@1 { 149 interrupt-parent = < &ipic >; 150 interrupts = <13 8>; 151 reg = <1>; 152 device_type = "ethernet-phy"; 153 }; 154 phy4: ethernet-phy@4 { 155 interrupt-parent = < &ipic >; 156 interrupts = <14 8>; 157 reg = <4>; 158 device_type = "ethernet-phy"; 159 }; 160 }; 161 162 enet0: ethernet@24000 { 163 cell-index = <0>; 164 device_type = "network"; 165 model = "eTSEC"; 166 compatible = "gianfar"; 167 reg = <24000 1000>; 168 local-mac-address = [ 00 00 00 00 00 00 ]; 169 interrupts = <25 8 24 8 23 8>; 170 interrupt-parent = < &ipic >; 171 phy-handle = < &phy1 >; 172 }; 173 174 enet1: ethernet@25000 { 175 cell-index = <1>; 176 device_type = "network"; 177 model = "eTSEC"; 178 compatible = "gianfar"; 179 reg = <25000 1000>; 180 local-mac-address = [ 00 00 00 00 00 00 ]; 181 interrupts = <22 8 21 8 20 8>; 182 interrupt-parent = < &ipic >; 183 phy-handle = < &phy4 >; 184 }; 185 186 serial0: serial@4500 { 187 cell-index = <0>; 188 device_type = "serial"; 189 compatible = "ns16550"; 190 reg = <4500 100>; 191 clock-frequency = <0>; 192 interrupts = <9 8>; 193 interrupt-parent = < &ipic >; 194 }; 195 196 serial1: serial@4600 { 197 cell-index = <1>; 198 device_type = "serial"; 199 compatible = "ns16550"; 200 reg = <4600 100>; 201 clock-frequency = <0>; 202 interrupts = <a 8>; 203 interrupt-parent = < &ipic >; 204 }; 205 206 crypto@30000 { 207 device_type = "crypto"; 208 model = "SEC2"; 209 compatible = "talitos"; 210 reg = <30000 7000>; 211 interrupts = <b 8>; 212 interrupt-parent = < &ipic >; 213 /* Rev. 2.2 */ 214 num-channels = <1>; 215 channel-fifo-len = <18>; 216 exec-units-mask = <0000004c>; 217 descriptor-types-mask = <0122003f>; 218 }; 219 220 /* IPIC 221 * interrupts cell = <intr #, sense> 222 * sense values match linux IORESOURCE_IRQ_* defines: 223 * sense == 8: Level, low assertion 224 * sense == 2: Edge, high-to-low change 225 */ 226 ipic: pic@700 { 227 interrupt-controller; 228 #address-cells = <0>; 229 #interrupt-cells = <2>; 230 reg = <700 100>; 231 device_type = "ipic"; 232 }; 233 }; 234 235 pci0: pci@e0008500 { 236 cell-index = <1>; 237 interrupt-map-mask = <f800 0 0 7>; 238 interrupt-map = < 239 240 /* IDSEL 0x0E -mini PCI */ 241 7000 0 0 1 &ipic 12 8 242 7000 0 0 2 &ipic 12 8 243 7000 0 0 3 &ipic 12 8 244 7000 0 0 4 &ipic 12 8 245 246 /* IDSEL 0x0F - PCI slot */ 247 7800 0 0 1 &ipic 11 8 248 7800 0 0 2 &ipic 12 8 249 7800 0 0 3 &ipic 11 8 250 7800 0 0 4 &ipic 12 8>; 251 interrupt-parent = < &ipic >; 252 interrupts = <42 8>; 253 bus-range = <0 0>; 254 ranges = <02000000 0 90000000 90000000 0 10000000 255 42000000 0 80000000 80000000 0 10000000 256 01000000 0 00000000 e2000000 0 00100000>; 257 clock-frequency = <3f940aa>; 258 #interrupt-cells = <1>; 259 #size-cells = <2>; 260 #address-cells = <3>; 261 reg = <e0008500 100>; 262 compatible = "fsl,mpc8349-pci"; 263 device_type = "pci"; 264 }; 265}; 266