1/* 2 * MPC8313E RDB Device Tree Source 3 * 4 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/ { 13 model = "MPC8313ERDB"; 14 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 PowerPC,8313@0 { 23 device_type = "cpu"; 24 reg = <0>; 25 d-cache-line-size = <20>; // 32 bytes 26 i-cache-line-size = <20>; // 32 bytes 27 d-cache-size = <4000>; // L1, 16K 28 i-cache-size = <4000>; // L1, 16K 29 timebase-frequency = <0>; // from bootloader 30 bus-frequency = <0>; // from bootloader 31 clock-frequency = <0>; // from bootloader 32 }; 33 }; 34 35 memory { 36 device_type = "memory"; 37 reg = <00000000 08000000>; // 128MB at 0 38 }; 39 40 soc8313@e0000000 { 41 #address-cells = <1>; 42 #size-cells = <1>; 43 device_type = "soc"; 44 ranges = <0 e0000000 00100000>; 45 reg = <e0000000 00000200>; 46 bus-frequency = <0>; 47 48 wdt@200 { 49 device_type = "watchdog"; 50 compatible = "mpc83xx_wdt"; 51 reg = <200 100>; 52 }; 53 54 i2c@3000 { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 cell-index = <0>; 58 compatible = "fsl-i2c"; 59 reg = <3000 100>; 60 interrupts = <e 8>; 61 interrupt-parent = < &ipic >; 62 dfsrr; 63 }; 64 65 i2c@3100 { 66 #address-cells = <1>; 67 #size-cells = <0>; 68 cell-index = <1>; 69 compatible = "fsl-i2c"; 70 reg = <3100 100>; 71 interrupts = <f 8>; 72 interrupt-parent = < &ipic >; 73 dfsrr; 74 }; 75 76 spi@7000 { 77 device_type = "spi"; 78 compatible = "fsl_spi"; 79 reg = <7000 1000>; 80 interrupts = <10 8>; 81 interrupt-parent = < &ipic >; 82 mode = "cpu"; 83 }; 84 85 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 86 usb@23000 { 87 device_type = "usb"; 88 compatible = "fsl-usb2-dr"; 89 reg = <23000 1000>; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 interrupt-parent = < &ipic >; 93 interrupts = <26 8>; 94 phy_type = "utmi_wide"; 95 }; 96 97 mdio@24520 { 98 device_type = "mdio"; 99 compatible = "gianfar"; 100 reg = <24520 20>; 101 #address-cells = <1>; 102 #size-cells = <0>; 103 phy1: ethernet-phy@1 { 104 interrupt-parent = < &ipic >; 105 interrupts = <13 8>; 106 reg = <1>; 107 device_type = "ethernet-phy"; 108 }; 109 phy4: ethernet-phy@4 { 110 interrupt-parent = < &ipic >; 111 interrupts = <14 8>; 112 reg = <4>; 113 device_type = "ethernet-phy"; 114 }; 115 }; 116 117 ethernet@24000 { 118 device_type = "network"; 119 model = "eTSEC"; 120 compatible = "gianfar"; 121 reg = <24000 1000>; 122 local-mac-address = [ 00 00 00 00 00 00 ]; 123 interrupts = <25 8 24 8 23 8>; 124 interrupt-parent = < &ipic >; 125 phy-handle = < &phy1 >; 126 }; 127 128 ethernet@25000 { 129 device_type = "network"; 130 model = "eTSEC"; 131 compatible = "gianfar"; 132 reg = <25000 1000>; 133 local-mac-address = [ 00 00 00 00 00 00 ]; 134 interrupts = <22 8 21 8 20 8>; 135 interrupt-parent = < &ipic >; 136 phy-handle = < &phy4 >; 137 }; 138 139 serial@4500 { 140 device_type = "serial"; 141 compatible = "ns16550"; 142 reg = <4500 100>; 143 clock-frequency = <0>; 144 interrupts = <9 8>; 145 interrupt-parent = < &ipic >; 146 }; 147 148 serial@4600 { 149 device_type = "serial"; 150 compatible = "ns16550"; 151 reg = <4600 100>; 152 clock-frequency = <0>; 153 interrupts = <a 8>; 154 interrupt-parent = < &ipic >; 155 }; 156 157 crypto@30000 { 158 device_type = "crypto"; 159 model = "SEC2"; 160 compatible = "talitos"; 161 reg = <30000 7000>; 162 interrupts = <b 8>; 163 interrupt-parent = < &ipic >; 164 /* Rev. 2.2 */ 165 num-channels = <1>; 166 channel-fifo-len = <18>; 167 exec-units-mask = <0000004c>; 168 descriptor-types-mask = <0122003f>; 169 }; 170 171 /* IPIC 172 * interrupts cell = <intr #, sense> 173 * sense values match linux IORESOURCE_IRQ_* defines: 174 * sense == 8: Level, low assertion 175 * sense == 2: Edge, high-to-low change 176 */ 177 ipic: pic@700 { 178 interrupt-controller; 179 #address-cells = <0>; 180 #interrupt-cells = <2>; 181 reg = <700 100>; 182 device_type = "ipic"; 183 }; 184 }; 185 186 pci@e0008500 { 187 interrupt-map-mask = <f800 0 0 7>; 188 interrupt-map = < 189 190 /* IDSEL 0x0E -mini PCI */ 191 7000 0 0 1 &ipic 12 8 192 7000 0 0 2 &ipic 12 8 193 7000 0 0 3 &ipic 12 8 194 7000 0 0 4 &ipic 12 8 195 196 /* IDSEL 0x0F - PCI slot */ 197 7800 0 0 1 &ipic 11 8 198 7800 0 0 2 &ipic 12 8 199 7800 0 0 3 &ipic 11 8 200 7800 0 0 4 &ipic 12 8>; 201 interrupt-parent = < &ipic >; 202 interrupts = <42 8>; 203 bus-range = <0 0>; 204 ranges = <02000000 0 90000000 90000000 0 10000000 205 42000000 0 80000000 80000000 0 10000000 206 01000000 0 00000000 e2000000 0 00100000>; 207 clock-frequency = <3f940aa>; 208 #interrupt-cells = <1>; 209 #size-cells = <2>; 210 #address-cells = <3>; 211 reg = <e0008500 100>; 212 compatible = "fsl,mpc8349-pci"; 213 device_type = "pci"; 214 }; 215}; 216