1/*
2 * MPC8313E RDB Device Tree Source
3 *
4 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "MPC8313ERDB";
16	compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,8313@0 {
33			device_type = "cpu";
34			reg = <0x0>;
35			d-cache-line-size = <32>;
36			i-cache-line-size = <32>;
37			d-cache-size = <16384>;
38			i-cache-size = <16384>;
39			timebase-frequency = <0>;	// from bootloader
40			bus-frequency = <0>;		// from bootloader
41			clock-frequency = <0>;		// from bootloader
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x08000000>;	// 128MB at 0
48	};
49
50	localbus@e0005000 {
51		#address-cells = <2>;
52		#size-cells = <1>;
53		compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
54		reg = <0xe0005000 0x1000>;
55		interrupts = <77 0x8>;
56		interrupt-parent = <&ipic>;
57
58		// CS0 and CS1 are swapped when
59		// booting from nand, but the
60		// addresses are the same.
61		ranges = <0x0 0x0 0xfe000000 0x00800000
62		          0x1 0x0 0xe2800000 0x00008000
63		          0x2 0x0 0xf0000000 0x00020000
64		          0x3 0x0 0xfa000000 0x00008000>;
65
66		flash@0,0 {
67			#address-cells = <1>;
68			#size-cells = <1>;
69			compatible = "cfi-flash";
70			reg = <0x0 0x0 0x800000>;
71			bank-width = <2>;
72			device-width = <1>;
73		};
74
75		nand@1,0 {
76			#address-cells = <1>;
77			#size-cells = <1>;
78			compatible = "fsl,mpc8313-fcm-nand",
79			             "fsl,elbc-fcm-nand";
80			reg = <0x1 0x0 0x2000>;
81
82			u-boot@0 {
83				reg = <0x0 0x100000>;
84				read-only;
85			};
86
87			kernel@100000 {
88				reg = <0x100000 0x300000>;
89			};
90
91			fs@400000 {
92				reg = <0x400000 0x1c00000>;
93			};
94		};
95	};
96
97	soc8313@e0000000 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		device_type = "soc";
101		compatible = "simple-bus";
102		ranges = <0x0 0xe0000000 0x00100000>;
103		reg = <0xe0000000 0x00000200>;
104		bus-frequency = <0>;
105
106		wdt@200 {
107			device_type = "watchdog";
108			compatible = "mpc83xx_wdt";
109			reg = <0x200 0x100>;
110		};
111
112		sleep-nexus {
113			#address-cells = <1>;
114			#size-cells = <1>;
115			compatible = "simple-bus";
116			sleep = <&pmc 0x03000000>;
117			ranges;
118
119			i2c@3000 {
120				#address-cells = <1>;
121				#size-cells = <0>;
122				cell-index = <0>;
123				compatible = "fsl-i2c";
124				reg = <0x3000 0x100>;
125				interrupts = <14 0x8>;
126				interrupt-parent = <&ipic>;
127				dfsrr;
128				rtc@68 {
129					compatible = "dallas,ds1339";
130					reg = <0x68>;
131				};
132			};
133
134			crypto@30000 {
135				compatible = "fsl,sec2.2", "fsl,sec2.1",
136				             "fsl,sec2.0";
137				reg = <0x30000 0x10000>;
138				interrupts = <11 0x8>;
139				interrupt-parent = <&ipic>;
140				fsl,num-channels = <1>;
141				fsl,channel-fifo-len = <24>;
142				fsl,exec-units-mask = <0x4c>;
143				fsl,descriptor-types-mask = <0x0122003f>;
144			};
145		};
146
147		i2c@3100 {
148			#address-cells = <1>;
149			#size-cells = <0>;
150			cell-index = <1>;
151			compatible = "fsl-i2c";
152			reg = <0x3100 0x100>;
153			interrupts = <15 0x8>;
154			interrupt-parent = <&ipic>;
155			dfsrr;
156		};
157
158		spi@7000 {
159			cell-index = <0>;
160			compatible = "fsl,spi";
161			reg = <0x7000 0x1000>;
162			interrupts = <16 0x8>;
163			interrupt-parent = <&ipic>;
164			mode = "cpu";
165		};
166
167		/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
168		usb@23000 {
169			compatible = "fsl-usb2-dr";
170			reg = <0x23000 0x1000>;
171			#address-cells = <1>;
172			#size-cells = <0>;
173			interrupt-parent = <&ipic>;
174			interrupts = <38 0x8>;
175			phy_type = "utmi_wide";
176			sleep = <&pmc 0x00300000>;
177		};
178
179		enet0: ethernet@24000 {
180			#address-cells = <1>;
181			#size-cells = <1>;
182			sleep = <&pmc 0x20000000>;
183			ranges;
184
185			cell-index = <0>;
186			device_type = "network";
187			model = "eTSEC";
188			compatible = "gianfar";
189			reg = <0x24000 0x1000>;
190			local-mac-address = [ 00 00 00 00 00 00 ];
191			interrupts = <37 0x8 36 0x8 35 0x8>;
192			interrupt-parent = <&ipic>;
193			tbi-handle = < &tbi0 >;
194			/* Vitesse 7385 isn't on the MDIO bus */
195			fixed-link = <1 1 1000 0 0>;
196			fsl,magic-packet;
197
198			mdio@24520 {
199				#address-cells = <1>;
200				#size-cells = <0>;
201				compatible = "fsl,gianfar-mdio";
202				reg = <0x24520 0x20>;
203				phy4: ethernet-phy@4 {
204					interrupt-parent = <&ipic>;
205					interrupts = <20 0x8>;
206					reg = <0x4>;
207					device_type = "ethernet-phy";
208				};
209				tbi0: tbi-phy@11 {
210					reg = <0x11>;
211					device_type = "tbi-phy";
212				};
213			};
214		};
215
216		enet1: ethernet@25000 {
217			#address-cells = <1>;
218			#size-cells = <1>;
219			cell-index = <1>;
220			device_type = "network";
221			model = "eTSEC";
222			compatible = "gianfar";
223			reg = <0x25000 0x1000>;
224			local-mac-address = [ 00 00 00 00 00 00 ];
225			interrupts = <34 0x8 33 0x8 32 0x8>;
226			interrupt-parent = <&ipic>;
227			tbi-handle = < &tbi1 >;
228			phy-handle = < &phy4 >;
229			sleep = <&pmc 0x10000000>;
230			fsl,magic-packet;
231
232			mdio@25520 {
233				#address-cells = <1>;
234				#size-cells = <0>;
235				compatible = "fsl,gianfar-tbi";
236				reg = <0x25520 0x20>;
237
238				tbi1: tbi-phy@11 {
239					reg = <0x11>;
240					device_type = "tbi-phy";
241				};
242			};
243
244
245		};
246
247		serial0: serial@4500 {
248			cell-index = <0>;
249			device_type = "serial";
250			compatible = "ns16550";
251			reg = <0x4500 0x100>;
252			clock-frequency = <0>;
253			interrupts = <9 0x8>;
254			interrupt-parent = <&ipic>;
255		};
256
257		serial1: serial@4600 {
258			cell-index = <1>;
259			device_type = "serial";
260			compatible = "ns16550";
261			reg = <0x4600 0x100>;
262			clock-frequency = <0>;
263			interrupts = <10 0x8>;
264			interrupt-parent = <&ipic>;
265		};
266
267		/* IPIC
268		 * interrupts cell = <intr #, sense>
269		 * sense values match linux IORESOURCE_IRQ_* defines:
270		 * sense == 8: Level, low assertion
271		 * sense == 2: Edge, high-to-low change
272		 */
273		ipic: pic@700 {
274			interrupt-controller;
275			#address-cells = <0>;
276			#interrupt-cells = <2>;
277			reg = <0x700 0x100>;
278			device_type = "ipic";
279		};
280
281		pmc: power@b00 {
282			compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
283			reg = <0xb00 0x100 0xa00 0x100>;
284			interrupts = <80 8>;
285			interrupt-parent = <&ipic>;
286			fsl,mpc8313-wakeup-timer = <&gtm1>;
287
288			/* Remove this (or change to "okay") if you have
289			 * a REVA3 or later board, if you apply one of the
290			 * workarounds listed in section 8.5 of the board
291			 * manual, or if you are adapting this device tree
292			 * to a different board.
293			 */
294			status = "fail";
295		};
296
297		gtm1: timer@500 {
298			compatible = "fsl,mpc8313-gtm", "fsl,gtm";
299			reg = <0x500 0x100>;
300			interrupts = <90 8 78 8 84 8 72 8>;
301			interrupt-parent = <&ipic>;
302		};
303
304		timer@600 {
305			compatible = "fsl,mpc8313-gtm", "fsl,gtm";
306			reg = <0x600 0x100>;
307			interrupts = <91 8 79 8 85 8 73 8>;
308			interrupt-parent = <&ipic>;
309		};
310	};
311
312	sleep-nexus {
313		#address-cells = <1>;
314		#size-cells = <1>;
315		compatible = "simple-bus";
316		sleep = <&pmc 0x00010000>;
317		ranges;
318
319		pci0: pci@e0008500 {
320			cell-index = <1>;
321			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
322			interrupt-map = <
323					/* IDSEL 0x0E -mini PCI */
324					 0x7000 0x0 0x0 0x1 &ipic 18 0x8
325					 0x7000 0x0 0x0 0x2 &ipic 18 0x8
326					 0x7000 0x0 0x0 0x3 &ipic 18 0x8
327					 0x7000 0x0 0x0 0x4 &ipic 18 0x8
328
329					/* IDSEL 0x0F - PCI slot */
330					 0x7800 0x0 0x0 0x1 &ipic 17 0x8
331					 0x7800 0x0 0x0 0x2 &ipic 18 0x8
332					 0x7800 0x0 0x0 0x3 &ipic 17 0x8
333					 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
334			interrupt-parent = <&ipic>;
335			interrupts = <66 0x8>;
336			bus-range = <0x0 0x0>;
337			ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
338				  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
339				  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
340			clock-frequency = <66666666>;
341			#interrupt-cells = <1>;
342			#size-cells = <2>;
343			#address-cells = <3>;
344			reg = <0xe0008500 0x100		/* internal registers */
345			       0xe0008300 0x8>;		/* config space access registers */
346			compatible = "fsl,mpc8349-pci";
347			device_type = "pci";
348		};
349
350		dma@82a8 {
351			#address-cells = <1>;
352			#size-cells = <1>;
353			compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
354			reg = <0xe00082a8 4>;
355			ranges = <0 0xe0008100 0x1a8>;
356			interrupt-parent = <&ipic>;
357			interrupts = <71 8>;
358
359			dma-channel@0 {
360				compatible = "fsl,mpc8313-dma-channel",
361				             "fsl,elo-dma-channel";
362				reg = <0 0x28>;
363				interrupt-parent = <&ipic>;
364				interrupts = <71 8>;
365				cell-index = <0>;
366			};
367
368			dma-channel@80 {
369				compatible = "fsl,mpc8313-dma-channel",
370				             "fsl,elo-dma-channel";
371				reg = <0x80 0x28>;
372				interrupt-parent = <&ipic>;
373				interrupts = <71 8>;
374				cell-index = <1>;
375			};
376
377			dma-channel@100 {
378				compatible = "fsl,mpc8313-dma-channel",
379				             "fsl,elo-dma-channel";
380				reg = <0x100 0x28>;
381				interrupt-parent = <&ipic>;
382				interrupts = <71 8>;
383				cell-index = <2>;
384			};
385
386			dma-channel@180 {
387				compatible = "fsl,mpc8313-dma-channel",
388				             "fsl,elo-dma-channel";
389				reg = <0x180 0x28>;
390				interrupt-parent = <&ipic>;
391				interrupts = <71 8>;
392				cell-index = <3>;
393			};
394		};
395	};
396};
397