1/*
2 * MPC8313E RDB Device Tree Source
3 *
4 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "MPC8313ERDB";
16	compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,8313@0 {
33			device_type = "cpu";
34			reg = <0x0>;
35			d-cache-line-size = <32>;
36			i-cache-line-size = <32>;
37			d-cache-size = <16384>;
38			i-cache-size = <16384>;
39			timebase-frequency = <0>;	// from bootloader
40			bus-frequency = <0>;		// from bootloader
41			clock-frequency = <0>;		// from bootloader
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x08000000>;	// 128MB at 0
48	};
49
50	localbus@e0005000 {
51		#address-cells = <2>;
52		#size-cells = <1>;
53		compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
54		reg = <0xe0005000 0x1000>;
55		interrupts = <77 0x8>;
56		interrupt-parent = <&ipic>;
57
58		// CS0 and CS1 are swapped when
59		// booting from nand, but the
60		// addresses are the same.
61		ranges = <0x0 0x0 0xfe000000 0x00800000
62		          0x1 0x0 0xe2800000 0x00008000
63		          0x2 0x0 0xf0000000 0x00020000
64		          0x3 0x0 0xfa000000 0x00008000>;
65
66		flash@0,0 {
67			#address-cells = <1>;
68			#size-cells = <1>;
69			compatible = "cfi-flash";
70			reg = <0x0 0x0 0x800000>;
71			bank-width = <2>;
72			device-width = <1>;
73		};
74
75		nand@1,0 {
76			#address-cells = <1>;
77			#size-cells = <1>;
78			compatible = "fsl,mpc8313-fcm-nand",
79			             "fsl,elbc-fcm-nand";
80			reg = <0x1 0x0 0x2000>;
81
82			u-boot@0 {
83				reg = <0x0 0x100000>;
84				read-only;
85			};
86
87			kernel@100000 {
88				reg = <0x100000 0x300000>;
89			};
90
91			fs@400000 {
92				reg = <0x400000 0x1c00000>;
93			};
94		};
95	};
96
97	soc8313@e0000000 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		device_type = "soc";
101		compatible = "simple-bus";
102		ranges = <0x0 0xe0000000 0x00100000>;
103		reg = <0xe0000000 0x00000200>;
104		bus-frequency = <0>;
105
106		wdt@200 {
107			device_type = "watchdog";
108			compatible = "mpc83xx_wdt";
109			reg = <0x200 0x100>;
110		};
111
112		i2c@3000 {
113			#address-cells = <1>;
114			#size-cells = <0>;
115			cell-index = <0>;
116			compatible = "fsl-i2c";
117			reg = <0x3000 0x100>;
118			interrupts = <14 0x8>;
119			interrupt-parent = <&ipic>;
120			dfsrr;
121			rtc@68 {
122				compatible = "dallas,ds1339";
123				reg = <0x68>;
124			};
125		};
126
127		i2c@3100 {
128			#address-cells = <1>;
129			#size-cells = <0>;
130			cell-index = <1>;
131			compatible = "fsl-i2c";
132			reg = <0x3100 0x100>;
133			interrupts = <15 0x8>;
134			interrupt-parent = <&ipic>;
135			dfsrr;
136		};
137
138		spi@7000 {
139			cell-index = <0>;
140			compatible = "fsl,spi";
141			reg = <0x7000 0x1000>;
142			interrupts = <16 0x8>;
143			interrupt-parent = <&ipic>;
144			mode = "cpu";
145		};
146
147		dma@82a8 {
148			#address-cells = <1>;
149			#size-cells = <1>;
150			compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
151			reg = <0x82a8 4>;
152			ranges = <0 0x8100 0x1a8>;
153			interrupt-parent = <&ipic>;
154			interrupts = <71 8>;
155			cell-index = <0>;
156			dma-channel@0 {
157				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
158				reg = <0 0x80>;
159				interrupt-parent = <&ipic>;
160				interrupts = <71 8>;
161			};
162			dma-channel@80 {
163				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
164				reg = <0x80 0x80>;
165				interrupt-parent = <&ipic>;
166				interrupts = <71 8>;
167			};
168			dma-channel@100 {
169				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
170				reg = <0x100 0x80>;
171				interrupt-parent = <&ipic>;
172				interrupts = <71 8>;
173			};
174			dma-channel@180 {
175				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
176				reg = <0x180 0x28>;
177				interrupt-parent = <&ipic>;
178				interrupts = <71 8>;
179			};
180		};
181
182		/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
183		usb@23000 {
184			compatible = "fsl-usb2-dr";
185			reg = <0x23000 0x1000>;
186			#address-cells = <1>;
187			#size-cells = <0>;
188			interrupt-parent = <&ipic>;
189			interrupts = <38 0x8>;
190			phy_type = "utmi_wide";
191		};
192
193		mdio@24520 {
194			#address-cells = <1>;
195			#size-cells = <0>;
196			compatible = "fsl,gianfar-mdio";
197			reg = <0x24520 0x20>;
198			phy1: ethernet-phy@1 {
199				interrupt-parent = <&ipic>;
200				interrupts = <19 0x8>;
201				reg = <0x1>;
202				device_type = "ethernet-phy";
203			};
204			phy4: ethernet-phy@4 {
205				interrupt-parent = <&ipic>;
206				interrupts = <20 0x8>;
207				reg = <0x4>;
208				device_type = "ethernet-phy";
209			};
210		};
211
212		enet0: ethernet@24000 {
213			cell-index = <0>;
214			device_type = "network";
215			model = "eTSEC";
216			compatible = "gianfar";
217			reg = <0x24000 0x1000>;
218			local-mac-address = [ 00 00 00 00 00 00 ];
219			interrupts = <37 0x8 36 0x8 35 0x8>;
220			interrupt-parent = <&ipic>;
221			phy-handle = < &phy1 >;
222		};
223
224		enet1: ethernet@25000 {
225			cell-index = <1>;
226			device_type = "network";
227			model = "eTSEC";
228			compatible = "gianfar";
229			reg = <0x25000 0x1000>;
230			local-mac-address = [ 00 00 00 00 00 00 ];
231			interrupts = <34 0x8 33 0x8 32 0x8>;
232			interrupt-parent = <&ipic>;
233			phy-handle = < &phy4 >;
234		};
235
236		serial0: serial@4500 {
237			cell-index = <0>;
238			device_type = "serial";
239			compatible = "ns16550";
240			reg = <0x4500 0x100>;
241			clock-frequency = <0>;
242			interrupts = <9 0x8>;
243			interrupt-parent = <&ipic>;
244		};
245
246		serial1: serial@4600 {
247			cell-index = <1>;
248			device_type = "serial";
249			compatible = "ns16550";
250			reg = <0x4600 0x100>;
251			clock-frequency = <0>;
252			interrupts = <10 0x8>;
253			interrupt-parent = <&ipic>;
254		};
255
256		crypto@30000 {
257			device_type = "crypto";
258			model = "SEC2";
259			compatible = "talitos";
260			reg = <0x30000 0x7000>;
261			interrupts = <11 0x8>;
262			interrupt-parent = <&ipic>;
263			/* Rev. 2.2 */
264			num-channels = <1>;
265			channel-fifo-len = <24>;
266			exec-units-mask = <0x0000004c>;
267			descriptor-types-mask = <0x0122003f>;
268		};
269
270		/* IPIC
271		 * interrupts cell = <intr #, sense>
272		 * sense values match linux IORESOURCE_IRQ_* defines:
273		 * sense == 8: Level, low assertion
274		 * sense == 2: Edge, high-to-low change
275		 */
276		ipic: pic@700 {
277			interrupt-controller;
278			#address-cells = <0>;
279			#interrupt-cells = <2>;
280			reg = <0x700 0x100>;
281			device_type = "ipic";
282		};
283	};
284
285	pci0: pci@e0008500 {
286		cell-index = <1>;
287		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
288		interrupt-map = <
289
290				/* IDSEL 0x0E -mini PCI */
291				 0x7000 0x0 0x0 0x1 &ipic 18 0x8
292				 0x7000 0x0 0x0 0x2 &ipic 18 0x8
293				 0x7000 0x0 0x0 0x3 &ipic 18 0x8
294				 0x7000 0x0 0x0 0x4 &ipic 18 0x8
295
296				/* IDSEL 0x0F - PCI slot */
297				 0x7800 0x0 0x0 0x1 &ipic 17 0x8
298				 0x7800 0x0 0x0 0x2 &ipic 18 0x8
299				 0x7800 0x0 0x0 0x3 &ipic 17 0x8
300				 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
301		interrupt-parent = <&ipic>;
302		interrupts = <66 0x8>;
303		bus-range = <0x0 0x0>;
304		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
305			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
306			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
307		clock-frequency = <66666666>;
308		#interrupt-cells = <1>;
309		#size-cells = <2>;
310		#address-cells = <3>;
311		reg = <0xe0008500 0x100>;
312		compatible = "fsl,mpc8349-pci";
313		device_type = "pci";
314	};
315};
316