1/*
2 * MPC8313E RDB Device Tree Source
3 *
4 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "MPC8313ERDB";
16	compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,8313@0 {
33			device_type = "cpu";
34			reg = <0x0>;
35			d-cache-line-size = <32>;
36			i-cache-line-size = <32>;
37			d-cache-size = <16384>;
38			i-cache-size = <16384>;
39			timebase-frequency = <0>;	// from bootloader
40			bus-frequency = <0>;		// from bootloader
41			clock-frequency = <0>;		// from bootloader
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x08000000>;	// 128MB at 0
48	};
49
50	localbus@e0005000 {
51		#address-cells = <2>;
52		#size-cells = <1>;
53		compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
54		reg = <0xe0005000 0x1000>;
55		interrupts = <77 0x8>;
56		interrupt-parent = <&ipic>;
57
58		// CS0 and CS1 are swapped when
59		// booting from nand, but the
60		// addresses are the same.
61		ranges = <0x0 0x0 0xfe000000 0x00800000
62		          0x1 0x0 0xe2800000 0x00008000
63		          0x2 0x0 0xf0000000 0x00020000
64		          0x3 0x0 0xfa000000 0x00008000>;
65
66		flash@0,0 {
67			#address-cells = <1>;
68			#size-cells = <1>;
69			compatible = "cfi-flash";
70			reg = <0x0 0x0 0x800000>;
71			bank-width = <2>;
72			device-width = <1>;
73		};
74
75		nand@1,0 {
76			#address-cells = <1>;
77			#size-cells = <1>;
78			compatible = "fsl,mpc8313-fcm-nand",
79			             "fsl,elbc-fcm-nand";
80			reg = <0x1 0x0 0x2000>;
81
82			u-boot@0 {
83				reg = <0x0 0x100000>;
84				read-only;
85			};
86
87			kernel@100000 {
88				reg = <0x100000 0x300000>;
89			};
90
91			fs@400000 {
92				reg = <0x400000 0x1c00000>;
93			};
94		};
95	};
96
97	soc8313@e0000000 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		device_type = "soc";
101		compatible = "simple-bus";
102		ranges = <0x0 0xe0000000 0x00100000>;
103		reg = <0xe0000000 0x00000200>;
104		bus-frequency = <0>;
105
106		wdt@200 {
107			device_type = "watchdog";
108			compatible = "mpc83xx_wdt";
109			reg = <0x200 0x100>;
110		};
111
112		sleep-nexus {
113			#address-cells = <1>;
114			#size-cells = <1>;
115			compatible = "simple-bus";
116			sleep = <&pmc 0x03000000>;
117			ranges;
118
119			i2c@3000 {
120				#address-cells = <1>;
121				#size-cells = <0>;
122				cell-index = <0>;
123				compatible = "fsl-i2c";
124				reg = <0x3000 0x100>;
125				interrupts = <14 0x8>;
126				interrupt-parent = <&ipic>;
127				dfsrr;
128				rtc@68 {
129					compatible = "dallas,ds1339";
130					reg = <0x68>;
131				};
132			};
133
134			crypto@30000 {
135				compatible = "fsl,sec2.2", "fsl,sec2.1",
136				             "fsl,sec2.0";
137				reg = <0x30000 0x10000>;
138				interrupts = <11 0x8>;
139				interrupt-parent = <&ipic>;
140				fsl,num-channels = <1>;
141				fsl,channel-fifo-len = <24>;
142				fsl,exec-units-mask = <0x4c>;
143				fsl,descriptor-types-mask = <0x0122003f>;
144			};
145		};
146
147		i2c@3100 {
148			#address-cells = <1>;
149			#size-cells = <0>;
150			cell-index = <1>;
151			compatible = "fsl-i2c";
152			reg = <0x3100 0x100>;
153			interrupts = <15 0x8>;
154			interrupt-parent = <&ipic>;
155			dfsrr;
156		};
157
158		spi@7000 {
159			cell-index = <0>;
160			compatible = "fsl,spi";
161			reg = <0x7000 0x1000>;
162			interrupts = <16 0x8>;
163			interrupt-parent = <&ipic>;
164			mode = "cpu";
165		};
166
167		dma@82a8 {
168			#address-cells = <1>;
169			#size-cells = <1>;
170			compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
171			reg = <0x82a8 4>;
172			ranges = <0 0x8100 0x1a8>;
173			interrupt-parent = <&ipic>;
174			interrupts = <71 8>;
175			cell-index = <0>;
176			dma-channel@0 {
177				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
178				reg = <0 0x80>;
179				cell-index = <0>;
180				interrupt-parent = <&ipic>;
181				interrupts = <71 8>;
182			};
183			dma-channel@80 {
184				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
185				reg = <0x80 0x80>;
186				cell-index = <1>;
187				interrupt-parent = <&ipic>;
188				interrupts = <71 8>;
189			};
190			dma-channel@100 {
191				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
192				reg = <0x100 0x80>;
193				cell-index = <2>;
194				interrupt-parent = <&ipic>;
195				interrupts = <71 8>;
196			};
197			dma-channel@180 {
198				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
199				reg = <0x180 0x28>;
200				cell-index = <3>;
201				interrupt-parent = <&ipic>;
202				interrupts = <71 8>;
203			};
204		};
205
206		/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
207		usb@23000 {
208			compatible = "fsl-usb2-dr";
209			reg = <0x23000 0x1000>;
210			#address-cells = <1>;
211			#size-cells = <0>;
212			interrupt-parent = <&ipic>;
213			interrupts = <38 0x8>;
214			phy_type = "utmi_wide";
215			sleep = <&pmc 0x00300000>;
216		};
217
218		enet0: ethernet@24000 {
219			#address-cells = <1>;
220			#size-cells = <1>;
221			sleep = <&pmc 0x20000000>;
222			ranges;
223
224			cell-index = <0>;
225			device_type = "network";
226			model = "eTSEC";
227			compatible = "gianfar", "simple-bus";
228			reg = <0x24000 0x1000>;
229			local-mac-address = [ 00 00 00 00 00 00 ];
230			interrupts = <37 0x8 36 0x8 35 0x8>;
231			interrupt-parent = <&ipic>;
232			phy-handle = < &phy1 >;
233			fsl,magic-packet;
234
235			mdio@24520 {
236				#address-cells = <1>;
237				#size-cells = <0>;
238				compatible = "fsl,gianfar-mdio";
239				reg = <0x24520 0x20>;
240				phy1: ethernet-phy@1 {
241					interrupt-parent = <&ipic>;
242					interrupts = <19 0x8>;
243					reg = <0x1>;
244					device_type = "ethernet-phy";
245				};
246				phy4: ethernet-phy@4 {
247					interrupt-parent = <&ipic>;
248					interrupts = <20 0x8>;
249					reg = <0x4>;
250					device_type = "ethernet-phy";
251				};
252			};
253		};
254
255		enet1: ethernet@25000 {
256			cell-index = <1>;
257			device_type = "network";
258			model = "eTSEC";
259			compatible = "gianfar";
260			reg = <0x25000 0x1000>;
261			local-mac-address = [ 00 00 00 00 00 00 ];
262			interrupts = <34 0x8 33 0x8 32 0x8>;
263			interrupt-parent = <&ipic>;
264			phy-handle = < &phy4 >;
265			sleep = <&pmc 0x10000000>;
266			fsl,magic-packet;
267		};
268
269		serial0: serial@4500 {
270			cell-index = <0>;
271			device_type = "serial";
272			compatible = "ns16550";
273			reg = <0x4500 0x100>;
274			clock-frequency = <0>;
275			interrupts = <9 0x8>;
276			interrupt-parent = <&ipic>;
277		};
278
279		serial1: serial@4600 {
280			cell-index = <1>;
281			device_type = "serial";
282			compatible = "ns16550";
283			reg = <0x4600 0x100>;
284			clock-frequency = <0>;
285			interrupts = <10 0x8>;
286			interrupt-parent = <&ipic>;
287		};
288
289		/* IPIC
290		 * interrupts cell = <intr #, sense>
291		 * sense values match linux IORESOURCE_IRQ_* defines:
292		 * sense == 8: Level, low assertion
293		 * sense == 2: Edge, high-to-low change
294		 */
295		ipic: pic@700 {
296			interrupt-controller;
297			#address-cells = <0>;
298			#interrupt-cells = <2>;
299			reg = <0x700 0x100>;
300			device_type = "ipic";
301		};
302
303		pmc: power@b00 {
304			compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
305			reg = <0xb00 0x100 0xa00 0x100>;
306			interrupts = <80 8>;
307			interrupt-parent = <&ipic>;
308			fsl,mpc8313-wakeup-timer = <&gtm1>;
309
310			/* Remove this (or change to "okay") if you have
311			 * a REVA3 or later board, if you apply one of the
312			 * workarounds listed in section 8.5 of the board
313			 * manual, or if you are adapting this device tree
314			 * to a different board.
315			 */
316			status = "fail";
317		};
318
319		gtm1: timer@500 {
320			compatible = "fsl,mpc8313-gtm", "fsl,gtm";
321			reg = <0x500 0x100>;
322			interrupts = <90 8 78 8 84 8 72 8>;
323			interrupt-parent = <&ipic>;
324		};
325
326		timer@600 {
327			compatible = "fsl,mpc8313-gtm", "fsl,gtm";
328			reg = <0x600 0x100>;
329			interrupts = <91 8 79 8 85 8 73 8>;
330			interrupt-parent = <&ipic>;
331		};
332	};
333
334	sleep-nexus {
335		#address-cells = <1>;
336		#size-cells = <1>;
337		compatible = "simple-bus";
338		sleep = <&pmc 0x00010000>;
339		ranges;
340
341		pci0: pci@e0008500 {
342			cell-index = <1>;
343			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
344			interrupt-map = <
345					/* IDSEL 0x0E -mini PCI */
346					 0x7000 0x0 0x0 0x1 &ipic 18 0x8
347					 0x7000 0x0 0x0 0x2 &ipic 18 0x8
348					 0x7000 0x0 0x0 0x3 &ipic 18 0x8
349					 0x7000 0x0 0x0 0x4 &ipic 18 0x8
350
351					/* IDSEL 0x0F - PCI slot */
352					 0x7800 0x0 0x0 0x1 &ipic 17 0x8
353					 0x7800 0x0 0x0 0x2 &ipic 18 0x8
354					 0x7800 0x0 0x0 0x3 &ipic 17 0x8
355					 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
356			interrupt-parent = <&ipic>;
357			interrupts = <66 0x8>;
358			bus-range = <0x0 0x0>;
359			ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
360				  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
361				  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
362			clock-frequency = <66666666>;
363			#interrupt-cells = <1>;
364			#size-cells = <2>;
365			#address-cells = <3>;
366			reg = <0xe0008500 0x100		/* internal registers */
367			       0xe0008300 0x8>;		/* config space access registers */
368			compatible = "fsl,mpc8349-pci";
369			device_type = "pci";
370		};
371
372		dma@82a8 {
373			#address-cells = <1>;
374			#size-cells = <1>;
375			compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
376			reg = <0xe00082a8 4>;
377			ranges = <0 0xe0008100 0x1a8>;
378			interrupt-parent = <&ipic>;
379			interrupts = <71 8>;
380
381			dma-channel@0 {
382				compatible = "fsl,mpc8313-dma-channel",
383				             "fsl,elo-dma-channel";
384				reg = <0 0x28>;
385				interrupt-parent = <&ipic>;
386				interrupts = <71 8>;
387				cell-index = <0>;
388			};
389
390			dma-channel@80 {
391				compatible = "fsl,mpc8313-dma-channel",
392				             "fsl,elo-dma-channel";
393				reg = <0x80 0x28>;
394				interrupt-parent = <&ipic>;
395				interrupts = <71 8>;
396				cell-index = <1>;
397			};
398
399			dma-channel@100 {
400				compatible = "fsl,mpc8313-dma-channel",
401				             "fsl,elo-dma-channel";
402				reg = <0x100 0x28>;
403				interrupt-parent = <&ipic>;
404				interrupts = <71 8>;
405				cell-index = <2>;
406			};
407
408			dma-channel@180 {
409				compatible = "fsl,mpc8313-dma-channel",
410				             "fsl,elo-dma-channel";
411				reg = <0x180 0x28>;
412				interrupt-parent = <&ipic>;
413				interrupts = <71 8>;
414				cell-index = <3>;
415			};
416		};
417	};
418};
419