1/*
2 * MPC8313E RDB Device Tree Source
3 *
4 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "MPC8313ERDB";
16	compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,8313@0 {
33			device_type = "cpu";
34			reg = <0x0>;
35			d-cache-line-size = <32>;
36			i-cache-line-size = <32>;
37			d-cache-size = <16384>;
38			i-cache-size = <16384>;
39			timebase-frequency = <0>;	// from bootloader
40			bus-frequency = <0>;		// from bootloader
41			clock-frequency = <0>;		// from bootloader
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x08000000>;	// 128MB at 0
48	};
49
50	localbus@e0005000 {
51		#address-cells = <2>;
52		#size-cells = <1>;
53		compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
54		reg = <0xe0005000 0x1000>;
55		interrupts = <77 0x8>;
56		interrupt-parent = <&ipic>;
57
58		// CS0 and CS1 are swapped when
59		// booting from nand, but the
60		// addresses are the same.
61		ranges = <0x0 0x0 0xfe000000 0x00800000
62		          0x1 0x0 0xe2800000 0x00008000
63		          0x2 0x0 0xf0000000 0x00020000
64		          0x3 0x0 0xfa000000 0x00008000>;
65
66		flash@0,0 {
67			#address-cells = <1>;
68			#size-cells = <1>;
69			compatible = "cfi-flash";
70			reg = <0x0 0x0 0x800000>;
71			bank-width = <2>;
72			device-width = <1>;
73		};
74
75		nand@1,0 {
76			#address-cells = <1>;
77			#size-cells = <1>;
78			compatible = "fsl,mpc8313-fcm-nand",
79			             "fsl,elbc-fcm-nand";
80			reg = <0x1 0x0 0x2000>;
81
82			u-boot@0 {
83				reg = <0x0 0x100000>;
84				read-only;
85			};
86
87			kernel@100000 {
88				reg = <0x100000 0x300000>;
89			};
90
91			fs@400000 {
92				reg = <0x400000 0x1c00000>;
93			};
94		};
95	};
96
97	soc8313@e0000000 {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		device_type = "soc";
101		compatible = "simple-bus";
102		ranges = <0x0 0xe0000000 0x00100000>;
103		reg = <0xe0000000 0x00000200>;
104		bus-frequency = <0>;
105
106		wdt@200 {
107			device_type = "watchdog";
108			compatible = "mpc83xx_wdt";
109			reg = <0x200 0x100>;
110		};
111
112		sleep-nexus {
113			#address-cells = <1>;
114			#size-cells = <1>;
115			compatible = "simple-bus";
116			sleep = <&pmc 0x03000000>;
117			ranges;
118
119			i2c@3000 {
120				#address-cells = <1>;
121				#size-cells = <0>;
122				cell-index = <0>;
123				compatible = "fsl-i2c";
124				reg = <0x3000 0x100>;
125				interrupts = <14 0x8>;
126				interrupt-parent = <&ipic>;
127				dfsrr;
128				rtc@68 {
129					compatible = "dallas,ds1339";
130					reg = <0x68>;
131				};
132			};
133
134			crypto@30000 {
135				compatible = "fsl,sec2.2", "fsl,sec2.1",
136				             "fsl,sec2.0";
137				reg = <0x30000 0x10000>;
138				interrupts = <11 0x8>;
139				interrupt-parent = <&ipic>;
140				fsl,num-channels = <1>;
141				fsl,channel-fifo-len = <24>;
142				fsl,exec-units-mask = <0x4c>;
143				fsl,descriptor-types-mask = <0x0122003f>;
144			};
145		};
146
147		i2c@3100 {
148			#address-cells = <1>;
149			#size-cells = <0>;
150			cell-index = <1>;
151			compatible = "fsl-i2c";
152			reg = <0x3100 0x100>;
153			interrupts = <15 0x8>;
154			interrupt-parent = <&ipic>;
155			dfsrr;
156		};
157
158		spi@7000 {
159			cell-index = <0>;
160			compatible = "fsl,spi";
161			reg = <0x7000 0x1000>;
162			interrupts = <16 0x8>;
163			interrupt-parent = <&ipic>;
164			mode = "cpu";
165		};
166
167		dma@82a8 {
168			#address-cells = <1>;
169			#size-cells = <1>;
170			compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
171			reg = <0x82a8 4>;
172			ranges = <0 0x8100 0x1a8>;
173			interrupt-parent = <&ipic>;
174			interrupts = <71 8>;
175			cell-index = <0>;
176			dma-channel@0 {
177				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
178				reg = <0 0x80>;
179				interrupt-parent = <&ipic>;
180				interrupts = <71 8>;
181			};
182			dma-channel@80 {
183				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
184				reg = <0x80 0x80>;
185				interrupt-parent = <&ipic>;
186				interrupts = <71 8>;
187			};
188			dma-channel@100 {
189				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
190				reg = <0x100 0x80>;
191				interrupt-parent = <&ipic>;
192				interrupts = <71 8>;
193			};
194			dma-channel@180 {
195				compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
196				reg = <0x180 0x28>;
197				interrupt-parent = <&ipic>;
198				interrupts = <71 8>;
199			};
200		};
201
202		/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
203		usb@23000 {
204			compatible = "fsl-usb2-dr";
205			reg = <0x23000 0x1000>;
206			#address-cells = <1>;
207			#size-cells = <0>;
208			interrupt-parent = <&ipic>;
209			interrupts = <38 0x8>;
210			phy_type = "utmi_wide";
211			sleep = <&pmc 0x00300000>;
212		};
213
214		enet0: ethernet@24000 {
215			#address-cells = <1>;
216			#size-cells = <1>;
217			sleep = <&pmc 0x20000000>;
218			ranges;
219
220			cell-index = <0>;
221			device_type = "network";
222			model = "eTSEC";
223			compatible = "gianfar", "simple-bus";
224			reg = <0x24000 0x1000>;
225			local-mac-address = [ 00 00 00 00 00 00 ];
226			interrupts = <37 0x8 36 0x8 35 0x8>;
227			interrupt-parent = <&ipic>;
228			phy-handle = < &phy1 >;
229			fsl,magic-packet;
230
231			mdio@24520 {
232				#address-cells = <1>;
233				#size-cells = <0>;
234				compatible = "fsl,gianfar-mdio";
235				reg = <0x24520 0x20>;
236				phy1: ethernet-phy@1 {
237					interrupt-parent = <&ipic>;
238					interrupts = <19 0x8>;
239					reg = <0x1>;
240					device_type = "ethernet-phy";
241				};
242				phy4: ethernet-phy@4 {
243					interrupt-parent = <&ipic>;
244					interrupts = <20 0x8>;
245					reg = <0x4>;
246					device_type = "ethernet-phy";
247				};
248			};
249		};
250
251		enet1: ethernet@25000 {
252			cell-index = <1>;
253			device_type = "network";
254			model = "eTSEC";
255			compatible = "gianfar";
256			reg = <0x25000 0x1000>;
257			local-mac-address = [ 00 00 00 00 00 00 ];
258			interrupts = <34 0x8 33 0x8 32 0x8>;
259			interrupt-parent = <&ipic>;
260			phy-handle = < &phy4 >;
261			sleep = <&pmc 0x10000000>;
262			fsl,magic-packet;
263		};
264
265		serial0: serial@4500 {
266			cell-index = <0>;
267			device_type = "serial";
268			compatible = "ns16550";
269			reg = <0x4500 0x100>;
270			clock-frequency = <0>;
271			interrupts = <9 0x8>;
272			interrupt-parent = <&ipic>;
273		};
274
275		serial1: serial@4600 {
276			cell-index = <1>;
277			device_type = "serial";
278			compatible = "ns16550";
279			reg = <0x4600 0x100>;
280			clock-frequency = <0>;
281			interrupts = <10 0x8>;
282			interrupt-parent = <&ipic>;
283		};
284
285		/* IPIC
286		 * interrupts cell = <intr #, sense>
287		 * sense values match linux IORESOURCE_IRQ_* defines:
288		 * sense == 8: Level, low assertion
289		 * sense == 2: Edge, high-to-low change
290		 */
291		ipic: pic@700 {
292			interrupt-controller;
293			#address-cells = <0>;
294			#interrupt-cells = <2>;
295			reg = <0x700 0x100>;
296			device_type = "ipic";
297		};
298
299		pmc: power@b00 {
300			compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
301			reg = <0xb00 0x100 0xa00 0x100>;
302			interrupts = <80 8>;
303			interrupt-parent = <&ipic>;
304			fsl,mpc8313-wakeup-timer = <&gtm1>;
305
306			/* Remove this (or change to "okay") if you have
307			 * a REVA3 or later board, if you apply one of the
308			 * workarounds listed in section 8.5 of the board
309			 * manual, or if you are adapting this device tree
310			 * to a different board.
311			 */
312			status = "fail";
313		};
314
315		gtm1: timer@500 {
316			compatible = "fsl,mpc8313-gtm", "fsl,gtm";
317			reg = <0x500 0x100>;
318			interrupts = <90 8 78 8 84 8 72 8>;
319			interrupt-parent = <&ipic>;
320		};
321
322		timer@600 {
323			compatible = "fsl,mpc8313-gtm", "fsl,gtm";
324			reg = <0x600 0x100>;
325			interrupts = <91 8 79 8 85 8 73 8>;
326			interrupt-parent = <&ipic>;
327		};
328	};
329
330	sleep-nexus {
331		#address-cells = <1>;
332		#size-cells = <1>;
333		compatible = "simple-bus";
334		sleep = <&pmc 0x00010000>;
335		ranges;
336
337		pci0: pci@e0008500 {
338			cell-index = <1>;
339			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
340			interrupt-map = <
341					/* IDSEL 0x0E -mini PCI */
342					 0x7000 0x0 0x0 0x1 &ipic 18 0x8
343					 0x7000 0x0 0x0 0x2 &ipic 18 0x8
344					 0x7000 0x0 0x0 0x3 &ipic 18 0x8
345					 0x7000 0x0 0x0 0x4 &ipic 18 0x8
346
347					/* IDSEL 0x0F - PCI slot */
348					 0x7800 0x0 0x0 0x1 &ipic 17 0x8
349					 0x7800 0x0 0x0 0x2 &ipic 18 0x8
350					 0x7800 0x0 0x0 0x3 &ipic 17 0x8
351					 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
352			interrupt-parent = <&ipic>;
353			interrupts = <66 0x8>;
354			bus-range = <0x0 0x0>;
355			ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
356				  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
357				  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
358			clock-frequency = <66666666>;
359			#interrupt-cells = <1>;
360			#size-cells = <2>;
361			#address-cells = <3>;
362			reg = <0xe0008500 0x100>;
363			compatible = "fsl,mpc8349-pci";
364			device_type = "pci";
365		};
366
367		dma@82a8 {
368			#address-cells = <1>;
369			#size-cells = <1>;
370			compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
371			reg = <0xe00082a8 4>;
372			ranges = <0 0xe0008100 0x1a8>;
373			interrupt-parent = <&ipic>;
374			interrupts = <71 8>;
375
376			dma-channel@0 {
377				compatible = "fsl,mpc8313-dma-channel",
378				             "fsl,elo-dma-channel";
379				reg = <0 0x28>;
380				interrupt-parent = <&ipic>;
381				interrupts = <71 8>;
382				cell-index = <0>;
383			};
384
385			dma-channel@80 {
386				compatible = "fsl,mpc8313-dma-channel",
387				             "fsl,elo-dma-channel";
388				reg = <0x80 0x28>;
389				interrupt-parent = <&ipic>;
390				interrupts = <71 8>;
391				cell-index = <1>;
392			};
393
394			dma-channel@100 {
395				compatible = "fsl,mpc8313-dma-channel",
396				             "fsl,elo-dma-channel";
397				reg = <0x100 0x28>;
398				interrupt-parent = <&ipic>;
399				interrupts = <71 8>;
400				cell-index = <2>;
401			};
402
403			dma-channel@180 {
404				compatible = "fsl,mpc8313-dma-channel",
405				             "fsl,elo-dma-channel";
406				reg = <0x180 0x28>;
407				interrupt-parent = <&ipic>;
408				interrupts = <71 8>;
409				cell-index = <3>;
410			};
411		};
412	};
413};
414