1ba4d1275SIlya Yanok/*
2ba4d1275SIlya Yanok * MPC8308RDB Device Tree Source
3ba4d1275SIlya Yanok *
4ba4d1275SIlya Yanok * Copyright 2009 Freescale Semiconductor Inc.
5ba4d1275SIlya Yanok * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
6ba4d1275SIlya Yanok *
7ba4d1275SIlya Yanok * This program is free software; you can redistribute  it and/or modify it
8ba4d1275SIlya Yanok * under  the terms of  the GNU General  Public License as published by the
9ba4d1275SIlya Yanok * Free Software Foundation;  either version 2 of the  License, or (at your
10ba4d1275SIlya Yanok * option) any later version.
11ba4d1275SIlya Yanok */
12ba4d1275SIlya Yanok
13ba4d1275SIlya Yanok/dts-v1/;
14ba4d1275SIlya Yanok
15ba4d1275SIlya Yanok/ {
16ba4d1275SIlya Yanok	compatible = "fsl,mpc8308rdb";
17ba4d1275SIlya Yanok	#address-cells = <1>;
18ba4d1275SIlya Yanok	#size-cells = <1>;
19ba4d1275SIlya Yanok
20ba4d1275SIlya Yanok	aliases {
21ba4d1275SIlya Yanok		ethernet0 = &enet0;
22ba4d1275SIlya Yanok		ethernet1 = &enet1;
23ba4d1275SIlya Yanok		serial0 = &serial0;
24ba4d1275SIlya Yanok		serial1 = &serial1;
25ba4d1275SIlya Yanok		pci0 = &pci0;
26ba4d1275SIlya Yanok	};
27ba4d1275SIlya Yanok
28ba4d1275SIlya Yanok	cpus {
29ba4d1275SIlya Yanok		#address-cells = <1>;
30ba4d1275SIlya Yanok		#size-cells = <0>;
31ba4d1275SIlya Yanok
32ba4d1275SIlya Yanok		PowerPC,8308@0 {
33ba4d1275SIlya Yanok			device_type = "cpu";
34ba4d1275SIlya Yanok			reg = <0x0>;
35ba4d1275SIlya Yanok			d-cache-line-size = <32>;
36ba4d1275SIlya Yanok			i-cache-line-size = <32>;
37ba4d1275SIlya Yanok			d-cache-size = <16384>;
38ba4d1275SIlya Yanok			i-cache-size = <16384>;
39ba4d1275SIlya Yanok			timebase-frequency = <0>;	// from bootloader
40ba4d1275SIlya Yanok			bus-frequency = <0>;		// from bootloader
41ba4d1275SIlya Yanok			clock-frequency = <0>;		// from bootloader
42ba4d1275SIlya Yanok		};
43ba4d1275SIlya Yanok	};
44ba4d1275SIlya Yanok
45ba4d1275SIlya Yanok	memory {
46ba4d1275SIlya Yanok		device_type = "memory";
47ba4d1275SIlya Yanok		reg = <0x00000000 0x08000000>;	// 128MB at 0
48ba4d1275SIlya Yanok	};
49ba4d1275SIlya Yanok
50ba4d1275SIlya Yanok	localbus@e0005000 {
51ba4d1275SIlya Yanok		#address-cells = <2>;
52ba4d1275SIlya Yanok		#size-cells = <1>;
53ba4d1275SIlya Yanok		compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
54ba4d1275SIlya Yanok		reg = <0xe0005000 0x1000>;
55ba4d1275SIlya Yanok		interrupts = <77 0x8>;
56ba4d1275SIlya Yanok		interrupt-parent = <&ipic>;
57ba4d1275SIlya Yanok
58ba4d1275SIlya Yanok		// CS0 and CS1 are swapped when
59ba4d1275SIlya Yanok		// booting from nand, but the
60ba4d1275SIlya Yanok		// addresses are the same.
61ba4d1275SIlya Yanok		ranges = <0x0 0x0 0xfe000000 0x00800000
62ba4d1275SIlya Yanok		          0x1 0x0 0xe0600000 0x00002000
63ba4d1275SIlya Yanok		          0x2 0x0 0xf0000000 0x00020000
64ba4d1275SIlya Yanok		          0x3 0x0 0xfa000000 0x00008000>;
65ba4d1275SIlya Yanok
66ba4d1275SIlya Yanok		flash@0,0 {
67ba4d1275SIlya Yanok			#address-cells = <1>;
68ba4d1275SIlya Yanok			#size-cells = <1>;
69ba4d1275SIlya Yanok			compatible = "cfi-flash";
70ba4d1275SIlya Yanok			reg = <0x0 0x0 0x800000>;
71ba4d1275SIlya Yanok			bank-width = <2>;
72ba4d1275SIlya Yanok			device-width = <1>;
73ba4d1275SIlya Yanok
74ba4d1275SIlya Yanok			u-boot@0 {
75ba4d1275SIlya Yanok				reg = <0x0 0x60000>;
76ba4d1275SIlya Yanok				read-only;
77ba4d1275SIlya Yanok			};
78ba4d1275SIlya Yanok			env@60000 {
79ba4d1275SIlya Yanok				reg = <0x60000 0x10000>;
80ba4d1275SIlya Yanok			};
81ba4d1275SIlya Yanok			env1@70000 {
82ba4d1275SIlya Yanok				reg = <0x70000 0x10000>;
83ba4d1275SIlya Yanok			};
84ba4d1275SIlya Yanok			kernel@80000 {
85ba4d1275SIlya Yanok				reg = <0x80000 0x200000>;
86ba4d1275SIlya Yanok			};
87ba4d1275SIlya Yanok			dtb@280000 {
88ba4d1275SIlya Yanok				reg = <0x280000 0x10000>;
89ba4d1275SIlya Yanok			};
90ba4d1275SIlya Yanok			ramdisk@290000 {
91ba4d1275SIlya Yanok				reg = <0x290000 0x570000>;
92ba4d1275SIlya Yanok			};
93ba4d1275SIlya Yanok		};
94ba4d1275SIlya Yanok
95ba4d1275SIlya Yanok		nand@1,0 {
96ba4d1275SIlya Yanok			#address-cells = <1>;
97ba4d1275SIlya Yanok			#size-cells = <1>;
98ba4d1275SIlya Yanok			compatible = "fsl,mpc8315-fcm-nand",
99ba4d1275SIlya Yanok			             "fsl,elbc-fcm-nand";
100ba4d1275SIlya Yanok			reg = <0x1 0x0 0x2000>;
101ba4d1275SIlya Yanok
102ba4d1275SIlya Yanok			jffs2@0 {
103ba4d1275SIlya Yanok				reg = <0x0 0x2000000>;
104ba4d1275SIlya Yanok			};
105ba4d1275SIlya Yanok		};
106ba4d1275SIlya Yanok	};
107ba4d1275SIlya Yanok
108ba4d1275SIlya Yanok	immr@e0000000 {
109ba4d1275SIlya Yanok		#address-cells = <1>;
110ba4d1275SIlya Yanok		#size-cells = <1>;
111ba4d1275SIlya Yanok		device_type = "soc";
112fd066e85SIlya Yanok		compatible = "fsl,mpc8308-immr", "simple-bus";
113ba4d1275SIlya Yanok		ranges = <0 0xe0000000 0x00100000>;
114ba4d1275SIlya Yanok		reg = <0xe0000000 0x00000200>;
115ba4d1275SIlya Yanok		bus-frequency = <0>;
116ba4d1275SIlya Yanok
117ba4d1275SIlya Yanok		i2c@3000 {
118ba4d1275SIlya Yanok			#address-cells = <1>;
119ba4d1275SIlya Yanok			#size-cells = <0>;
120ba4d1275SIlya Yanok			cell-index = <0>;
121ba4d1275SIlya Yanok			compatible = "fsl-i2c";
122ba4d1275SIlya Yanok			reg = <0x3000 0x100>;
123ba4d1275SIlya Yanok			interrupts = <14 0x8>;
124ba4d1275SIlya Yanok			interrupt-parent = <&ipic>;
125ba4d1275SIlya Yanok			dfsrr;
126ba4d1275SIlya Yanok			rtc@68 {
127ba4d1275SIlya Yanok				compatible = "dallas,ds1339";
128ba4d1275SIlya Yanok				reg = <0x68>;
129ba4d1275SIlya Yanok			};
130ba4d1275SIlya Yanok		};
131ba4d1275SIlya Yanok
132ba4d1275SIlya Yanok		usb@23000 {
133ba4d1275SIlya Yanok			compatible = "fsl-usb2-dr";
134ba4d1275SIlya Yanok			reg = <0x23000 0x1000>;
135ba4d1275SIlya Yanok			#address-cells = <1>;
136ba4d1275SIlya Yanok			#size-cells = <0>;
137ba4d1275SIlya Yanok			interrupt-parent = <&ipic>;
138ba4d1275SIlya Yanok			interrupts = <38 0x8>;
139ba4d1275SIlya Yanok			dr_mode = "peripheral";
140ba4d1275SIlya Yanok			phy_type = "ulpi";
141ba4d1275SIlya Yanok		};
142ba4d1275SIlya Yanok
143ba4d1275SIlya Yanok		enet0: ethernet@24000 {
144ba4d1275SIlya Yanok			#address-cells = <1>;
145ba4d1275SIlya Yanok			#size-cells = <1>;
146ba4d1275SIlya Yanok			ranges = <0x0 0x24000 0x1000>;
147ba4d1275SIlya Yanok
148ba4d1275SIlya Yanok			cell-index = <0>;
149ba4d1275SIlya Yanok			device_type = "network";
150ba4d1275SIlya Yanok			model = "eTSEC";
151ba4d1275SIlya Yanok			compatible = "gianfar";
152ba4d1275SIlya Yanok			reg = <0x24000 0x1000>;
153ba4d1275SIlya Yanok			local-mac-address = [ 00 00 00 00 00 00 ];
154ba4d1275SIlya Yanok			interrupts = <32 0x8 33 0x8 34 0x8>;
155ba4d1275SIlya Yanok			interrupt-parent = <&ipic>;
156ba4d1275SIlya Yanok			tbi-handle = < &tbi0 >;
157ba4d1275SIlya Yanok			phy-handle = < &phy2 >;
158ba4d1275SIlya Yanok			fsl,magic-packet;
159ba4d1275SIlya Yanok
160ba4d1275SIlya Yanok			mdio@520 {
161ba4d1275SIlya Yanok				#address-cells = <1>;
162ba4d1275SIlya Yanok				#size-cells = <0>;
163ba4d1275SIlya Yanok				compatible = "fsl,gianfar-mdio";
164ba4d1275SIlya Yanok				reg = <0x520 0x20>;
165ba4d1275SIlya Yanok				phy2: ethernet-phy@2 {
166ba4d1275SIlya Yanok					interrupt-parent = <&ipic>;
167ba4d1275SIlya Yanok					interrupts = <17 0x8>;
168ba4d1275SIlya Yanok					reg = <0x2>;
169ba4d1275SIlya Yanok					device_type = "ethernet-phy";
170ba4d1275SIlya Yanok				};
171ba4d1275SIlya Yanok				tbi0: tbi-phy@11 {
172ba4d1275SIlya Yanok					reg = <0x11>;
173ba4d1275SIlya Yanok					device_type = "tbi-phy";
174ba4d1275SIlya Yanok				};
175ba4d1275SIlya Yanok			};
176ba4d1275SIlya Yanok		};
177ba4d1275SIlya Yanok
178ba4d1275SIlya Yanok		enet1: ethernet@25000 {
179ba4d1275SIlya Yanok			#address-cells = <1>;
180ba4d1275SIlya Yanok			#size-cells = <1>;
181ba4d1275SIlya Yanok			cell-index = <1>;
182ba4d1275SIlya Yanok			device_type = "network";
183ba4d1275SIlya Yanok			model = "eTSEC";
184ba4d1275SIlya Yanok			compatible = "gianfar";
185ba4d1275SIlya Yanok			reg = <0x25000 0x1000>;
186ba4d1275SIlya Yanok			ranges = <0x0 0x25000 0x1000>;
187ba4d1275SIlya Yanok			local-mac-address = [ 00 00 00 00 00 00 ];
188ba4d1275SIlya Yanok			interrupts = <35 0x8 36 0x8 37 0x8>;
189ba4d1275SIlya Yanok			interrupt-parent = <&ipic>;
190ba4d1275SIlya Yanok			tbi-handle = < &tbi1 >;
191ba4d1275SIlya Yanok			/* Vitesse 7385 isn't on the MDIO bus */
192ba4d1275SIlya Yanok			fixed-link = <1 1 1000 0 0>;
193ba4d1275SIlya Yanok			fsl,magic-packet;
194ba4d1275SIlya Yanok
195ba4d1275SIlya Yanok			mdio@520 {
196ba4d1275SIlya Yanok				#address-cells = <1>;
197ba4d1275SIlya Yanok				#size-cells = <0>;
198ba4d1275SIlya Yanok				compatible = "fsl,gianfar-tbi";
199ba4d1275SIlya Yanok				reg = <0x520 0x20>;
200ba4d1275SIlya Yanok
201ba4d1275SIlya Yanok				tbi1: tbi-phy@11 {
202ba4d1275SIlya Yanok					reg = <0x11>;
203ba4d1275SIlya Yanok					device_type = "tbi-phy";
204ba4d1275SIlya Yanok				};
205ba4d1275SIlya Yanok			};
206ba4d1275SIlya Yanok		};
207ba4d1275SIlya Yanok
208ba4d1275SIlya Yanok		serial0: serial@4500 {
209ba4d1275SIlya Yanok			cell-index = <0>;
210ba4d1275SIlya Yanok			device_type = "serial";
211f706bed1SKumar Gala			compatible = "fsl,ns16550", "ns16550";
212ba4d1275SIlya Yanok			reg = <0x4500 0x100>;
213ba4d1275SIlya Yanok			clock-frequency = <133333333>;
214ba4d1275SIlya Yanok			interrupts = <9 0x8>;
215ba4d1275SIlya Yanok			interrupt-parent = <&ipic>;
216ba4d1275SIlya Yanok		};
217ba4d1275SIlya Yanok
218ba4d1275SIlya Yanok		serial1: serial@4600 {
219ba4d1275SIlya Yanok			cell-index = <1>;
220ba4d1275SIlya Yanok			device_type = "serial";
221f706bed1SKumar Gala			compatible = "fsl,ns16550", "ns16550";
222ba4d1275SIlya Yanok			reg = <0x4600 0x100>;
223ba4d1275SIlya Yanok			clock-frequency = <133333333>;
224ba4d1275SIlya Yanok			interrupts = <10 0x8>;
225ba4d1275SIlya Yanok			interrupt-parent = <&ipic>;
226ba4d1275SIlya Yanok		};
227ba4d1275SIlya Yanok
228ba4d1275SIlya Yanok		gpio@c00 {
229ba4d1275SIlya Yanok			#gpio-cells = <2>;
230ba4d1275SIlya Yanok			device_type = "gpio";
231ba4d1275SIlya Yanok			compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
232ba4d1275SIlya Yanok			reg = <0xc00 0x18>;
233ba4d1275SIlya Yanok			interrupts = <74 0x8>;
234ba4d1275SIlya Yanok			interrupt-parent = <&ipic>;
235ba4d1275SIlya Yanok			gpio-controller;
236ba4d1275SIlya Yanok		};
237ba4d1275SIlya Yanok
238ba4d1275SIlya Yanok		/* IPIC
239ba4d1275SIlya Yanok		 * interrupts cell = <intr #, sense>
240ba4d1275SIlya Yanok		 * sense values match linux IORESOURCE_IRQ_* defines:
241ba4d1275SIlya Yanok		 * sense == 8: Level, low assertion
242ba4d1275SIlya Yanok		 * sense == 2: Edge, high-to-low change
243ba4d1275SIlya Yanok		 */
244ba4d1275SIlya Yanok		ipic: interrupt-controller@700 {
245ba4d1275SIlya Yanok			compatible = "fsl,ipic";
246ba4d1275SIlya Yanok			interrupt-controller;
247ba4d1275SIlya Yanok			#address-cells = <0>;
248ba4d1275SIlya Yanok			#interrupt-cells = <2>;
249ba4d1275SIlya Yanok			reg = <0x700 0x100>;
250ba4d1275SIlya Yanok			device_type = "ipic";
251ba4d1275SIlya Yanok		};
252ba4d1275SIlya Yanok
253ba4d1275SIlya Yanok		ipic-msi@7c0 {
254ba4d1275SIlya Yanok			compatible = "fsl,ipic-msi";
255ba4d1275SIlya Yanok			reg = <0x7c0 0x40>;
256ba4d1275SIlya Yanok			msi-available-ranges = <0x0 0x100>;
257ba4d1275SIlya Yanok			interrupts = < 0x43 0x8
258ba4d1275SIlya Yanok					0x4  0x8
259ba4d1275SIlya Yanok					0x51 0x8
260ba4d1275SIlya Yanok					0x52 0x8
261ba4d1275SIlya Yanok					0x56 0x8
262ba4d1275SIlya Yanok					0x57 0x8
263ba4d1275SIlya Yanok					0x58 0x8
264ba4d1275SIlya Yanok					0x59 0x8 >;
265ba4d1275SIlya Yanok			interrupt-parent = < &ipic >;
266ba4d1275SIlya Yanok		};
267ba4d1275SIlya Yanok
2689d659944SIlya Yanok		dma@2c000 {
2699d659944SIlya Yanok			compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
2709d659944SIlya Yanok			reg = <0x2c000 0x1800>;
2719d659944SIlya Yanok			interrupts = <3 0x8
2729d659944SIlya Yanok					94 0x8>;
2739d659944SIlya Yanok			interrupt-parent = < &ipic >;
2749d659944SIlya Yanok		};
2759d659944SIlya Yanok
276ba4d1275SIlya Yanok	};
277ba4d1275SIlya Yanok
278ba4d1275SIlya Yanok	pci0: pcie@e0009000 {
279ba4d1275SIlya Yanok		#address-cells = <3>;
280ba4d1275SIlya Yanok		#size-cells = <2>;
281ba4d1275SIlya Yanok		#interrupt-cells = <1>;
282ba4d1275SIlya Yanok		device_type = "pci";
283ba4d1275SIlya Yanok		compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
284ba4d1275SIlya Yanok		reg = <0xe0009000 0x00001000
285ba4d1275SIlya Yanok			0xb0000000 0x01000000>;
286ba4d1275SIlya Yanok		ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
287ba4d1275SIlya Yanok		          0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
288ba4d1275SIlya Yanok		bus-range = <0 0>;
289ba4d1275SIlya Yanok		interrupt-map-mask = <0xf800 0 0 7>;
290ba4d1275SIlya Yanok		interrupt-map = <0 0 0 1 &ipic 1 8
291ba4d1275SIlya Yanok				 0 0 0 2 &ipic 1 8
292ba4d1275SIlya Yanok				 0 0 0 3 &ipic 1 8
293ba4d1275SIlya Yanok				 0 0 0 4 &ipic 1 8>;
294ba4d1275SIlya Yanok		interrupts = <0x1 0x8>;
295ba4d1275SIlya Yanok		interrupt-parent = <&ipic>;
296ba4d1275SIlya Yanok		clock-frequency = <0>;
297ba4d1275SIlya Yanok
298ba4d1275SIlya Yanok		pcie@0 {
299ba4d1275SIlya Yanok			#address-cells = <3>;
300ba4d1275SIlya Yanok			#size-cells = <2>;
301ba4d1275SIlya Yanok			device_type = "pci";
302ba4d1275SIlya Yanok			reg = <0 0 0 0 0>;
303ba4d1275SIlya Yanok			ranges = <0x02000000 0 0xa0000000
304ba4d1275SIlya Yanok				  0x02000000 0 0xa0000000
305ba4d1275SIlya Yanok				  0 0x10000000
306ba4d1275SIlya Yanok				  0x01000000 0 0x00000000
307ba4d1275SIlya Yanok				  0x01000000 0 0x00000000
308ba4d1275SIlya Yanok				  0 0x00800000>;
309ba4d1275SIlya Yanok		};
310ba4d1275SIlya Yanok	};
311ba4d1275SIlya Yanok};
312