1cd2bd44eSIlya Yanok/* 2cd2bd44eSIlya Yanok * mpc8308_p1m Device Tree Source 3cd2bd44eSIlya Yanok * 4cd2bd44eSIlya Yanok * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 5cd2bd44eSIlya Yanok * 6cd2bd44eSIlya Yanok * This program is free software; you can redistribute it and/or modify it 7cd2bd44eSIlya Yanok * under the terms of the GNU General Public License as published by the 8cd2bd44eSIlya Yanok * Free Software Foundation; either version 2 of the License, or (at your 9cd2bd44eSIlya Yanok * option) any later version. 10cd2bd44eSIlya Yanok */ 11cd2bd44eSIlya Yanok 12cd2bd44eSIlya Yanok/dts-v1/; 13cd2bd44eSIlya Yanok 14cd2bd44eSIlya Yanok/ { 15cd2bd44eSIlya Yanok compatible = "denx,mpc8308_p1m"; 16cd2bd44eSIlya Yanok #address-cells = <1>; 17cd2bd44eSIlya Yanok #size-cells = <1>; 18cd2bd44eSIlya Yanok 19cd2bd44eSIlya Yanok aliases { 20cd2bd44eSIlya Yanok ethernet0 = &enet0; 21cd2bd44eSIlya Yanok ethernet1 = &enet1; 22cd2bd44eSIlya Yanok serial0 = &serial0; 23cd2bd44eSIlya Yanok serial1 = &serial1; 24cd2bd44eSIlya Yanok pci0 = &pci0; 25cd2bd44eSIlya Yanok }; 26cd2bd44eSIlya Yanok 27cd2bd44eSIlya Yanok cpus { 28cd2bd44eSIlya Yanok #address-cells = <1>; 29cd2bd44eSIlya Yanok #size-cells = <0>; 30cd2bd44eSIlya Yanok 31cd2bd44eSIlya Yanok PowerPC,8308@0 { 32cd2bd44eSIlya Yanok device_type = "cpu"; 33cd2bd44eSIlya Yanok reg = <0x0>; 34cd2bd44eSIlya Yanok d-cache-line-size = <32>; 35cd2bd44eSIlya Yanok i-cache-line-size = <32>; 36cd2bd44eSIlya Yanok d-cache-size = <16384>; 37cd2bd44eSIlya Yanok i-cache-size = <16384>; 38cd2bd44eSIlya Yanok timebase-frequency = <0>; // from bootloader 39cd2bd44eSIlya Yanok bus-frequency = <0>; // from bootloader 40cd2bd44eSIlya Yanok clock-frequency = <0>; // from bootloader 41cd2bd44eSIlya Yanok }; 42cd2bd44eSIlya Yanok }; 43cd2bd44eSIlya Yanok 44cd2bd44eSIlya Yanok memory { 45cd2bd44eSIlya Yanok device_type = "memory"; 46cd2bd44eSIlya Yanok reg = <0x00000000 0x08000000>; // 128MB at 0 47cd2bd44eSIlya Yanok }; 48cd2bd44eSIlya Yanok 49cd2bd44eSIlya Yanok localbus@e0005000 { 50cd2bd44eSIlya Yanok #address-cells = <2>; 51cd2bd44eSIlya Yanok #size-cells = <1>; 52cd2bd44eSIlya Yanok compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 53cd2bd44eSIlya Yanok reg = <0xe0005000 0x1000>; 54cd2bd44eSIlya Yanok interrupts = <77 0x8>; 55cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 56cd2bd44eSIlya Yanok 57cd2bd44eSIlya Yanok ranges = <0x0 0x0 0xfc000000 0x04000000 58cd2bd44eSIlya Yanok 0x1 0x0 0xfbff0000 0x00008000 59cd2bd44eSIlya Yanok 0x2 0x0 0xfbff8000 0x00008000>; 60cd2bd44eSIlya Yanok 61cd2bd44eSIlya Yanok flash@0,0 { 62cd2bd44eSIlya Yanok #address-cells = <1>; 63cd2bd44eSIlya Yanok #size-cells = <1>; 64cd2bd44eSIlya Yanok compatible = "cfi-flash"; 65cd2bd44eSIlya Yanok reg = <0x0 0x0 0x4000000>; 66cd2bd44eSIlya Yanok bank-width = <2>; 67cd2bd44eSIlya Yanok device-width = <1>; 68cd2bd44eSIlya Yanok 69cd2bd44eSIlya Yanok u-boot@0 { 70cd2bd44eSIlya Yanok reg = <0x0 0x60000>; 71cd2bd44eSIlya Yanok read-only; 72cd2bd44eSIlya Yanok }; 73cd2bd44eSIlya Yanok env@60000 { 74cd2bd44eSIlya Yanok reg = <0x60000 0x20000>; 75cd2bd44eSIlya Yanok }; 76cd2bd44eSIlya Yanok env1@80000 { 77cd2bd44eSIlya Yanok reg = <0x80000 0x20000>; 78cd2bd44eSIlya Yanok }; 79cd2bd44eSIlya Yanok kernel@a0000 { 80cd2bd44eSIlya Yanok reg = <0xa0000 0x200000>; 81cd2bd44eSIlya Yanok }; 82cd2bd44eSIlya Yanok dtb@2a0000 { 83cd2bd44eSIlya Yanok reg = <0x2a0000 0x20000>; 84cd2bd44eSIlya Yanok }; 85cd2bd44eSIlya Yanok ramdisk@2c0000 { 86cd2bd44eSIlya Yanok reg = <0x2c0000 0x640000>; 87cd2bd44eSIlya Yanok }; 88cd2bd44eSIlya Yanok user@700000 { 89cd2bd44eSIlya Yanok reg = <0x700000 0x3900000>; 90cd2bd44eSIlya Yanok }; 91cd2bd44eSIlya Yanok }; 92cd2bd44eSIlya Yanok 93cd2bd44eSIlya Yanok can@1,0 { 94cd2bd44eSIlya Yanok compatible = "nxp,sja1000"; 95cd2bd44eSIlya Yanok reg = <0x1 0x0 0x80>; 96cd2bd44eSIlya Yanok interrupts = <18 0x8>; 97cd2bd44eSIlya Yanok interrups-parent = <&ipic>; 98cd2bd44eSIlya Yanok }; 99cd2bd44eSIlya Yanok 100cd2bd44eSIlya Yanok cpld@2,0 { 101cd2bd44eSIlya Yanok compatible = "denx,mpc8308_p1m-cpld"; 102cd2bd44eSIlya Yanok reg = <0x2 0x0 0x8>; 103cd2bd44eSIlya Yanok interrupts = <48 0x8>; 104cd2bd44eSIlya Yanok interrups-parent = <&ipic>; 105cd2bd44eSIlya Yanok }; 106cd2bd44eSIlya Yanok }; 107cd2bd44eSIlya Yanok 108cd2bd44eSIlya Yanok immr@e0000000 { 109cd2bd44eSIlya Yanok #address-cells = <1>; 110cd2bd44eSIlya Yanok #size-cells = <1>; 111cd2bd44eSIlya Yanok device_type = "soc"; 112cd2bd44eSIlya Yanok compatible = "fsl,mpc8308-immr", "simple-bus"; 113cd2bd44eSIlya Yanok ranges = <0 0xe0000000 0x00100000>; 114cd2bd44eSIlya Yanok reg = <0xe0000000 0x00000200>; 115cd2bd44eSIlya Yanok bus-frequency = <0>; 116cd2bd44eSIlya Yanok 117cd2bd44eSIlya Yanok i2c@3000 { 118cd2bd44eSIlya Yanok #address-cells = <1>; 119cd2bd44eSIlya Yanok #size-cells = <0>; 120cd2bd44eSIlya Yanok compatible = "fsl-i2c"; 121cd2bd44eSIlya Yanok reg = <0x3000 0x100>; 122cd2bd44eSIlya Yanok interrupts = <14 0x8>; 123cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 124cd2bd44eSIlya Yanok dfsrr; 125cd2bd44eSIlya Yanok fram@50 { 126cd2bd44eSIlya Yanok compatible = "ramtron,24c64"; 127cd2bd44eSIlya Yanok reg = <0x50>; 128cd2bd44eSIlya Yanok }; 129cd2bd44eSIlya Yanok }; 130cd2bd44eSIlya Yanok 131cd2bd44eSIlya Yanok i2c@3100 { 132cd2bd44eSIlya Yanok #address-cells = <1>; 133cd2bd44eSIlya Yanok #size-cells = <0>; 134cd2bd44eSIlya Yanok compatible = "fsl-i2c"; 135cd2bd44eSIlya Yanok reg = <0x3100 0x100>; 136cd2bd44eSIlya Yanok interrupts = <15 0x8>; 137cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 138cd2bd44eSIlya Yanok dfsrr; 139cd2bd44eSIlya Yanok pwm@28 { 140cd2bd44eSIlya Yanok compatible = "maxim,ds1050"; 141cd2bd44eSIlya Yanok reg = <0x28>; 142cd2bd44eSIlya Yanok }; 143cd2bd44eSIlya Yanok sensor@48 { 144cd2bd44eSIlya Yanok compatible = "maxim,max6625"; 145cd2bd44eSIlya Yanok reg = <0x48>; 146cd2bd44eSIlya Yanok }; 147cd2bd44eSIlya Yanok sensor@49 { 148cd2bd44eSIlya Yanok compatible = "maxim,max6625"; 149cd2bd44eSIlya Yanok reg = <0x49>; 150cd2bd44eSIlya Yanok }; 151cd2bd44eSIlya Yanok sensor@4b { 152cd2bd44eSIlya Yanok compatible = "maxim,max6625"; 153cd2bd44eSIlya Yanok reg = <0x4b>; 154cd2bd44eSIlya Yanok }; 155cd2bd44eSIlya Yanok }; 156cd2bd44eSIlya Yanok 157cd2bd44eSIlya Yanok usb@23000 { 158cd2bd44eSIlya Yanok compatible = "fsl-usb2-dr"; 159cd2bd44eSIlya Yanok reg = <0x23000 0x1000>; 160cd2bd44eSIlya Yanok #address-cells = <1>; 161cd2bd44eSIlya Yanok #size-cells = <0>; 162cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 163cd2bd44eSIlya Yanok interrupts = <38 0x8>; 164cd2bd44eSIlya Yanok dr_mode = "peripheral"; 165cd2bd44eSIlya Yanok phy_type = "ulpi"; 166cd2bd44eSIlya Yanok }; 167cd2bd44eSIlya Yanok 168cd2bd44eSIlya Yanok enet0: ethernet@24000 { 169cd2bd44eSIlya Yanok #address-cells = <1>; 170cd2bd44eSIlya Yanok #size-cells = <1>; 171cd2bd44eSIlya Yanok ranges = <0x0 0x24000 0x1000>; 172cd2bd44eSIlya Yanok 173cd2bd44eSIlya Yanok cell-index = <0>; 174cd2bd44eSIlya Yanok device_type = "network"; 175cd2bd44eSIlya Yanok model = "eTSEC"; 176cd2bd44eSIlya Yanok compatible = "gianfar"; 177cd2bd44eSIlya Yanok reg = <0x24000 0x1000>; 178cd2bd44eSIlya Yanok local-mac-address = [ 00 00 00 00 00 00 ]; 179cd2bd44eSIlya Yanok interrupts = <32 0x8 33 0x8 34 0x8>; 180cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 181cd2bd44eSIlya Yanok phy-handle = < &phy1 >; 182cd2bd44eSIlya Yanok 183cd2bd44eSIlya Yanok mdio@520 { 184cd2bd44eSIlya Yanok #address-cells = <1>; 185cd2bd44eSIlya Yanok #size-cells = <0>; 186cd2bd44eSIlya Yanok compatible = "fsl,gianfar-mdio"; 187cd2bd44eSIlya Yanok reg = <0x520 0x20>; 188cd2bd44eSIlya Yanok phy1: ethernet-phy@1 { 189cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 190cd2bd44eSIlya Yanok interrupts = <17 0x8>; 191cd2bd44eSIlya Yanok reg = <0x1>; 192cd2bd44eSIlya Yanok device_type = "ethernet-phy"; 193cd2bd44eSIlya Yanok }; 194cd2bd44eSIlya Yanok phy2: ethernet-phy@2 { 195cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 196cd2bd44eSIlya Yanok interrupts = <19 0x8>; 197cd2bd44eSIlya Yanok reg = <0x2>; 198cd2bd44eSIlya Yanok device_type = "ethernet-phy"; 199cd2bd44eSIlya Yanok }; 200cd2bd44eSIlya Yanok tbi0: tbi-phy@11 { 201cd2bd44eSIlya Yanok reg = <0x11>; 202cd2bd44eSIlya Yanok device_type = "tbi-phy"; 203cd2bd44eSIlya Yanok }; 204cd2bd44eSIlya Yanok }; 205cd2bd44eSIlya Yanok }; 206cd2bd44eSIlya Yanok 207cd2bd44eSIlya Yanok enet1: ethernet@25000 { 208cd2bd44eSIlya Yanok #address-cells = <1>; 209cd2bd44eSIlya Yanok #size-cells = <1>; 210cd2bd44eSIlya Yanok cell-index = <1>; 211cd2bd44eSIlya Yanok device_type = "network"; 212cd2bd44eSIlya Yanok model = "eTSEC"; 213cd2bd44eSIlya Yanok compatible = "gianfar"; 214cd2bd44eSIlya Yanok reg = <0x25000 0x1000>; 215cd2bd44eSIlya Yanok ranges = <0x0 0x25000 0x1000>; 216cd2bd44eSIlya Yanok local-mac-address = [ 00 00 00 00 00 00 ]; 217cd2bd44eSIlya Yanok interrupts = <35 0x8 36 0x8 37 0x8>; 218cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 219cd2bd44eSIlya Yanok phy-handle = < &phy2 >; 220cd2bd44eSIlya Yanok 221cd2bd44eSIlya Yanok mdio@520 { 222cd2bd44eSIlya Yanok #address-cells = <1>; 223cd2bd44eSIlya Yanok #size-cells = <0>; 224cd2bd44eSIlya Yanok compatible = "fsl,gianfar-tbi"; 225cd2bd44eSIlya Yanok reg = <0x520 0x20>; 226cd2bd44eSIlya Yanok tbi1: tbi-phy@11 { 227cd2bd44eSIlya Yanok reg = <0x11>; 228cd2bd44eSIlya Yanok device_type = "tbi-phy"; 229cd2bd44eSIlya Yanok }; 230cd2bd44eSIlya Yanok }; 231cd2bd44eSIlya Yanok }; 232cd2bd44eSIlya Yanok 233cd2bd44eSIlya Yanok serial0: serial@4500 { 234cd2bd44eSIlya Yanok cell-index = <0>; 235cd2bd44eSIlya Yanok device_type = "serial"; 236f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 237cd2bd44eSIlya Yanok reg = <0x4500 0x100>; 238cd2bd44eSIlya Yanok clock-frequency = <133333333>; 239cd2bd44eSIlya Yanok interrupts = <9 0x8>; 240cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 241cd2bd44eSIlya Yanok }; 242cd2bd44eSIlya Yanok 243cd2bd44eSIlya Yanok serial1: serial@4600 { 244cd2bd44eSIlya Yanok cell-index = <1>; 245cd2bd44eSIlya Yanok device_type = "serial"; 246f706bed1SKumar Gala compatible = "fsl,ns16550", "ns16550"; 247cd2bd44eSIlya Yanok reg = <0x4600 0x100>; 248cd2bd44eSIlya Yanok clock-frequency = <133333333>; 249cd2bd44eSIlya Yanok interrupts = <10 0x8>; 250cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 251cd2bd44eSIlya Yanok }; 252cd2bd44eSIlya Yanok 253cd2bd44eSIlya Yanok gpio@c00 { 254cd2bd44eSIlya Yanok #gpio-cells = <2>; 255cd2bd44eSIlya Yanok compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio"; 256cd2bd44eSIlya Yanok reg = <0xc00 0x18>; 257cd2bd44eSIlya Yanok interrupts = <74 0x8>; 258cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 259cd2bd44eSIlya Yanok gpio-controller; 260cd2bd44eSIlya Yanok }; 261cd2bd44eSIlya Yanok 262cd2bd44eSIlya Yanok timer@500 { 263cd2bd44eSIlya Yanok compatible = "fsl,mpc8308-gtm", "fsl,gtm"; 264cd2bd44eSIlya Yanok reg = <0x500 0x100>; 265cd2bd44eSIlya Yanok interrupts = <90 8 78 8 84 8 72 8>; 266cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 267cd2bd44eSIlya Yanok clock-frequency = <133333333>; 268cd2bd44eSIlya Yanok }; 269cd2bd44eSIlya Yanok 270cd2bd44eSIlya Yanok /* IPIC 271cd2bd44eSIlya Yanok * interrupts cell = <intr #, sense> 272cd2bd44eSIlya Yanok * sense values match linux IORESOURCE_IRQ_* defines: 273cd2bd44eSIlya Yanok * sense == 8: Level, low assertion 274cd2bd44eSIlya Yanok * sense == 2: Edge, high-to-low change 275cd2bd44eSIlya Yanok */ 276cd2bd44eSIlya Yanok ipic: interrupt-controller@700 { 277cd2bd44eSIlya Yanok compatible = "fsl,ipic"; 278cd2bd44eSIlya Yanok interrupt-controller; 279cd2bd44eSIlya Yanok #address-cells = <0>; 280cd2bd44eSIlya Yanok #interrupt-cells = <2>; 281cd2bd44eSIlya Yanok reg = <0x700 0x100>; 282cd2bd44eSIlya Yanok device_type = "ipic"; 283cd2bd44eSIlya Yanok }; 284cd2bd44eSIlya Yanok 285cd2bd44eSIlya Yanok ipic-msi@7c0 { 286cd2bd44eSIlya Yanok compatible = "fsl,ipic-msi"; 287cd2bd44eSIlya Yanok reg = <0x7c0 0x40>; 288cd2bd44eSIlya Yanok msi-available-ranges = <0x0 0x100>; 289cd2bd44eSIlya Yanok interrupts = < 0x43 0x8 290cd2bd44eSIlya Yanok 0x4 0x8 291cd2bd44eSIlya Yanok 0x51 0x8 292cd2bd44eSIlya Yanok 0x52 0x8 293cd2bd44eSIlya Yanok 0x56 0x8 294cd2bd44eSIlya Yanok 0x57 0x8 295cd2bd44eSIlya Yanok 0x58 0x8 296cd2bd44eSIlya Yanok 0x59 0x8 >; 297cd2bd44eSIlya Yanok interrupt-parent = < &ipic >; 298cd2bd44eSIlya Yanok }; 299cd2bd44eSIlya Yanok 300c9de9333SIlya Yanok dma@2c000 { 301c9de9333SIlya Yanok compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma"; 302c9de9333SIlya Yanok reg = <0x2c000 0x1800>; 303c9de9333SIlya Yanok interrupts = <3 0x8 304c9de9333SIlya Yanok 94 0x8>; 305c9de9333SIlya Yanok interrupt-parent = < &ipic >; 306c9de9333SIlya Yanok }; 307c9de9333SIlya Yanok 308cd2bd44eSIlya Yanok }; 309cd2bd44eSIlya Yanok 310cd2bd44eSIlya Yanok pci0: pcie@e0009000 { 311cd2bd44eSIlya Yanok #address-cells = <3>; 312cd2bd44eSIlya Yanok #size-cells = <2>; 313cd2bd44eSIlya Yanok #interrupt-cells = <1>; 314cd2bd44eSIlya Yanok device_type = "pci"; 315cd2bd44eSIlya Yanok compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie"; 316cd2bd44eSIlya Yanok reg = <0xe0009000 0x00001000 317cd2bd44eSIlya Yanok 0xb0000000 0x01000000>; 318cd2bd44eSIlya Yanok ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 319cd2bd44eSIlya Yanok 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; 320cd2bd44eSIlya Yanok bus-range = <0 0>; 321cd2bd44eSIlya Yanok interrupt-map-mask = <0 0 0 0>; 322cd2bd44eSIlya Yanok interrupt-map = <0 0 0 0 &ipic 1 8>; 323cd2bd44eSIlya Yanok interrupts = <0x1 0x8>; 324cd2bd44eSIlya Yanok interrupt-parent = <&ipic>; 325cd2bd44eSIlya Yanok clock-frequency = <0>; 326cd2bd44eSIlya Yanok 327cd2bd44eSIlya Yanok pcie@0 { 328cd2bd44eSIlya Yanok #address-cells = <3>; 329cd2bd44eSIlya Yanok #size-cells = <2>; 330cd2bd44eSIlya Yanok device_type = "pci"; 331cd2bd44eSIlya Yanok reg = <0 0 0 0 0>; 332cd2bd44eSIlya Yanok ranges = <0x02000000 0 0xa0000000 333cd2bd44eSIlya Yanok 0x02000000 0 0xa0000000 334cd2bd44eSIlya Yanok 0 0x10000000 335cd2bd44eSIlya Yanok 0x01000000 0 0x00000000 336cd2bd44eSIlya Yanok 0x01000000 0 0x00000000 337cd2bd44eSIlya Yanok 0 0x00800000>; 338cd2bd44eSIlya Yanok }; 339cd2bd44eSIlya Yanok }; 340cd2bd44eSIlya Yanok}; 341