1/*
2 * STx/Freescale ADS5125 MPC5125 silicon
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
5 *
6 * Reworked by Matteo Facchinetti (engineering@sirius-es.it)
7 * Copyright (C) 2013 Sirius Electronic Systems
8 *
9 * This program is free software; you can redistribute  it and/or modify it
10 * under  the terms of  the GNU General  Public License as published by the
11 * Free Software Foundation;  either version 2 of the  License, or (at your
12 * option) any later version.
13 */
14
15/dts-v1/;
16
17/ {
18	model = "mpc5125twr"; // In BSP "mpc5125ads"
19	compatible = "fsl,mpc5125ads", "fsl,mpc5125";
20	#address-cells = <1>;
21	#size-cells = <1>;
22	interrupt-parent = <&ipic>;
23
24	aliases {
25		gpio0 = &gpio0;
26		gpio1 = &gpio1;
27		ethernet0 = &eth0;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		PowerPC,5125@0 {
35			device_type = "cpu";
36			reg = <0>;
37			d-cache-line-size = <0x20>;	// 32 bytes
38			i-cache-line-size = <0x20>;	// 32 bytes
39			d-cache-size = <0x8000>;	// L1, 32K
40			i-cache-size = <0x8000>;	// L1, 32K
41			timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
42			bus-frequency = <198000000>;	// 198 MHz csb bus
43			clock-frequency = <396000000>;	// 396 MHz ppc core
44		};
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x00000000 0x10000000>;	// 256MB at 0
50	};
51
52	sram@30000000 {
53		compatible = "fsl,mpc5121-sram";
54		reg = <0x30000000 0x08000>;		// 32K at 0x30000000
55	};
56
57	soc@80000000 {
58		compatible = "fsl,mpc5121-immr";
59		#address-cells = <1>;
60		#size-cells = <1>;
61		ranges = <0x0 0x80000000 0x400000>;
62		reg = <0x80000000 0x400000>;
63		bus-frequency = <66000000>;	// 66 MHz ips bus
64
65		// IPIC
66		// interrupts cell = <intr #, sense>
67		// sense values match linux IORESOURCE_IRQ_* defines:
68		// sense == 8: Level, low assertion
69		// sense == 2: Edge, high-to-low change
70		//
71		ipic: interrupt-controller@c00 {
72			compatible = "fsl,mpc5121-ipic", "fsl,ipic";
73			interrupt-controller;
74			#address-cells = <0>;
75			#interrupt-cells = <2>;
76			reg = <0xc00 0x100>;
77		};
78
79		rtc@a00 {	// Real time clock
80			compatible = "fsl,mpc5121-rtc";
81			reg = <0xa00 0x100>;
82			interrupts = <79 0x8 80 0x8>;
83		};
84
85		reset@e00 {	// Reset module
86			compatible = "fsl,mpc5125-reset";
87			reg = <0xe00 0x100>;
88		};
89
90		clock@f00 {	// Clock control
91			compatible = "fsl,mpc5121-clock";
92			reg = <0xf00 0x100>;
93		};
94
95		pmc@1000{  // Power Management Controller
96			compatible = "fsl,mpc5121-pmc";
97			reg = <0x1000 0x100>;
98			interrupts = <83 0x2>;
99		};
100
101		gpio0: gpio@1100 {
102			compatible = "fsl,mpc5125-gpio";
103			reg = <0x1100 0x080>;
104			interrupts = <78 0x8>;
105		};
106
107		gpio1: gpio@1180 {
108			compatible = "fsl,mpc5125-gpio";
109			reg = <0x1180 0x080>;
110			interrupts = <86 0x8>;
111		};
112
113		can@1300 { // CAN rev.2
114			compatible = "fsl,mpc5121-mscan";
115			interrupts = <12 0x8>;
116			reg = <0x1300 0x80>;
117		};
118
119		can@1380 {
120			compatible = "fsl,mpc5121-mscan";
121			interrupts = <13 0x8>;
122			reg = <0x1380 0x80>;
123		};
124
125		sdhc@1500 {
126			compatible = "fsl,mpc5121-sdhc";
127			interrupts = <8 0x8>;
128			reg = <0x1500 0x100>;
129		};
130
131		i2c@1700 {
132			#address-cells = <1>;
133			#size-cells = <0>;
134			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
135			reg = <0x1700 0x20>;
136			interrupts = <0x9 0x8>;
137		};
138
139		i2c@1720 {
140			#address-cells = <1>;
141			#size-cells = <0>;
142			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
143			reg = <0x1720 0x20>;
144			interrupts = <0xa 0x8>;
145		};
146
147		i2c@1740 {
148			#address-cells = <1>;
149			#size-cells = <0>;
150			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
151			reg = <0x1740 0x20>;
152			interrupts = <0xb 0x8>;
153		};
154
155		i2ccontrol@1760 {
156			compatible = "fsl,mpc5121-i2c-ctrl";
157			reg = <0x1760 0x8>;
158		};
159
160		diu@2100 {
161			compatible = "fsl,mpc5121-diu";
162			reg = <0x2100 0x100>;
163			interrupts = <64 0x8>;
164		};
165
166		mdio@2800 {
167			compatible = "fsl,mpc5121-fec-mdio";
168			reg = <0x2800 0x800>;
169			#address-cells = <1>;
170			#size-cells = <0>;
171			phy0: ethernet-phy@0 {
172				reg = <1>;
173			};
174		};
175
176		eth0: ethernet@2800 {
177			compatible = "fsl,mpc5125-fec";
178			reg = <0x2800 0x800>;
179			local-mac-address = [ 00 00 00 00 00 00 ];
180			interrupts = <4 0x8>;
181			phy-handle = < &phy0 >;
182			phy-connection-type = "rmii";
183		};
184
185		// IO control
186		ioctl@a000 {
187			compatible = "fsl,mpc5125-ioctl";
188			reg = <0xA000 0x1000>;
189		};
190
191		usb@3000 {
192			compatible = "fsl,mpc5121-usb2-dr";
193			reg = <0x3000 0x400>;
194			#address-cells = <1>;
195			#size-cells = <0>;
196			interrupts = <43 0x8>;
197			dr_mode = "host";
198			phy_type = "ulpi";
199		};
200
201		// 5125 PSCs are not 52xx or 5121 PSC compatible
202		// PSC1 uart0 aka ttyPSC0
203		serial@11100 {
204			compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
205			reg = <0x11100 0x100>;
206			interrupts = <40 0x8>;
207			fsl,rx-fifo-size = <16>;
208			fsl,tx-fifo-size = <16>;
209		};
210
211		// PSC9 uart1 aka ttyPSC1
212		serial@11900 {
213			compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
214			reg = <0x11900 0x100>;
215			interrupts = <40 0x8>;
216			fsl,rx-fifo-size = <16>;
217			fsl,tx-fifo-size = <16>;
218		};
219
220		pscfifo@11f00 {
221			compatible = "fsl,mpc5121-psc-fifo";
222			reg = <0x11f00 0x100>;
223			interrupts = <40 0x8>;
224		};
225
226		dma@14000 {
227			compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
228			reg = <0x14000 0x1800>;
229			interrupts = <65 0x8>;
230		};
231	};
232};
233