1a9b6aae4SMatteo Facchinetti/* 2a9b6aae4SMatteo Facchinetti * STx/Freescale ADS5125 MPC5125 silicon 3a9b6aae4SMatteo Facchinetti * 4a9b6aae4SMatteo Facchinetti * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved. 5a9b6aae4SMatteo Facchinetti * 6a9b6aae4SMatteo Facchinetti * Reworked by Matteo Facchinetti (engineering@sirius-es.it) 7a9b6aae4SMatteo Facchinetti * Copyright (C) 2013 Sirius Electronic Systems 8a9b6aae4SMatteo Facchinetti * 9a9b6aae4SMatteo Facchinetti * This program is free software; you can redistribute it and/or modify it 10a9b6aae4SMatteo Facchinetti * under the terms of the GNU General Public License as published by the 11a9b6aae4SMatteo Facchinetti * Free Software Foundation; either version 2 of the License, or (at your 12a9b6aae4SMatteo Facchinetti * option) any later version. 13a9b6aae4SMatteo Facchinetti */ 14a9b6aae4SMatteo Facchinetti 15bc750594SGerhard Sittig#include <dt-bindings/clock/mpc512x-clock.h> 16bc750594SGerhard Sittig 17a9b6aae4SMatteo Facchinetti/dts-v1/; 18a9b6aae4SMatteo Facchinetti 19a9b6aae4SMatteo Facchinetti/ { 20a9b6aae4SMatteo Facchinetti model = "mpc5125twr"; // In BSP "mpc5125ads" 21a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125ads", "fsl,mpc5125"; 22a9b6aae4SMatteo Facchinetti #address-cells = <1>; 23a9b6aae4SMatteo Facchinetti #size-cells = <1>; 24a9b6aae4SMatteo Facchinetti interrupt-parent = <&ipic>; 25a9b6aae4SMatteo Facchinetti 26a9b6aae4SMatteo Facchinetti aliases { 27a9b6aae4SMatteo Facchinetti gpio0 = &gpio0; 28a9b6aae4SMatteo Facchinetti gpio1 = &gpio1; 29a9b6aae4SMatteo Facchinetti ethernet0 = ð0; 30a9b6aae4SMatteo Facchinetti }; 31a9b6aae4SMatteo Facchinetti 32a9b6aae4SMatteo Facchinetti cpus { 33a9b6aae4SMatteo Facchinetti #address-cells = <1>; 34a9b6aae4SMatteo Facchinetti #size-cells = <0>; 35a9b6aae4SMatteo Facchinetti 36a9b6aae4SMatteo Facchinetti PowerPC,5125@0 { 37a9b6aae4SMatteo Facchinetti device_type = "cpu"; 38a9b6aae4SMatteo Facchinetti reg = <0>; 39a9b6aae4SMatteo Facchinetti d-cache-line-size = <0x20>; // 32 bytes 40a9b6aae4SMatteo Facchinetti i-cache-line-size = <0x20>; // 32 bytes 41a9b6aae4SMatteo Facchinetti d-cache-size = <0x8000>; // L1, 32K 42a9b6aae4SMatteo Facchinetti i-cache-size = <0x8000>; // L1, 32K 43a9b6aae4SMatteo Facchinetti timebase-frequency = <49500000>;// 49.5 MHz (csb/4) 44a9b6aae4SMatteo Facchinetti bus-frequency = <198000000>; // 198 MHz csb bus 45a9b6aae4SMatteo Facchinetti clock-frequency = <396000000>; // 396 MHz ppc core 46a9b6aae4SMatteo Facchinetti }; 47a9b6aae4SMatteo Facchinetti }; 48a9b6aae4SMatteo Facchinetti 49a9b6aae4SMatteo Facchinetti memory { 50a9b6aae4SMatteo Facchinetti device_type = "memory"; 51a9b6aae4SMatteo Facchinetti reg = <0x00000000 0x10000000>; // 256MB at 0 52a9b6aae4SMatteo Facchinetti }; 53a9b6aae4SMatteo Facchinetti 54a9b6aae4SMatteo Facchinetti sram@30000000 { 55a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-sram"; 56a9b6aae4SMatteo Facchinetti reg = <0x30000000 0x08000>; // 32K at 0x30000000 57a9b6aae4SMatteo Facchinetti }; 58a9b6aae4SMatteo Facchinetti 59bc750594SGerhard Sittig clocks { 60bc750594SGerhard Sittig #address-cells = <1>; 61bc750594SGerhard Sittig #size-cells = <0>; 62bc750594SGerhard Sittig 63bc750594SGerhard Sittig osc: osc { 64bc750594SGerhard Sittig compatible = "fixed-clock"; 65bc750594SGerhard Sittig #clock-cells = <0>; 66bc750594SGerhard Sittig clock-frequency = <33000000>; 67bc750594SGerhard Sittig }; 68bc750594SGerhard Sittig }; 69bc750594SGerhard Sittig 70a9b6aae4SMatteo Facchinetti soc@80000000 { 71a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-immr"; 72a9b6aae4SMatteo Facchinetti #address-cells = <1>; 73a9b6aae4SMatteo Facchinetti #size-cells = <1>; 74a9b6aae4SMatteo Facchinetti ranges = <0x0 0x80000000 0x400000>; 75a9b6aae4SMatteo Facchinetti reg = <0x80000000 0x400000>; 76a9b6aae4SMatteo Facchinetti bus-frequency = <66000000>; // 66 MHz ips bus 77a9b6aae4SMatteo Facchinetti 78a9b6aae4SMatteo Facchinetti // IPIC 79a9b6aae4SMatteo Facchinetti // interrupts cell = <intr #, sense> 80a9b6aae4SMatteo Facchinetti // sense values match linux IORESOURCE_IRQ_* defines: 81a9b6aae4SMatteo Facchinetti // sense == 8: Level, low assertion 82a9b6aae4SMatteo Facchinetti // sense == 2: Edge, high-to-low change 83a9b6aae4SMatteo Facchinetti // 84a9b6aae4SMatteo Facchinetti ipic: interrupt-controller@c00 { 85a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-ipic", "fsl,ipic"; 86a9b6aae4SMatteo Facchinetti interrupt-controller; 87a9b6aae4SMatteo Facchinetti #address-cells = <0>; 88a9b6aae4SMatteo Facchinetti #interrupt-cells = <2>; 89a9b6aae4SMatteo Facchinetti reg = <0xc00 0x100>; 90a9b6aae4SMatteo Facchinetti }; 91a9b6aae4SMatteo Facchinetti 92a9b6aae4SMatteo Facchinetti rtc@a00 { // Real time clock 93a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-rtc"; 94a9b6aae4SMatteo Facchinetti reg = <0xa00 0x100>; 95a9b6aae4SMatteo Facchinetti interrupts = <79 0x8 80 0x8>; 96a9b6aae4SMatteo Facchinetti }; 97a9b6aae4SMatteo Facchinetti 98a9b6aae4SMatteo Facchinetti reset@e00 { // Reset module 99a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-reset"; 100a9b6aae4SMatteo Facchinetti reg = <0xe00 0x100>; 101a9b6aae4SMatteo Facchinetti }; 102a9b6aae4SMatteo Facchinetti 103bc750594SGerhard Sittig clks: clock@f00 { // Clock control 104a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-clock"; 105a9b6aae4SMatteo Facchinetti reg = <0xf00 0x100>; 106bc750594SGerhard Sittig #clock-cells = <1>; 107bc750594SGerhard Sittig clocks = <&osc>; 108bc750594SGerhard Sittig clock-names = "osc"; 109a9b6aae4SMatteo Facchinetti }; 110a9b6aae4SMatteo Facchinetti 111a9b6aae4SMatteo Facchinetti pmc@1000{ // Power Management Controller 112a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-pmc"; 113a9b6aae4SMatteo Facchinetti reg = <0x1000 0x100>; 114a9b6aae4SMatteo Facchinetti interrupts = <83 0x2>; 115a9b6aae4SMatteo Facchinetti }; 116a9b6aae4SMatteo Facchinetti 117a9b6aae4SMatteo Facchinetti gpio0: gpio@1100 { 118a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-gpio"; 119a9b6aae4SMatteo Facchinetti reg = <0x1100 0x080>; 120a9b6aae4SMatteo Facchinetti interrupts = <78 0x8>; 121a9b6aae4SMatteo Facchinetti }; 122a9b6aae4SMatteo Facchinetti 123a9b6aae4SMatteo Facchinetti gpio1: gpio@1180 { 124a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-gpio"; 125a9b6aae4SMatteo Facchinetti reg = <0x1180 0x080>; 126a9b6aae4SMatteo Facchinetti interrupts = <86 0x8>; 127a9b6aae4SMatteo Facchinetti }; 128a9b6aae4SMatteo Facchinetti 129a9b6aae4SMatteo Facchinetti can@1300 { // CAN rev.2 130a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-mscan"; 131a9b6aae4SMatteo Facchinetti interrupts = <12 0x8>; 132a9b6aae4SMatteo Facchinetti reg = <0x1300 0x80>; 133bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_BDLC>, 134bc750594SGerhard Sittig <&clks MPC512x_CLK_IPS>, 135bc750594SGerhard Sittig <&clks MPC512x_CLK_SYS>, 136bc750594SGerhard Sittig <&clks MPC512x_CLK_REF>, 137bc750594SGerhard Sittig <&clks MPC512x_CLK_MSCAN0_MCLK>; 138bc750594SGerhard Sittig clock-names = "ipg", "ips", "sys", "ref", "mclk"; 139a9b6aae4SMatteo Facchinetti }; 140a9b6aae4SMatteo Facchinetti 141a9b6aae4SMatteo Facchinetti can@1380 { 142a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-mscan"; 143a9b6aae4SMatteo Facchinetti interrupts = <13 0x8>; 144a9b6aae4SMatteo Facchinetti reg = <0x1380 0x80>; 145bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_BDLC>, 146bc750594SGerhard Sittig <&clks MPC512x_CLK_IPS>, 147bc750594SGerhard Sittig <&clks MPC512x_CLK_SYS>, 148bc750594SGerhard Sittig <&clks MPC512x_CLK_REF>, 149bc750594SGerhard Sittig <&clks MPC512x_CLK_MSCAN1_MCLK>; 150bc750594SGerhard Sittig clock-names = "ipg", "ips", "sys", "ref", "mclk"; 151a9b6aae4SMatteo Facchinetti }; 152a9b6aae4SMatteo Facchinetti 153a9b6aae4SMatteo Facchinetti sdhc@1500 { 154a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-sdhc"; 155a9b6aae4SMatteo Facchinetti interrupts = <8 0x8>; 156a9b6aae4SMatteo Facchinetti reg = <0x1500 0x100>; 157bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_IPS>, 158bc750594SGerhard Sittig <&clks MPC512x_CLK_SDHC>; 159bc750594SGerhard Sittig clock-names = "ipg", "per"; 160a9b6aae4SMatteo Facchinetti }; 161a9b6aae4SMatteo Facchinetti 162a9b6aae4SMatteo Facchinetti i2c@1700 { 163a9b6aae4SMatteo Facchinetti #address-cells = <1>; 164a9b6aae4SMatteo Facchinetti #size-cells = <0>; 165a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 166a9b6aae4SMatteo Facchinetti reg = <0x1700 0x20>; 167a9b6aae4SMatteo Facchinetti interrupts = <0x9 0x8>; 168bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_I2C>; 169bc750594SGerhard Sittig clock-names = "ipg"; 170a9b6aae4SMatteo Facchinetti }; 171a9b6aae4SMatteo Facchinetti 172a9b6aae4SMatteo Facchinetti i2c@1720 { 173a9b6aae4SMatteo Facchinetti #address-cells = <1>; 174a9b6aae4SMatteo Facchinetti #size-cells = <0>; 175a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 176a9b6aae4SMatteo Facchinetti reg = <0x1720 0x20>; 177a9b6aae4SMatteo Facchinetti interrupts = <0xa 0x8>; 178bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_I2C>; 179bc750594SGerhard Sittig clock-names = "ipg"; 180a9b6aae4SMatteo Facchinetti }; 181a9b6aae4SMatteo Facchinetti 182a9b6aae4SMatteo Facchinetti i2c@1740 { 183a9b6aae4SMatteo Facchinetti #address-cells = <1>; 184a9b6aae4SMatteo Facchinetti #size-cells = <0>; 185a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 186a9b6aae4SMatteo Facchinetti reg = <0x1740 0x20>; 187a9b6aae4SMatteo Facchinetti interrupts = <0xb 0x8>; 188bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_I2C>; 189bc750594SGerhard Sittig clock-names = "ipg"; 190a9b6aae4SMatteo Facchinetti }; 191a9b6aae4SMatteo Facchinetti 192a9b6aae4SMatteo Facchinetti i2ccontrol@1760 { 193a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-i2c-ctrl"; 194a9b6aae4SMatteo Facchinetti reg = <0x1760 0x8>; 195a9b6aae4SMatteo Facchinetti }; 196a9b6aae4SMatteo Facchinetti 197a9b6aae4SMatteo Facchinetti diu@2100 { 198a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-diu"; 199a9b6aae4SMatteo Facchinetti reg = <0x2100 0x100>; 200a9b6aae4SMatteo Facchinetti interrupts = <64 0x8>; 201bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_DIU>; 202bc750594SGerhard Sittig clock-names = "ipg"; 203a9b6aae4SMatteo Facchinetti }; 204a9b6aae4SMatteo Facchinetti 205a9b6aae4SMatteo Facchinetti mdio@2800 { 206a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-fec-mdio"; 207a9b6aae4SMatteo Facchinetti reg = <0x2800 0x800>; 208a9b6aae4SMatteo Facchinetti #address-cells = <1>; 209a9b6aae4SMatteo Facchinetti #size-cells = <0>; 210a9b6aae4SMatteo Facchinetti phy0: ethernet-phy@0 { 211a9b6aae4SMatteo Facchinetti reg = <1>; 212a9b6aae4SMatteo Facchinetti }; 213a9b6aae4SMatteo Facchinetti }; 214a9b6aae4SMatteo Facchinetti 215a9b6aae4SMatteo Facchinetti eth0: ethernet@2800 { 216a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-fec"; 217a9b6aae4SMatteo Facchinetti reg = <0x2800 0x800>; 218a9b6aae4SMatteo Facchinetti local-mac-address = [ 00 00 00 00 00 00 ]; 219a9b6aae4SMatteo Facchinetti interrupts = <4 0x8>; 220a9b6aae4SMatteo Facchinetti phy-handle = < &phy0 >; 221a9b6aae4SMatteo Facchinetti phy-connection-type = "rmii"; 222bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_FEC>; 223bc750594SGerhard Sittig clock-names = "per"; 224a9b6aae4SMatteo Facchinetti }; 225a9b6aae4SMatteo Facchinetti 226a9b6aae4SMatteo Facchinetti // IO control 227a9b6aae4SMatteo Facchinetti ioctl@a000 { 228a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-ioctl"; 229a9b6aae4SMatteo Facchinetti reg = <0xA000 0x1000>; 230a9b6aae4SMatteo Facchinetti }; 231a9b6aae4SMatteo Facchinetti 23211daf32bSMatteo Facchinetti // disable USB1 port 23311daf32bSMatteo Facchinetti // TODO: 23411daf32bSMatteo Facchinetti // correct pinmux config and fix USB3320 ulpi dependency 23511daf32bSMatteo Facchinetti // before re-enabling it 236a9b6aae4SMatteo Facchinetti usb@3000 { 237a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-usb2-dr"; 238a9b6aae4SMatteo Facchinetti reg = <0x3000 0x400>; 239a9b6aae4SMatteo Facchinetti #address-cells = <1>; 240a9b6aae4SMatteo Facchinetti #size-cells = <0>; 241a9b6aae4SMatteo Facchinetti interrupts = <43 0x8>; 242a9b6aae4SMatteo Facchinetti dr_mode = "host"; 243a9b6aae4SMatteo Facchinetti phy_type = "ulpi"; 244bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_USB1>; 245bc750594SGerhard Sittig clock-names = "ipg"; 24611daf32bSMatteo Facchinetti status = "disabled"; 247a9b6aae4SMatteo Facchinetti }; 248a9b6aae4SMatteo Facchinetti 249a9b6aae4SMatteo Facchinetti // 5125 PSCs are not 52xx or 5121 PSC compatible 250a9b6aae4SMatteo Facchinetti // PSC1 uart0 aka ttyPSC0 251a9b6aae4SMatteo Facchinetti serial@11100 { 252a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc"; 253a9b6aae4SMatteo Facchinetti reg = <0x11100 0x100>; 254a9b6aae4SMatteo Facchinetti interrupts = <40 0x8>; 255a9b6aae4SMatteo Facchinetti fsl,rx-fifo-size = <16>; 256a9b6aae4SMatteo Facchinetti fsl,tx-fifo-size = <16>; 257bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_PSC1>, 258bc750594SGerhard Sittig <&clks MPC512x_CLK_PSC1_MCLK>; 259bc750594SGerhard Sittig clock-names = "ipg", "mclk"; 260a9b6aae4SMatteo Facchinetti }; 261a9b6aae4SMatteo Facchinetti 262a9b6aae4SMatteo Facchinetti // PSC9 uart1 aka ttyPSC1 263a9b6aae4SMatteo Facchinetti serial@11900 { 264a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc"; 265a9b6aae4SMatteo Facchinetti reg = <0x11900 0x100>; 266a9b6aae4SMatteo Facchinetti interrupts = <40 0x8>; 267a9b6aae4SMatteo Facchinetti fsl,rx-fifo-size = <16>; 268a9b6aae4SMatteo Facchinetti fsl,tx-fifo-size = <16>; 269bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_PSC9>, 270bc750594SGerhard Sittig <&clks MPC512x_CLK_PSC9_MCLK>; 271bc750594SGerhard Sittig clock-names = "ipg", "mclk"; 272a9b6aae4SMatteo Facchinetti }; 273a9b6aae4SMatteo Facchinetti 274a9b6aae4SMatteo Facchinetti pscfifo@11f00 { 275a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-psc-fifo"; 276a9b6aae4SMatteo Facchinetti reg = <0x11f00 0x100>; 277a9b6aae4SMatteo Facchinetti interrupts = <40 0x8>; 278bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_PSC_FIFO>; 279bc750594SGerhard Sittig clock-names = "ipg"; 280a9b6aae4SMatteo Facchinetti }; 281a9b6aae4SMatteo Facchinetti 282a9b6aae4SMatteo Facchinetti dma@14000 { 283a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2" 284a9b6aae4SMatteo Facchinetti reg = <0x14000 0x1800>; 285a9b6aae4SMatteo Facchinetti interrupts = <65 0x8>; 286a9b6aae4SMatteo Facchinetti }; 287a9b6aae4SMatteo Facchinetti }; 288a9b6aae4SMatteo Facchinetti}; 289