12874c5fdSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-or-later 2a9b6aae4SMatteo Facchinetti/* 3a9b6aae4SMatteo Facchinetti * STx/Freescale ADS5125 MPC5125 silicon 4a9b6aae4SMatteo Facchinetti * 5a9b6aae4SMatteo Facchinetti * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved. 6a9b6aae4SMatteo Facchinetti * 7a9b6aae4SMatteo Facchinetti * Reworked by Matteo Facchinetti (engineering@sirius-es.it) 8a9b6aae4SMatteo Facchinetti * Copyright (C) 2013 Sirius Electronic Systems 9a9b6aae4SMatteo Facchinetti */ 10a9b6aae4SMatteo Facchinetti 11bc750594SGerhard Sittig#include <dt-bindings/clock/mpc512x-clock.h> 12bc750594SGerhard Sittig 13a9b6aae4SMatteo Facchinetti/dts-v1/; 14a9b6aae4SMatteo Facchinetti 15a9b6aae4SMatteo Facchinetti/ { 16a9b6aae4SMatteo Facchinetti model = "mpc5125twr"; // In BSP "mpc5125ads" 17a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125ads", "fsl,mpc5125"; 18a9b6aae4SMatteo Facchinetti #address-cells = <1>; 19a9b6aae4SMatteo Facchinetti #size-cells = <1>; 20a9b6aae4SMatteo Facchinetti interrupt-parent = <&ipic>; 21a9b6aae4SMatteo Facchinetti 22a9b6aae4SMatteo Facchinetti aliases { 23a9b6aae4SMatteo Facchinetti gpio0 = &gpio0; 24a9b6aae4SMatteo Facchinetti gpio1 = &gpio1; 25a9b6aae4SMatteo Facchinetti ethernet0 = ð0; 26a9b6aae4SMatteo Facchinetti }; 27a9b6aae4SMatteo Facchinetti 28a9b6aae4SMatteo Facchinetti cpus { 29a9b6aae4SMatteo Facchinetti #address-cells = <1>; 30a9b6aae4SMatteo Facchinetti #size-cells = <0>; 31a9b6aae4SMatteo Facchinetti 32a9b6aae4SMatteo Facchinetti PowerPC,5125@0 { 33a9b6aae4SMatteo Facchinetti device_type = "cpu"; 34a9b6aae4SMatteo Facchinetti reg = <0>; 35a9b6aae4SMatteo Facchinetti d-cache-line-size = <0x20>; // 32 bytes 36a9b6aae4SMatteo Facchinetti i-cache-line-size = <0x20>; // 32 bytes 37a9b6aae4SMatteo Facchinetti d-cache-size = <0x8000>; // L1, 32K 38a9b6aae4SMatteo Facchinetti i-cache-size = <0x8000>; // L1, 32K 39a9b6aae4SMatteo Facchinetti timebase-frequency = <49500000>;// 49.5 MHz (csb/4) 40a9b6aae4SMatteo Facchinetti bus-frequency = <198000000>; // 198 MHz csb bus 41a9b6aae4SMatteo Facchinetti clock-frequency = <396000000>; // 396 MHz ppc core 42a9b6aae4SMatteo Facchinetti }; 43a9b6aae4SMatteo Facchinetti }; 44a9b6aae4SMatteo Facchinetti 45a9b6aae4SMatteo Facchinetti memory { 46a9b6aae4SMatteo Facchinetti device_type = "memory"; 47a9b6aae4SMatteo Facchinetti reg = <0x00000000 0x10000000>; // 256MB at 0 48a9b6aae4SMatteo Facchinetti }; 49a9b6aae4SMatteo Facchinetti 50a9b6aae4SMatteo Facchinetti sram@30000000 { 51a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-sram"; 52a9b6aae4SMatteo Facchinetti reg = <0x30000000 0x08000>; // 32K at 0x30000000 53a9b6aae4SMatteo Facchinetti }; 54a9b6aae4SMatteo Facchinetti 55bc750594SGerhard Sittig clocks { 56bc750594SGerhard Sittig #address-cells = <1>; 57bc750594SGerhard Sittig #size-cells = <0>; 58bc750594SGerhard Sittig 59bc750594SGerhard Sittig osc: osc { 60bc750594SGerhard Sittig compatible = "fixed-clock"; 61bc750594SGerhard Sittig #clock-cells = <0>; 62bc750594SGerhard Sittig clock-frequency = <33000000>; 63bc750594SGerhard Sittig }; 64bc750594SGerhard Sittig }; 65bc750594SGerhard Sittig 66a9b6aae4SMatteo Facchinetti soc@80000000 { 67a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-immr"; 68a9b6aae4SMatteo Facchinetti #address-cells = <1>; 69a9b6aae4SMatteo Facchinetti #size-cells = <1>; 70a9b6aae4SMatteo Facchinetti ranges = <0x0 0x80000000 0x400000>; 71a9b6aae4SMatteo Facchinetti reg = <0x80000000 0x400000>; 72a9b6aae4SMatteo Facchinetti bus-frequency = <66000000>; // 66 MHz ips bus 73a9b6aae4SMatteo Facchinetti 74a9b6aae4SMatteo Facchinetti // IPIC 75a9b6aae4SMatteo Facchinetti // interrupts cell = <intr #, sense> 76a9b6aae4SMatteo Facchinetti // sense values match linux IORESOURCE_IRQ_* defines: 77a9b6aae4SMatteo Facchinetti // sense == 8: Level, low assertion 78a9b6aae4SMatteo Facchinetti // sense == 2: Edge, high-to-low change 79a9b6aae4SMatteo Facchinetti // 80a9b6aae4SMatteo Facchinetti ipic: interrupt-controller@c00 { 81a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-ipic", "fsl,ipic"; 82a9b6aae4SMatteo Facchinetti interrupt-controller; 83a9b6aae4SMatteo Facchinetti #address-cells = <0>; 84a9b6aae4SMatteo Facchinetti #interrupt-cells = <2>; 85a9b6aae4SMatteo Facchinetti reg = <0xc00 0x100>; 86a9b6aae4SMatteo Facchinetti }; 87a9b6aae4SMatteo Facchinetti 88a9b6aae4SMatteo Facchinetti rtc@a00 { // Real time clock 89a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-rtc"; 90a9b6aae4SMatteo Facchinetti reg = <0xa00 0x100>; 91a9b6aae4SMatteo Facchinetti interrupts = <79 0x8 80 0x8>; 92a9b6aae4SMatteo Facchinetti }; 93a9b6aae4SMatteo Facchinetti 94a9b6aae4SMatteo Facchinetti reset@e00 { // Reset module 95a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-reset"; 96a9b6aae4SMatteo Facchinetti reg = <0xe00 0x100>; 97a9b6aae4SMatteo Facchinetti }; 98a9b6aae4SMatteo Facchinetti 99bc750594SGerhard Sittig clks: clock@f00 { // Clock control 100a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-clock"; 101a9b6aae4SMatteo Facchinetti reg = <0xf00 0x100>; 102bc750594SGerhard Sittig #clock-cells = <1>; 103bc750594SGerhard Sittig clocks = <&osc>; 104bc750594SGerhard Sittig clock-names = "osc"; 105a9b6aae4SMatteo Facchinetti }; 106a9b6aae4SMatteo Facchinetti 107a9b6aae4SMatteo Facchinetti pmc@1000{ // Power Management Controller 108a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-pmc"; 109a9b6aae4SMatteo Facchinetti reg = <0x1000 0x100>; 110a9b6aae4SMatteo Facchinetti interrupts = <83 0x2>; 111a9b6aae4SMatteo Facchinetti }; 112a9b6aae4SMatteo Facchinetti 113a9b6aae4SMatteo Facchinetti gpio0: gpio@1100 { 114a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-gpio"; 115a9b6aae4SMatteo Facchinetti reg = <0x1100 0x080>; 116a9b6aae4SMatteo Facchinetti interrupts = <78 0x8>; 117a9b6aae4SMatteo Facchinetti }; 118a9b6aae4SMatteo Facchinetti 119a9b6aae4SMatteo Facchinetti gpio1: gpio@1180 { 120a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-gpio"; 121a9b6aae4SMatteo Facchinetti reg = <0x1180 0x080>; 122a9b6aae4SMatteo Facchinetti interrupts = <86 0x8>; 123a9b6aae4SMatteo Facchinetti }; 124a9b6aae4SMatteo Facchinetti 125a9b6aae4SMatteo Facchinetti can@1300 { // CAN rev.2 126a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-mscan"; 127a9b6aae4SMatteo Facchinetti interrupts = <12 0x8>; 128a9b6aae4SMatteo Facchinetti reg = <0x1300 0x80>; 129bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_BDLC>, 130bc750594SGerhard Sittig <&clks MPC512x_CLK_IPS>, 131bc750594SGerhard Sittig <&clks MPC512x_CLK_SYS>, 132bc750594SGerhard Sittig <&clks MPC512x_CLK_REF>, 133bc750594SGerhard Sittig <&clks MPC512x_CLK_MSCAN0_MCLK>; 134bc750594SGerhard Sittig clock-names = "ipg", "ips", "sys", "ref", "mclk"; 135a9b6aae4SMatteo Facchinetti }; 136a9b6aae4SMatteo Facchinetti 137a9b6aae4SMatteo Facchinetti can@1380 { 138a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-mscan"; 139a9b6aae4SMatteo Facchinetti interrupts = <13 0x8>; 140a9b6aae4SMatteo Facchinetti reg = <0x1380 0x80>; 141bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_BDLC>, 142bc750594SGerhard Sittig <&clks MPC512x_CLK_IPS>, 143bc750594SGerhard Sittig <&clks MPC512x_CLK_SYS>, 144bc750594SGerhard Sittig <&clks MPC512x_CLK_REF>, 145bc750594SGerhard Sittig <&clks MPC512x_CLK_MSCAN1_MCLK>; 146bc750594SGerhard Sittig clock-names = "ipg", "ips", "sys", "ref", "mclk"; 147a9b6aae4SMatteo Facchinetti }; 148a9b6aae4SMatteo Facchinetti 149a9b6aae4SMatteo Facchinetti sdhc@1500 { 150a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-sdhc"; 151a9b6aae4SMatteo Facchinetti interrupts = <8 0x8>; 152a9b6aae4SMatteo Facchinetti reg = <0x1500 0x100>; 153bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_IPS>, 154bc750594SGerhard Sittig <&clks MPC512x_CLK_SDHC>; 155bc750594SGerhard Sittig clock-names = "ipg", "per"; 156a9b6aae4SMatteo Facchinetti }; 157a9b6aae4SMatteo Facchinetti 158a9b6aae4SMatteo Facchinetti i2c@1700 { 159a9b6aae4SMatteo Facchinetti #address-cells = <1>; 160a9b6aae4SMatteo Facchinetti #size-cells = <0>; 161a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 162a9b6aae4SMatteo Facchinetti reg = <0x1700 0x20>; 163a9b6aae4SMatteo Facchinetti interrupts = <0x9 0x8>; 164bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_I2C>; 165bc750594SGerhard Sittig clock-names = "ipg"; 166a9b6aae4SMatteo Facchinetti }; 167a9b6aae4SMatteo Facchinetti 168a9b6aae4SMatteo Facchinetti i2c@1720 { 169a9b6aae4SMatteo Facchinetti #address-cells = <1>; 170a9b6aae4SMatteo Facchinetti #size-cells = <0>; 171a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 172a9b6aae4SMatteo Facchinetti reg = <0x1720 0x20>; 173a9b6aae4SMatteo Facchinetti interrupts = <0xa 0x8>; 174bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_I2C>; 175bc750594SGerhard Sittig clock-names = "ipg"; 176a9b6aae4SMatteo Facchinetti }; 177a9b6aae4SMatteo Facchinetti 178a9b6aae4SMatteo Facchinetti i2c@1740 { 179a9b6aae4SMatteo Facchinetti #address-cells = <1>; 180a9b6aae4SMatteo Facchinetti #size-cells = <0>; 181a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 182a9b6aae4SMatteo Facchinetti reg = <0x1740 0x20>; 183a9b6aae4SMatteo Facchinetti interrupts = <0xb 0x8>; 184bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_I2C>; 185bc750594SGerhard Sittig clock-names = "ipg"; 186a9b6aae4SMatteo Facchinetti }; 187a9b6aae4SMatteo Facchinetti 188a9b6aae4SMatteo Facchinetti i2ccontrol@1760 { 189a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-i2c-ctrl"; 190a9b6aae4SMatteo Facchinetti reg = <0x1760 0x8>; 191a9b6aae4SMatteo Facchinetti }; 192a9b6aae4SMatteo Facchinetti 193a9b6aae4SMatteo Facchinetti diu@2100 { 194a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-diu"; 195a9b6aae4SMatteo Facchinetti reg = <0x2100 0x100>; 196a9b6aae4SMatteo Facchinetti interrupts = <64 0x8>; 197bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_DIU>; 198bc750594SGerhard Sittig clock-names = "ipg"; 199a9b6aae4SMatteo Facchinetti }; 200a9b6aae4SMatteo Facchinetti 201a9b6aae4SMatteo Facchinetti mdio@2800 { 202a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-fec-mdio"; 203a9b6aae4SMatteo Facchinetti reg = <0x2800 0x800>; 204a9b6aae4SMatteo Facchinetti #address-cells = <1>; 205a9b6aae4SMatteo Facchinetti #size-cells = <0>; 206a9b6aae4SMatteo Facchinetti phy0: ethernet-phy@0 { 207a9b6aae4SMatteo Facchinetti reg = <1>; 208a9b6aae4SMatteo Facchinetti }; 209a9b6aae4SMatteo Facchinetti }; 210a9b6aae4SMatteo Facchinetti 211a9b6aae4SMatteo Facchinetti eth0: ethernet@2800 { 212a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-fec"; 213a9b6aae4SMatteo Facchinetti reg = <0x2800 0x800>; 214a9b6aae4SMatteo Facchinetti local-mac-address = [ 00 00 00 00 00 00 ]; 215a9b6aae4SMatteo Facchinetti interrupts = <4 0x8>; 216a9b6aae4SMatteo Facchinetti phy-handle = < &phy0 >; 217a9b6aae4SMatteo Facchinetti phy-connection-type = "rmii"; 218bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_FEC>; 219bc750594SGerhard Sittig clock-names = "per"; 220a9b6aae4SMatteo Facchinetti }; 221a9b6aae4SMatteo Facchinetti 222a9b6aae4SMatteo Facchinetti // IO control 223a9b6aae4SMatteo Facchinetti ioctl@a000 { 224a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-ioctl"; 225a9b6aae4SMatteo Facchinetti reg = <0xA000 0x1000>; 226a9b6aae4SMatteo Facchinetti }; 227a9b6aae4SMatteo Facchinetti 22811daf32bSMatteo Facchinetti // disable USB1 port 22911daf32bSMatteo Facchinetti // TODO: 23011daf32bSMatteo Facchinetti // correct pinmux config and fix USB3320 ulpi dependency 23111daf32bSMatteo Facchinetti // before re-enabling it 232a9b6aae4SMatteo Facchinetti usb@3000 { 233a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-usb2-dr"; 234a9b6aae4SMatteo Facchinetti reg = <0x3000 0x400>; 235a9b6aae4SMatteo Facchinetti #address-cells = <1>; 236a9b6aae4SMatteo Facchinetti #size-cells = <0>; 237a9b6aae4SMatteo Facchinetti interrupts = <43 0x8>; 238a9b6aae4SMatteo Facchinetti dr_mode = "host"; 239a9b6aae4SMatteo Facchinetti phy_type = "ulpi"; 240bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_USB1>; 241bc750594SGerhard Sittig clock-names = "ipg"; 24211daf32bSMatteo Facchinetti status = "disabled"; 243a9b6aae4SMatteo Facchinetti }; 244a9b6aae4SMatteo Facchinetti 245de03fe28SAlexander Popov sclpc@10100 { 246de03fe28SAlexander Popov compatible = "fsl,mpc512x-lpbfifo"; 247de03fe28SAlexander Popov reg = <0x10100 0x50>; 248de03fe28SAlexander Popov interrupts = <7 0x8>; 249de03fe28SAlexander Popov dmas = <&dma0 26>; 250de03fe28SAlexander Popov dma-names = "rx-tx"; 251de03fe28SAlexander Popov }; 252de03fe28SAlexander Popov 253a9b6aae4SMatteo Facchinetti // 5125 PSCs are not 52xx or 5121 PSC compatible 254a9b6aae4SMatteo Facchinetti // PSC1 uart0 aka ttyPSC0 255a9b6aae4SMatteo Facchinetti serial@11100 { 256a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc"; 257a9b6aae4SMatteo Facchinetti reg = <0x11100 0x100>; 258a9b6aae4SMatteo Facchinetti interrupts = <40 0x8>; 259a9b6aae4SMatteo Facchinetti fsl,rx-fifo-size = <16>; 260a9b6aae4SMatteo Facchinetti fsl,tx-fifo-size = <16>; 261bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_PSC1>, 262bc750594SGerhard Sittig <&clks MPC512x_CLK_PSC1_MCLK>; 263bc750594SGerhard Sittig clock-names = "ipg", "mclk"; 264a9b6aae4SMatteo Facchinetti }; 265a9b6aae4SMatteo Facchinetti 266a9b6aae4SMatteo Facchinetti // PSC9 uart1 aka ttyPSC1 267a9b6aae4SMatteo Facchinetti serial@11900 { 268a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc"; 269a9b6aae4SMatteo Facchinetti reg = <0x11900 0x100>; 270a9b6aae4SMatteo Facchinetti interrupts = <40 0x8>; 271a9b6aae4SMatteo Facchinetti fsl,rx-fifo-size = <16>; 272a9b6aae4SMatteo Facchinetti fsl,tx-fifo-size = <16>; 273bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_PSC9>, 274bc750594SGerhard Sittig <&clks MPC512x_CLK_PSC9_MCLK>; 275bc750594SGerhard Sittig clock-names = "ipg", "mclk"; 276a9b6aae4SMatteo Facchinetti }; 277a9b6aae4SMatteo Facchinetti 278a9b6aae4SMatteo Facchinetti pscfifo@11f00 { 279a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-psc-fifo"; 280a9b6aae4SMatteo Facchinetti reg = <0x11f00 0x100>; 281a9b6aae4SMatteo Facchinetti interrupts = <40 0x8>; 282bc750594SGerhard Sittig clocks = <&clks MPC512x_CLK_PSC_FIFO>; 283bc750594SGerhard Sittig clock-names = "ipg"; 284a9b6aae4SMatteo Facchinetti }; 285a9b6aae4SMatteo Facchinetti 286de03fe28SAlexander Popov dma0: dma@14000 { 287a9b6aae4SMatteo Facchinetti compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2" 288a9b6aae4SMatteo Facchinetti reg = <0x14000 0x1800>; 289a9b6aae4SMatteo Facchinetti interrupts = <65 0x8>; 290de03fe28SAlexander Popov #dma-cells = <1>; 291a9b6aae4SMatteo Facchinetti }; 292a9b6aae4SMatteo Facchinetti }; 293a9b6aae4SMatteo Facchinetti}; 294