1/*
2 * base MPC5121 Device Tree Source
3 *
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12#include <dt-bindings/clock/mpc512x-clock.h>
13
14/dts-v1/;
15
16/ {
17	model = "mpc5121";
18	compatible = "fsl,mpc5121";
19	#address-cells = <1>;
20	#size-cells = <1>;
21        interrupt-parent = <&ipic>;
22
23	aliases {
24		ethernet0 = &eth0;
25		pci = &pci;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,5121@0 {
33			device_type = "cpu";
34			reg = <0>;
35			d-cache-line-size = <0x20>;	/* 32 bytes */
36			i-cache-line-size = <0x20>;	/* 32 bytes */
37			d-cache-size = <0x8000>;	/* L1, 32K */
38			i-cache-size = <0x8000>;	/* L1, 32K */
39			timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
40			bus-frequency = <198000000>;	/* 198 MHz csb bus */
41			clock-frequency = <396000000>;	/* 396 MHz ppc core */
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x10000000>;	/* 256MB at 0 */
48	};
49
50	mbx@20000000 {
51		compatible = "fsl,mpc5121-mbx";
52		reg = <0x20000000 0x4000>;
53		interrupts = <66 0x8>;
54	};
55
56	sram@30000000 {
57		compatible = "fsl,mpc5121-sram";
58		reg = <0x30000000 0x20000>;	/* 128K at 0x30000000 */
59	};
60
61	nfc@40000000 {
62		compatible = "fsl,mpc5121-nfc";
63		reg = <0x40000000 0x100000>;	/* 1M at 0x40000000 */
64		interrupts = <6 8>;
65		#address-cells = <1>;
66		#size-cells = <1>;
67	};
68
69	localbus@80000020 {
70		compatible = "fsl,mpc5121-localbus";
71		#address-cells = <2>;
72		#size-cells = <1>;
73		reg = <0x80000020 0x40>;
74		interrupts = <7 0x8>;
75		ranges = <0x0 0x0 0xfc000000 0x04000000>;
76	};
77
78	clocks {
79		#address-cells = <1>;
80		#size-cells = <0>;
81
82		osc: osc {
83			compatible = "fixed-clock";
84			#clock-cells = <0>;
85			clock-frequency = <33000000>;
86		};
87	};
88
89	soc@80000000 {
90		compatible = "fsl,mpc5121-immr";
91		#address-cells = <1>;
92		#size-cells = <1>;
93		ranges = <0x0 0x80000000 0x400000>;
94		reg = <0x80000000 0x400000>;
95		bus-frequency = <66000000>;	/* 66 MHz ips bus */
96
97
98		/*
99		 * IPIC
100		 * interrupts cell = <intr #, sense>
101		 * sense values match linux IORESOURCE_IRQ_* defines:
102		 * sense == 8: Level, low assertion
103		 * sense == 2: Edge, high-to-low change
104		 */
105		ipic: interrupt-controller@c00 {
106			compatible = "fsl,mpc5121-ipic", "fsl,ipic";
107			interrupt-controller;
108			#address-cells = <0>;
109			#interrupt-cells = <2>;
110			reg = <0xc00 0x100>;
111		};
112
113		/* Watchdog timer */
114		wdt@900 {
115			compatible = "fsl,mpc5121-wdt";
116			reg = <0x900 0x100>;
117		};
118
119		/* Real time clock */
120		rtc@a00 {
121			compatible = "fsl,mpc5121-rtc";
122			reg = <0xa00 0x100>;
123			interrupts = <79 0x8 80 0x8>;
124		};
125
126		/* Reset module */
127		reset@e00 {
128			compatible = "fsl,mpc5121-reset";
129			reg = <0xe00 0x100>;
130		};
131
132		/* Clock control */
133		clks: clock@f00 {
134			compatible = "fsl,mpc5121-clock";
135			reg = <0xf00 0x100>;
136			#clock-cells = <1>;
137			clocks = <&osc>;
138			clock-names = "osc";
139		};
140
141		/* Power Management Controller */
142		pmc@1000{
143			compatible = "fsl,mpc5121-pmc";
144			reg = <0x1000 0x100>;
145			interrupts = <83 0x8>;
146		};
147
148		gpio@1100 {
149			compatible = "fsl,mpc5121-gpio";
150			reg = <0x1100 0x100>;
151			interrupts = <78 0x8>;
152		};
153
154		can@1300 {
155			compatible = "fsl,mpc5121-mscan";
156			reg = <0x1300 0x80>;
157			interrupts = <12 0x8>;
158		};
159
160		can@1380 {
161			compatible = "fsl,mpc5121-mscan";
162			reg = <0x1380 0x80>;
163			interrupts = <13 0x8>;
164		};
165
166		sdhc@1500 {
167			compatible = "fsl,mpc5121-sdhc";
168			reg = <0x1500 0x100>;
169			interrupts = <8 0x8>;
170			dmas = <&dma0 30>;
171			dma-names = "rx-tx";
172		};
173
174		i2c@1700 {
175			#address-cells = <1>;
176			#size-cells = <0>;
177			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
178			reg = <0x1700 0x20>;
179			interrupts = <9 0x8>;
180		};
181
182		i2c@1720 {
183			#address-cells = <1>;
184			#size-cells = <0>;
185			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
186			reg = <0x1720 0x20>;
187			interrupts = <10 0x8>;
188		};
189
190		i2c@1740 {
191			#address-cells = <1>;
192			#size-cells = <0>;
193			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
194			reg = <0x1740 0x20>;
195			interrupts = <11 0x8>;
196		};
197
198		i2ccontrol@1760 {
199			compatible = "fsl,mpc5121-i2c-ctrl";
200			reg = <0x1760 0x8>;
201		};
202
203		axe@2000 {
204			compatible = "fsl,mpc5121-axe";
205			reg = <0x2000 0x100>;
206			interrupts = <42 0x8>;
207		};
208
209		display@2100 {
210			compatible = "fsl,mpc5121-diu";
211			reg = <0x2100 0x100>;
212			interrupts = <64 0x8>;
213		};
214
215		can@2300 {
216			compatible = "fsl,mpc5121-mscan";
217			reg = <0x2300 0x80>;
218			interrupts = <90 0x8>;
219		};
220
221		can@2380 {
222			compatible = "fsl,mpc5121-mscan";
223			reg = <0x2380 0x80>;
224			interrupts = <91 0x8>;
225		};
226
227		viu@2400 {
228			compatible = "fsl,mpc5121-viu";
229			reg = <0x2400 0x400>;
230			interrupts = <67 0x8>;
231		};
232
233		mdio@2800 {
234			compatible = "fsl,mpc5121-fec-mdio";
235			reg = <0x2800 0x800>;
236			#address-cells = <1>;
237			#size-cells = <0>;
238		};
239
240		eth0: ethernet@2800 {
241			device_type = "network";
242			compatible = "fsl,mpc5121-fec";
243			reg = <0x2800 0x800>;
244			local-mac-address = [ 00 00 00 00 00 00 ];
245			interrupts = <4 0x8>;
246		};
247
248		/* USB1 using external ULPI PHY */
249		usb@3000 {
250			compatible = "fsl,mpc5121-usb2-dr";
251			reg = <0x3000 0x600>;
252			#address-cells = <1>;
253			#size-cells = <0>;
254			interrupts = <43 0x8>;
255			dr_mode = "otg";
256			phy_type = "ulpi";
257		};
258
259		/* USB0 using internal UTMI PHY */
260		usb@4000 {
261			compatible = "fsl,mpc5121-usb2-dr";
262			reg = <0x4000 0x600>;
263			#address-cells = <1>;
264			#size-cells = <0>;
265			interrupts = <44 0x8>;
266			dr_mode = "otg";
267			phy_type = "utmi_wide";
268		};
269
270		/* IO control */
271		ioctl@a000 {
272			compatible = "fsl,mpc5121-ioctl";
273			reg = <0xA000 0x1000>;
274		};
275
276		/* LocalPlus controller */
277		lpc@10000 {
278			compatible = "fsl,mpc5121-lpc";
279			reg = <0x10000 0x200>;
280		};
281
282		pata@10200 {
283			compatible = "fsl,mpc5121-pata";
284			reg = <0x10200 0x100>;
285			interrupts = <5 0x8>;
286		};
287
288		/* 512x PSCs are not 52xx PSC compatible */
289
290		/* PSC0 */
291		psc@11000 {
292			compatible = "fsl,mpc5121-psc";
293			reg = <0x11000 0x100>;
294			interrupts = <40 0x8>;
295			fsl,rx-fifo-size = <16>;
296			fsl,tx-fifo-size = <16>;
297		};
298
299		/* PSC1 */
300		psc@11100 {
301			compatible = "fsl,mpc5121-psc";
302			reg = <0x11100 0x100>;
303			interrupts = <40 0x8>;
304			fsl,rx-fifo-size = <16>;
305			fsl,tx-fifo-size = <16>;
306		};
307
308		/* PSC2 */
309		psc@11200 {
310			compatible = "fsl,mpc5121-psc";
311			reg = <0x11200 0x100>;
312			interrupts = <40 0x8>;
313			fsl,rx-fifo-size = <16>;
314			fsl,tx-fifo-size = <16>;
315		};
316
317		/* PSC3 */
318		psc@11300 {
319			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
320			reg = <0x11300 0x100>;
321			interrupts = <40 0x8>;
322			fsl,rx-fifo-size = <16>;
323			fsl,tx-fifo-size = <16>;
324		};
325
326		/* PSC4 */
327		psc@11400 {
328			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
329			reg = <0x11400 0x100>;
330			interrupts = <40 0x8>;
331			fsl,rx-fifo-size = <16>;
332			fsl,tx-fifo-size = <16>;
333		};
334
335		/* PSC5 */
336		psc@11500 {
337			compatible = "fsl,mpc5121-psc";
338			reg = <0x11500 0x100>;
339			interrupts = <40 0x8>;
340			fsl,rx-fifo-size = <16>;
341			fsl,tx-fifo-size = <16>;
342		};
343
344		/* PSC6 */
345		psc@11600 {
346			compatible = "fsl,mpc5121-psc";
347			reg = <0x11600 0x100>;
348			interrupts = <40 0x8>;
349			fsl,rx-fifo-size = <16>;
350			fsl,tx-fifo-size = <16>;
351		};
352
353		/* PSC7 */
354		psc@11700 {
355			compatible = "fsl,mpc5121-psc";
356			reg = <0x11700 0x100>;
357			interrupts = <40 0x8>;
358			fsl,rx-fifo-size = <16>;
359			fsl,tx-fifo-size = <16>;
360		};
361
362		/* PSC8 */
363		psc@11800 {
364			compatible = "fsl,mpc5121-psc";
365			reg = <0x11800 0x100>;
366			interrupts = <40 0x8>;
367			fsl,rx-fifo-size = <16>;
368			fsl,tx-fifo-size = <16>;
369		};
370
371		/* PSC9 */
372		psc@11900 {
373			compatible = "fsl,mpc5121-psc";
374			reg = <0x11900 0x100>;
375			interrupts = <40 0x8>;
376			fsl,rx-fifo-size = <16>;
377			fsl,tx-fifo-size = <16>;
378		};
379
380		/* PSC10 */
381		psc@11a00 {
382			compatible = "fsl,mpc5121-psc";
383			reg = <0x11a00 0x100>;
384			interrupts = <40 0x8>;
385			fsl,rx-fifo-size = <16>;
386			fsl,tx-fifo-size = <16>;
387		};
388
389		/* PSC11 */
390		psc@11b00 {
391			compatible = "fsl,mpc5121-psc";
392			reg = <0x11b00 0x100>;
393			interrupts = <40 0x8>;
394			fsl,rx-fifo-size = <16>;
395			fsl,tx-fifo-size = <16>;
396		};
397
398		pscfifo@11f00 {
399			compatible = "fsl,mpc5121-psc-fifo";
400			reg = <0x11f00 0x100>;
401			interrupts = <40 0x8>;
402		};
403
404		dma0: dma@14000 {
405			compatible = "fsl,mpc5121-dma";
406			reg = <0x14000 0x1800>;
407			interrupts = <65 0x8>;
408		};
409	};
410
411	pci: pci@80008500 {
412		compatible = "fsl,mpc5121-pci";
413		device_type = "pci";
414		interrupts = <1 0x8>;
415		clock-frequency = <0>;
416		#address-cells = <3>;
417		#size-cells = <2>;
418		#interrupt-cells = <1>;
419
420		reg = <0x80008500 0x100	/* internal registers */
421		       0x80008300 0x8>;	/* config space access registers */
422		bus-range = <0x0 0x0>;
423		ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
424			  0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
425			  0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
426	};
427};
428