1/* 2 * Motion-PRO board Device Tree Source 3 * 4 * Copyright (C) 2007 Semihalf 5 * Marian Balakowicz <m8@semihalf.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14 15/ { 16 model = "promess,motionpro"; 17 compatible = "promess,motionpro"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 PowerPC,5200@0 { 26 device_type = "cpu"; 27 reg = <0>; 28 d-cache-line-size = <32>; 29 i-cache-line-size = <32>; 30 d-cache-size = <0x4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K 32 timebase-frequency = <0>; // from bootloader 33 bus-frequency = <0>; // from bootloader 34 clock-frequency = <0>; // from bootloader 35 }; 36 }; 37 38 memory { 39 device_type = "memory"; 40 reg = <0x00000000 0x04000000>; // 64MB 41 }; 42 43 soc5200@f0000000 { 44 #address-cells = <1>; 45 #size-cells = <1>; 46 compatible = "fsl,mpc5200b-immr"; 47 ranges = <0 0xf0000000 0x0000c000>; 48 reg = <0xf0000000 0x00000100>; 49 bus-frequency = <0>; // from bootloader 50 system-frequency = <0>; // from bootloader 51 52 cdm@200 { 53 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 54 reg = <0x200 0x38>; 55 }; 56 57 mpc5200_pic: interrupt-controller@500 { 58 // 5200 interrupts are encoded into two levels; 59 interrupt-controller; 60 #interrupt-cells = <3>; 61 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 62 reg = <0x500 0x80>; 63 }; 64 65 timer@600 { // General Purpose Timer 66 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 reg = <0x600 0x10>; 68 interrupts = <1 9 0>; 69 interrupt-parent = <&mpc5200_pic>; 70 fsl,has-wdt; 71 }; 72 73 timer@610 { // General Purpose Timer 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 75 reg = <0x610 0x10>; 76 interrupts = <1 10 0>; 77 interrupt-parent = <&mpc5200_pic>; 78 }; 79 80 timer@620 { // General Purpose Timer 81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 82 reg = <0x620 0x10>; 83 interrupts = <1 11 0>; 84 interrupt-parent = <&mpc5200_pic>; 85 }; 86 87 timer@630 { // General Purpose Timer 88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 89 reg = <0x630 0x10>; 90 interrupts = <1 12 0>; 91 interrupt-parent = <&mpc5200_pic>; 92 }; 93 94 timer@640 { // General Purpose Timer 95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 96 reg = <0x640 0x10>; 97 interrupts = <1 13 0>; 98 interrupt-parent = <&mpc5200_pic>; 99 }; 100 101 timer@650 { // General Purpose Timer 102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 103 reg = <0x650 0x10>; 104 interrupts = <1 14 0>; 105 interrupt-parent = <&mpc5200_pic>; 106 }; 107 108 motionpro-led@660 { // Motion-PRO status LED 109 compatible = "promess,motionpro-led"; 110 label = "motionpro-statusled"; 111 reg = <0x660 0x10>; 112 interrupts = <1 15 0>; 113 interrupt-parent = <&mpc5200_pic>; 114 blink-delay = <100>; // 100 msec 115 }; 116 117 motionpro-led@670 { // Motion-PRO ready LED 118 compatible = "promess,motionpro-led"; 119 label = "motionpro-readyled"; 120 reg = <0x670 0x10>; 121 interrupts = <1 16 0>; 122 interrupt-parent = <&mpc5200_pic>; 123 }; 124 125 rtc@800 { // Real time clock 126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 127 reg = <0x800 0x100>; 128 interrupts = <1 5 0 1 6 0>; 129 interrupt-parent = <&mpc5200_pic>; 130 }; 131 132 can@980 { 133 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 134 interrupts = <2 18 0>; 135 interrupt-parent = <&mpc5200_pic>; 136 reg = <0x980 0x80>; 137 }; 138 139 gpio@b00 { 140 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 141 reg = <0xb00 0x40>; 142 interrupts = <1 7 0>; 143 interrupt-parent = <&mpc5200_pic>; 144 }; 145 146 gpio@c00 { 147 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 148 reg = <0xc00 0x40>; 149 interrupts = <1 8 0 0 3 0>; 150 interrupt-parent = <&mpc5200_pic>; 151 }; 152 153 spi@f00 { 154 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 155 reg = <0xf00 0x20>; 156 interrupts = <2 13 0 2 14 0>; 157 interrupt-parent = <&mpc5200_pic>; 158 }; 159 160 usb@1000 { 161 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 162 reg = <0x1000 0xff>; 163 interrupts = <2 6 0>; 164 interrupt-parent = <&mpc5200_pic>; 165 }; 166 167 dma-controller@1200 { 168 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 169 reg = <0x1200 0x80>; 170 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 171 3 4 0 3 5 0 3 6 0 3 7 0 172 3 8 0 3 9 0 3 10 0 3 11 0 173 3 12 0 3 13 0 3 14 0 3 15 0>; 174 interrupt-parent = <&mpc5200_pic>; 175 }; 176 177 xlb@1f00 { 178 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 179 reg = <0x1f00 0x100>; 180 }; 181 182 serial@2000 { // PSC1 183 device_type = "serial"; 184 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 185 port-number = <0>; // Logical port assignment 186 reg = <0x2000 0x100>; 187 interrupts = <2 1 0>; 188 interrupt-parent = <&mpc5200_pic>; 189 }; 190 191 // PSC2 in spi master mode 192 spi@2200 { // PSC2 193 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; 194 cell-index = <1>; 195 reg = <0x2200 0x100>; 196 interrupts = <2 2 0>; 197 interrupt-parent = <&mpc5200_pic>; 198 }; 199 200 // PSC5 in uart mode 201 serial@2800 { // PSC5 202 device_type = "serial"; 203 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 204 port-number = <4>; // Logical port assignment 205 reg = <0x2800 0x100>; 206 interrupts = <2 12 0>; 207 interrupt-parent = <&mpc5200_pic>; 208 }; 209 210 ethernet@3000 { 211 device_type = "network"; 212 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 213 reg = <0x3000 0x400>; 214 local-mac-address = [ 00 00 00 00 00 00 ]; 215 interrupts = <2 5 0>; 216 interrupt-parent = <&mpc5200_pic>; 217 phy-handle = <&phy0>; 218 }; 219 220 mdio@3000 { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 224 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 225 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 226 interrupt-parent = <&mpc5200_pic>; 227 228 phy0: ethernet-phy@2 { 229 device_type = "ethernet-phy"; 230 reg = <2>; 231 }; 232 }; 233 234 ata@3a00 { 235 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 236 reg = <0x3a00 0x100>; 237 interrupts = <2 7 0>; 238 interrupt-parent = <&mpc5200_pic>; 239 }; 240 241 i2c@3d40 { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 245 reg = <0x3d40 0x40>; 246 interrupts = <2 16 0>; 247 interrupt-parent = <&mpc5200_pic>; 248 fsl5200-clocking; 249 250 rtc@68 { 251 compatible = "dallas,ds1339"; 252 reg = <0x68>; 253 }; 254 }; 255 256 sram@8000 { 257 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 258 reg = <0x8000 0x4000>; 259 }; 260 }; 261 262 lpb { 263 compatible = "fsl,lpb"; 264 #address-cells = <2>; 265 #size-cells = <1>; 266 ranges = <0 0 0xff000000 0x01000000 267 1 0 0x50000000 0x00010000 268 2 0 0x50010000 0x00010000 269 3 0 0x50020000 0x00010000>; 270 271 // 8-bit DualPort SRAM on LocalPlus Bus CS1 272 kollmorgen@1,0 { 273 compatible = "promess,motionpro-kollmorgen"; 274 reg = <1 0 0x10000>; 275 interrupts = <1 1 0>; 276 interrupt-parent = <&mpc5200_pic>; 277 }; 278 279 // 8-bit board CPLD on LocalPlus Bus CS2 280 cpld@2,0 { 281 compatible = "promess,motionpro-cpld"; 282 reg = <2 0 0x10000>; 283 }; 284 285 // 8-bit custom Anybus Module on LocalPlus Bus CS3 286 anybus@3,0 { 287 compatible = "promess,motionpro-anybus"; 288 reg = <3 0 0x10000>; 289 }; 290 pro_module_general@3,0 { 291 compatible = "promess,pro_module_general"; 292 reg = <3 0 3>; 293 }; 294 pro_module_dio@3,800 { 295 compatible = "promess,pro_module_dio"; 296 reg = <3 0x800 2>; 297 }; 298 299 // 16-bit flash device at LocalPlus Bus CS0 300 flash@0,0 { 301 compatible = "cfi-flash"; 302 reg = <0 0 0x01000000>; 303 bank-width = <2>; 304 device-width = <2>; 305 #size-cells = <1>; 306 #address-cells = <1>; 307 }; 308 }; 309}; 310