1/* 2 * Motion-PRO board Device Tree Source 3 * 4 * Copyright (C) 2007 Semihalf 5 * Marian Balakowicz <m8@semihalf.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/ { 14 model = "promess,motionpro"; 15 compatible = "promess,motionpro"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 PowerPC,5200@0 { 24 device_type = "cpu"; 25 reg = <0>; 26 d-cache-line-size = <20>; 27 i-cache-line-size = <20>; 28 d-cache-size = <4000>; // L1, 16K 29 i-cache-size = <4000>; // L1, 16K 30 timebase-frequency = <0>; // from bootloader 31 bus-frequency = <0>; // from bootloader 32 clock-frequency = <0>; // from bootloader 33 }; 34 }; 35 36 memory { 37 device_type = "memory"; 38 reg = <00000000 04000000>; // 64MB 39 }; 40 41 soc5200@f0000000 { 42 #address-cells = <1>; 43 #size-cells = <1>; 44 compatible = "fsl,mpc5200b-immr"; 45 ranges = <0 f0000000 0000c000>; 46 reg = <f0000000 00000100>; 47 bus-frequency = <0>; // from bootloader 48 system-frequency = <0>; // from bootloader 49 50 cdm@200 { 51 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 52 reg = <200 38>; 53 }; 54 55 mpc5200_pic: interrupt-controller@500 { 56 // 5200 interrupts are encoded into two levels; 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 60 reg = <500 80>; 61 }; 62 63 timer@600 { // General Purpose Timer 64 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 65 reg = <600 10>; 66 interrupts = <1 9 0>; 67 interrupt-parent = <&mpc5200_pic>; 68 fsl,has-wdt; 69 }; 70 71 timer@610 { // General Purpose Timer 72 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 73 reg = <610 10>; 74 interrupts = <1 a 0>; 75 interrupt-parent = <&mpc5200_pic>; 76 }; 77 78 timer@620 { // General Purpose Timer 79 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 reg = <620 10>; 81 interrupts = <1 b 0>; 82 interrupt-parent = <&mpc5200_pic>; 83 }; 84 85 timer@630 { // General Purpose Timer 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 87 reg = <630 10>; 88 interrupts = <1 c 0>; 89 interrupt-parent = <&mpc5200_pic>; 90 }; 91 92 timer@640 { // General Purpose Timer 93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 94 reg = <640 10>; 95 interrupts = <1 d 0>; 96 interrupt-parent = <&mpc5200_pic>; 97 }; 98 99 timer@650 { // General Purpose Timer 100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 101 reg = <650 10>; 102 interrupts = <1 e 0>; 103 interrupt-parent = <&mpc5200_pic>; 104 }; 105 106 motionpro-led@660 { // Motion-PRO status LED 107 compatible = "promess,motionpro-led"; 108 label = "motionpro-statusled"; 109 reg = <660 10>; 110 interrupts = <1 f 0>; 111 interrupt-parent = <&mpc5200_pic>; 112 blink-delay = <64>; // 100 msec 113 }; 114 115 motionpro-led@670 { // Motion-PRO ready LED 116 compatible = "promess,motionpro-led"; 117 label = "motionpro-readyled"; 118 reg = <670 10>; 119 interrupts = <1 10 0>; 120 interrupt-parent = <&mpc5200_pic>; 121 }; 122 123 rtc@800 { // Real time clock 124 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 125 reg = <800 100>; 126 interrupts = <1 5 0 1 6 0>; 127 interrupt-parent = <&mpc5200_pic>; 128 }; 129 130 mscan@980 { 131 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 132 interrupts = <2 12 0>; 133 interrupt-parent = <&mpc5200_pic>; 134 reg = <980 80>; 135 }; 136 137 gpio@b00 { 138 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 139 reg = <b00 40>; 140 interrupts = <1 7 0>; 141 interrupt-parent = <&mpc5200_pic>; 142 }; 143 144 gpio@c00 { 145 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 146 reg = <c00 40>; 147 interrupts = <1 8 0 0 3 0>; 148 interrupt-parent = <&mpc5200_pic>; 149 }; 150 151 152 spi@f00 { 153 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 154 reg = <f00 20>; 155 interrupts = <2 d 0 2 e 0>; 156 interrupt-parent = <&mpc5200_pic>; 157 }; 158 159 usb@1000 { 160 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 161 reg = <1000 ff>; 162 interrupts = <2 6 0>; 163 interrupt-parent = <&mpc5200_pic>; 164 }; 165 166 dma-controller@1200 { 167 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 168 reg = <1200 80>; 169 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 170 3 4 0 3 5 0 3 6 0 3 7 0 171 3 8 0 3 9 0 3 a 0 3 b 0 172 3 c 0 3 d 0 3 e 0 3 f 0>; 173 interrupt-parent = <&mpc5200_pic>; 174 }; 175 176 xlb@1f00 { 177 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 178 reg = <1f00 100>; 179 }; 180 181 serial@2000 { // PSC1 182 device_type = "serial"; 183 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 184 port-number = <0>; // Logical port assignment 185 reg = <2000 100>; 186 interrupts = <2 1 0>; 187 interrupt-parent = <&mpc5200_pic>; 188 }; 189 190 // PSC2 in spi master mode 191 spi@2200 { // PSC2 192 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; 193 cell-index = <1>; 194 reg = <2200 100>; 195 interrupts = <2 2 0>; 196 interrupt-parent = <&mpc5200_pic>; 197 }; 198 199 // PSC5 in uart mode 200 serial@2800 { // PSC5 201 device_type = "serial"; 202 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 203 port-number = <4>; // Logical port assignment 204 reg = <2800 100>; 205 interrupts = <2 c 0>; 206 interrupt-parent = <&mpc5200_pic>; 207 }; 208 209 ethernet@3000 { 210 device_type = "network"; 211 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 212 reg = <3000 800>; 213 local-mac-address = [ 00 00 00 00 00 00 ]; 214 interrupts = <2 5 0>; 215 interrupt-parent = <&mpc5200_pic>; 216 }; 217 218 ata@3a00 { 219 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 220 reg = <3a00 100>; 221 interrupts = <2 7 0>; 222 interrupt-parent = <&mpc5200_pic>; 223 }; 224 225 i2c@3d40 { 226 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 227 reg = <3d40 40>; 228 interrupts = <2 10 0>; 229 interrupt-parent = <&mpc5200_pic>; 230 fsl5200-clocking; 231 }; 232 233 sram@8000 { 234 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 235 reg = <8000 4000>; 236 }; 237 }; 238 239 lpb { 240 compatible = "fsl,lpb"; 241 #address-cells = <2>; 242 #size-cells = <1>; 243 ranges = <1 0 50000000 00010000 244 2 0 50010000 00010000 245 3 0 50020000 00010000>; 246 247 // 8-bit DualPort SRAM on LocalPlus Bus CS1 248 kollmorgen@1,0 { 249 compatible = "promess,motionpro-kollmorgen"; 250 reg = <1 0 10000>; 251 interrupts = <1 1 0>; 252 interrupt-parent = <&mpc5200_pic>; 253 }; 254 255 // 8-bit board CPLD on LocalPlus Bus CS2 256 cpld@2,0 { 257 compatible = "promess,motionpro-cpld"; 258 reg = <2 0 10000>; 259 }; 260 261 // 8-bit custom Anybus Module on LocalPlus Bus CS3 262 anybus@3,0 { 263 compatible = "promess,motionpro-anybus"; 264 reg = <3 0 10000>; 265 }; 266 pro_module_general@3,0 { 267 compatible = "promess,pro_module_general"; 268 reg = <3 0 3>; 269 }; 270 pro_module_dio@3,800 { 271 compatible = "promess,pro_module_dio"; 272 reg = <3 800 2>; 273 }; 274 }; 275 276 pci@f0000d00 { 277 #interrupt-cells = <1>; 278 #size-cells = <2>; 279 #address-cells = <3>; 280 device_type = "pci"; 281 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 282 reg = <f0000d00 100>; 283 interrupt-map-mask = <f800 0 0 7>; 284 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 285 c000 0 0 2 &mpc5200_pic 1 1 3 286 c000 0 0 3 &mpc5200_pic 1 2 3 287 c000 0 0 4 &mpc5200_pic 1 3 3 288 289 c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot 290 c800 0 0 2 &mpc5200_pic 1 2 3 291 c800 0 0 3 &mpc5200_pic 1 3 3 292 c800 0 0 4 &mpc5200_pic 0 0 3>; 293 clock-frequency = <0>; // From boot loader 294 interrupts = <2 8 0 2 9 0 2 a 0>; 295 interrupt-parent = <&mpc5200_pic>; 296 bus-range = <0 0>; 297 ranges = <42000000 0 80000000 80000000 0 20000000 298 02000000 0 a0000000 a0000000 0 10000000 299 01000000 0 00000000 b0000000 0 01000000>; 300 }; 301}; 302