1/*
2 * Freescale Media5200 board Device Tree Source
3 *
4 * Copyright 2009 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 * Steven Cavanagh <scavanagh@secretlab.ca>
7 *
8 * This program is free software; you can redistribute  it and/or modify it
9 * under  the terms of  the GNU General  Public License as published by the
10 * Free Software Foundation;  either version 2 of the  License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17	model = "fsl,media5200";
18	compatible = "fsl,media5200";
19	#address-cells = <1>;
20	#size-cells = <1>;
21	interrupt-parent = <&mpc5200_pic>;
22
23	aliases {
24		console = &console;
25		ethernet0 = &eth0;
26	};
27
28	chosen {
29		linux,stdout-path = &console;
30	};
31
32	cpus {
33		#address-cells = <1>;
34		#size-cells = <0>;
35
36		PowerPC,5200@0 {
37			device_type = "cpu";
38			reg = <0>;
39			d-cache-line-size = <32>;
40			i-cache-line-size = <32>;
41			d-cache-size = <0x4000>;		// L1, 16K
42			i-cache-size = <0x4000>;		// L1, 16K
43			timebase-frequency = <33000000>;	// 33 MHz, these were configured by U-Boot
44			bus-frequency = <132000000>;		// 132 MHz
45			clock-frequency = <396000000>;		// 396 MHz
46		};
47	};
48
49	memory {
50		device_type = "memory";
51		reg = <0x00000000 0x08000000>;	// 128MB RAM
52	};
53
54	soc@f0000000 {
55		#address-cells = <1>;
56		#size-cells = <1>;
57		compatible = "fsl,mpc5200b-immr";
58		ranges = <0 0xf0000000 0x0000c000>;
59		reg = <0xf0000000 0x00000100>;
60		bus-frequency = <132000000>;// 132 MHz
61		system-frequency = <0>;		// from bootloader
62
63		cdm@200 {
64			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
65			reg = <0x200 0x38>;
66		};
67
68		mpc5200_pic: interrupt-controller@500 {
69			// 5200 interrupts are encoded into two levels;
70			interrupt-controller;
71			#interrupt-cells = <3>;
72			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
73			reg = <0x500 0x80>;
74		};
75
76		timer@600 {	// General Purpose Timer
77			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78			reg = <0x600 0x10>;
79			interrupts = <1 9 0>;
80			fsl,has-wdt;
81		};
82
83		timer@610 {	// General Purpose Timer
84			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85			reg = <0x610 0x10>;
86			interrupts = <1 10 0>;
87		};
88
89		timer@620 {	// General Purpose Timer
90			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
91			reg = <0x620 0x10>;
92			interrupts = <1 11 0>;
93		};
94
95		timer@630 {	// General Purpose Timer
96			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
97			reg = <0x630 0x10>;
98			interrupts = <1 12 0>;
99		};
100
101		timer@640 {	// General Purpose Timer
102			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103			reg = <0x640 0x10>;
104			interrupts = <1 13 0>;
105		};
106
107		timer@650 {	// General Purpose Timer
108			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109			reg = <0x650 0x10>;
110			interrupts = <1 14 0>;
111		};
112
113		timer@660 {	// General Purpose Timer
114			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115			reg = <0x660 0x10>;
116			interrupts = <1 15 0>;
117		};
118
119		timer@670 {	// General Purpose Timer
120			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
121			reg = <0x670 0x10>;
122			interrupts = <1 16 0>;
123		};
124
125		rtc@800 {	// Real time clock
126			compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127			reg = <0x800 0x100>;
128			interrupts = <1 5 0 1 6 0>;
129		};
130
131		can@900 {
132			compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
133			interrupts = <2 17 0>;
134			reg = <0x900 0x80>;
135		};
136
137		can@980 {
138			compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
139			interrupts = <2 18 0>;
140			reg = <0x980 0x80>;
141		};
142
143		gpio_simple: gpio@b00 {
144			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
145			reg = <0xb00 0x40>;
146			interrupts = <1 7 0>;
147			gpio-controller;
148			#gpio-cells = <2>;
149		};
150
151		gpio_wkup: gpio@c00 {
152			compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
153			reg = <0xc00 0x40>;
154			interrupts = <1 8 0 0 3 0>;
155			gpio-controller;
156			#gpio-cells = <2>;
157		};
158
159		spi@f00 {
160			compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
161			reg = <0xf00 0x20>;
162			interrupts = <2 13 0 2 14 0>;
163		};
164
165		usb@1000 {
166			compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
167			reg = <0x1000 0x100>;
168			interrupts = <2 6 0>;
169		};
170
171		dma-controller@1200 {
172			compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
173			reg = <0x1200 0x80>;
174			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
175			              3 4 0  3 5 0  3 6 0  3 7 0
176			              3 8 0  3 9 0  3 10 0  3 11 0
177			              3 12 0  3 13 0  3 14 0  3 15 0>;
178		};
179
180		xlb@1f00 {
181			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
182			reg = <0x1f00 0x100>;
183		};
184
185		// PSC6 in uart mode
186		console: psc@2c00 {		// PSC6
187			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
188			reg = <0x2c00 0x100>;
189			interrupts = <2 4 0>;
190		};
191
192		eth0: ethernet@3000 {
193			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
194			reg = <0x3000 0x400>;
195			local-mac-address = [ 00 00 00 00 00 00 ];
196			interrupts = <2 5 0>;
197			phy-handle = <&phy0>;
198		};
199
200		mdio@3000 {
201			#address-cells = <1>;
202			#size-cells = <0>;
203			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
204			reg = <0x3000 0x400>;	// fec range, since we need to setup fec interrupts
205			interrupts = <2 5 0>;	// these are for "mii command finished", not link changes & co.
206
207			phy0: ethernet-phy@0 {
208				reg = <0>;
209			};
210		};
211
212		ata@3a00 {
213			compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
214			reg = <0x3a00 0x100>;
215			interrupts = <2 7 0>;
216		};
217
218		i2c@3d00 {
219			#address-cells = <1>;
220			#size-cells = <0>;
221			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
222			reg = <0x3d00 0x40>;
223			interrupts = <2 15 0>;
224		};
225
226		i2c@3d40 {
227			#address-cells = <1>;
228			#size-cells = <0>;
229			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
230			reg = <0x3d40 0x40>;
231			interrupts = <2 16 0>;
232		};
233
234		sram@8000 {
235			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
236			reg = <0x8000 0x4000>;
237		};
238	};
239
240	pci@f0000d00 {
241		#interrupt-cells = <1>;
242		#size-cells = <2>;
243		#address-cells = <3>;
244		device_type = "pci";
245		compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
246		reg = <0xf0000d00 0x100>;
247		interrupt-map-mask = <0xf800 0 0 7>;
248		interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
249				 0xc000 0 0 2 &media5200_fpga 0 3
250				 0xc000 0 0 3 &media5200_fpga 0 4
251				 0xc000 0 0 4 &media5200_fpga 0 5
252
253				 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
254				 0xc800 0 0 2 &media5200_fpga 0 4
255				 0xc800 0 0 3 &media5200_fpga 0 5
256				 0xc800 0 0 4 &media5200_fpga 0 2
257
258				 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
259				 0xd000 0 0 2 &media5200_fpga 0 5
260
261				 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
262				>;
263		clock-frequency = <0>; // From boot loader
264		interrupts = <2 8 0 2 9 0 2 10 0>;
265		interrupt-parent = <&mpc5200_pic>;
266		bus-range = <0 0>;
267		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
268			  0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
269			  0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
270	};
271
272	localbus {
273		compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
274		#address-cells = <2>;
275		#size-cells = <1>;
276
277		ranges = < 0 0 0xfc000000 0x02000000
278			   1 0 0xfe000000 0x02000000
279			   2 0 0xf0010000 0x00010000
280			   3 0 0xf0020000 0x00010000 >;
281
282		flash@0,0 {
283			compatible = "amd,am29lv28ml", "cfi-flash";
284			reg = <0 0x0 0x2000000>;		// 32 MB
285			bank-width = <4>;			// Width in bytes of the flash bank
286			device-width = <2>;			// Two devices on each bank
287		};
288
289		flash@1,0 {
290			compatible = "amd,am29lv28ml", "cfi-flash";
291			reg = <1 0 0x2000000>;			// 32 MB
292			bank-width = <4>;			// Width in bytes of the flash bank
293			device-width = <2>;			// Two devices on each bank
294		};
295
296		media5200_fpga: fpga@2,0 {
297			compatible = "fsl,media5200-fpga";
298			interrupt-controller;
299			#interrupt-cells = <2>;	// 0:bank 1:id; no type field
300			reg = <2 0 0x10000>;
301
302			interrupt-parent = <&mpc5200_pic>;
303			interrupts = <0 0 3	// IRQ bank 0
304			              1 1 3>;	// IRQ bank 1
305		};
306
307		uart@3,0 {
308			compatible = "ti,tl16c752bpt";
309			reg = <3 0 0x10000>;
310			interrupt-parent = <&media5200_fpga>;
311			interrupts = <0 0  0 1>; // 2 irqs
312		};
313	};
314};
315