1bfee95bbSGrant Likely/* 2bfee95bbSGrant Likely * Freescale Media5200 board Device Tree Source 3bfee95bbSGrant Likely * 4bfee95bbSGrant Likely * Copyright 2009 Secret Lab Technologies Ltd. 5bfee95bbSGrant Likely * Grant Likely <grant.likely@secretlab.ca> 6bfee95bbSGrant Likely * Steven Cavanagh <scavanagh@secretlab.ca> 7bfee95bbSGrant Likely * 8bfee95bbSGrant Likely * This program is free software; you can redistribute it and/or modify it 9bfee95bbSGrant Likely * under the terms of the GNU General Public License as published by the 10bfee95bbSGrant Likely * Free Software Foundation; either version 2 of the License, or (at your 11bfee95bbSGrant Likely * option) any later version. 12bfee95bbSGrant Likely */ 13bfee95bbSGrant Likely 14c8bf6b52SJohn Bonesio/include/ "mpc5200b.dtsi" 15bfee95bbSGrant Likely 16bfee95bbSGrant Likely/ { 17bfee95bbSGrant Likely model = "fsl,media5200"; 18bfee95bbSGrant Likely compatible = "fsl,media5200"; 19bfee95bbSGrant Likely 20bfee95bbSGrant Likely aliases { 21bfee95bbSGrant Likely console = &console; 22bfee95bbSGrant Likely ethernet0 = ð0; 23bfee95bbSGrant Likely }; 24bfee95bbSGrant Likely 25bfee95bbSGrant Likely chosen { 26bfee95bbSGrant Likely linux,stdout-path = &console; 27bfee95bbSGrant Likely }; 28bfee95bbSGrant Likely 29bfee95bbSGrant Likely cpus { 30bfee95bbSGrant Likely PowerPC,5200@0 { 31bfee95bbSGrant Likely timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot 32bfee95bbSGrant Likely bus-frequency = <132000000>; // 132 MHz 33bfee95bbSGrant Likely clock-frequency = <396000000>; // 396 MHz 34bfee95bbSGrant Likely }; 35bfee95bbSGrant Likely }; 36bfee95bbSGrant Likely 37bfee95bbSGrant Likely memory { 38bfee95bbSGrant Likely reg = <0x00000000 0x08000000>; // 128MB RAM 39bfee95bbSGrant Likely }; 40bfee95bbSGrant Likely 41c8bf6b52SJohn Bonesio soc5200@f0000000 { 42bfee95bbSGrant Likely bus-frequency = <132000000>;// 132 MHz 43bfee95bbSGrant Likely 44bfee95bbSGrant Likely timer@600 { // General Purpose Timer 45bfee95bbSGrant Likely fsl,has-wdt; 46bfee95bbSGrant Likely }; 47bfee95bbSGrant Likely 48c8bf6b52SJohn Bonesio psc@2000 { // PSC1 49c8bf6b52SJohn Bonesio status = "disabled"; 50bfee95bbSGrant Likely }; 51bfee95bbSGrant Likely 52c8bf6b52SJohn Bonesio psc@2200 { // PSC2 53c8bf6b52SJohn Bonesio status = "disabled"; 54bfee95bbSGrant Likely }; 55bfee95bbSGrant Likely 56c8bf6b52SJohn Bonesio psc@2400 { // PSC3 57c8bf6b52SJohn Bonesio status = "disabled"; 58bfee95bbSGrant Likely }; 59bfee95bbSGrant Likely 60c8bf6b52SJohn Bonesio psc@2600 { // PSC4 61c8bf6b52SJohn Bonesio status = "disabled"; 62bfee95bbSGrant Likely }; 63bfee95bbSGrant Likely 64c8bf6b52SJohn Bonesio psc@2800 { // PSC5 65c8bf6b52SJohn Bonesio status = "disabled"; 66bfee95bbSGrant Likely }; 67bfee95bbSGrant Likely 68bfee95bbSGrant Likely // PSC6 in uart mode 69abf1e27fSJohn Bonesio console: psc@2c00 { // PSC6 70bfee95bbSGrant Likely compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 71bfee95bbSGrant Likely }; 72bfee95bbSGrant Likely 73c8bf6b52SJohn Bonesio ethernet@3000 { 74bfee95bbSGrant Likely phy-handle = <&phy0>; 75bfee95bbSGrant Likely }; 76bfee95bbSGrant Likely 77bfee95bbSGrant Likely mdio@3000 { 78bfee95bbSGrant Likely phy0: ethernet-phy@0 { 79bfee95bbSGrant Likely reg = <0>; 80bfee95bbSGrant Likely }; 81bfee95bbSGrant Likely }; 82bfee95bbSGrant Likely 83c8bf6b52SJohn Bonesio usb@1000 { 84c8bf6b52SJohn Bonesio reg = <0x1000 0x100>; 85bfee95bbSGrant Likely }; 86bfee95bbSGrant Likely }; 87bfee95bbSGrant Likely 88bfee95bbSGrant Likely pci@f0000d00 { 89bfee95bbSGrant Likely interrupt-map-mask = <0xf800 0 0 7>; 90bfee95bbSGrant Likely interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot 91bfee95bbSGrant Likely 0xc000 0 0 2 &media5200_fpga 0 3 92bfee95bbSGrant Likely 0xc000 0 0 3 &media5200_fpga 0 4 93bfee95bbSGrant Likely 0xc000 0 0 4 &media5200_fpga 0 5 94bfee95bbSGrant Likely 95bfee95bbSGrant Likely 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot 96bfee95bbSGrant Likely 0xc800 0 0 2 &media5200_fpga 0 4 97bfee95bbSGrant Likely 0xc800 0 0 3 &media5200_fpga 0 5 98bfee95bbSGrant Likely 0xc800 0 0 4 &media5200_fpga 0 2 99bfee95bbSGrant Likely 100bfee95bbSGrant Likely 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI 101bfee95bbSGrant Likely 0xd000 0 0 2 &media5200_fpga 0 5 102bfee95bbSGrant Likely 103bfee95bbSGrant Likely 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP 104bfee95bbSGrant Likely >; 105bfee95bbSGrant Likely ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 106bfee95bbSGrant Likely 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 107bfee95bbSGrant Likely 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 108c8bf6b52SJohn Bonesio interrupt-parent = <&mpc5200_pic>; 109bfee95bbSGrant Likely }; 110bfee95bbSGrant Likely 111bfee95bbSGrant Likely localbus { 112bfee95bbSGrant Likely ranges = < 0 0 0xfc000000 0x02000000 113bfee95bbSGrant Likely 1 0 0xfe000000 0x02000000 114bfee95bbSGrant Likely 2 0 0xf0010000 0x00010000 115bfee95bbSGrant Likely 3 0 0xf0020000 0x00010000 >; 116bfee95bbSGrant Likely flash@0,0 { 117bfee95bbSGrant Likely compatible = "amd,am29lv28ml", "cfi-flash"; 118bfee95bbSGrant Likely reg = <0 0x0 0x2000000>; // 32 MB 119bfee95bbSGrant Likely bank-width = <4>; // Width in bytes of the flash bank 120bfee95bbSGrant Likely device-width = <2>; // Two devices on each bank 121bfee95bbSGrant Likely }; 122bfee95bbSGrant Likely 123bfee95bbSGrant Likely flash@1,0 { 124bfee95bbSGrant Likely compatible = "amd,am29lv28ml", "cfi-flash"; 125bfee95bbSGrant Likely reg = <1 0 0x2000000>; // 32 MB 126bfee95bbSGrant Likely bank-width = <4>; // Width in bytes of the flash bank 127bfee95bbSGrant Likely device-width = <2>; // Two devices on each bank 128bfee95bbSGrant Likely }; 129bfee95bbSGrant Likely 130bfee95bbSGrant Likely media5200_fpga: fpga@2,0 { 131bfee95bbSGrant Likely compatible = "fsl,media5200-fpga"; 132bfee95bbSGrant Likely interrupt-controller; 133bfee95bbSGrant Likely #interrupt-cells = <2>; // 0:bank 1:id; no type field 134bfee95bbSGrant Likely reg = <2 0 0x10000>; 135bfee95bbSGrant Likely 136bfee95bbSGrant Likely interrupt-parent = <&mpc5200_pic>; 137bfee95bbSGrant Likely interrupts = <0 0 3 // IRQ bank 0 138bfee95bbSGrant Likely 1 1 3>; // IRQ bank 1 139bfee95bbSGrant Likely }; 140bfee95bbSGrant Likely 141bfee95bbSGrant Likely uart@3,0 { 142bfee95bbSGrant Likely compatible = "ti,tl16c752bpt"; 143bfee95bbSGrant Likely reg = <3 0 0x10000>; 144bfee95bbSGrant Likely interrupt-parent = <&media5200_fpga>; 145bfee95bbSGrant Likely interrupts = <0 0 0 1>; // 2 irqs 146bfee95bbSGrant Likely }; 147bfee95bbSGrant Likely }; 148bfee95bbSGrant Likely}; 149