12874c5fdSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-or-later
2bfee95bbSGrant Likely/*
3bfee95bbSGrant Likely * Freescale Media5200 board Device Tree Source
4bfee95bbSGrant Likely *
5bfee95bbSGrant Likely * Copyright 2009 Secret Lab Technologies Ltd.
6bfee95bbSGrant Likely * Grant Likely <grant.likely@secretlab.ca>
7bfee95bbSGrant Likely * Steven Cavanagh <scavanagh@secretlab.ca>
8bfee95bbSGrant Likely */
9bfee95bbSGrant Likely
10c8bf6b52SJohn Bonesio/include/ "mpc5200b.dtsi"
11bfee95bbSGrant Likely
12fa59f178SGrant Likely&gpt0 { fsl,has-wdt; };
13fa59f178SGrant Likely
14bfee95bbSGrant Likely/ {
15bfee95bbSGrant Likely	model = "fsl,media5200";
16bfee95bbSGrant Likely	compatible = "fsl,media5200";
17bfee95bbSGrant Likely
18bfee95bbSGrant Likely	aliases {
19bfee95bbSGrant Likely		console = &console;
20bfee95bbSGrant Likely		ethernet0 = &eth0;
21bfee95bbSGrant Likely	};
22bfee95bbSGrant Likely
23bfee95bbSGrant Likely	chosen {
2478e5dfeaSRob Herring		stdout-path = &console;
25bfee95bbSGrant Likely	};
26bfee95bbSGrant Likely
27bfee95bbSGrant Likely	cpus {
28bfee95bbSGrant Likely		PowerPC,5200@0 {
29bfee95bbSGrant Likely			timebase-frequency = <33000000>;	// 33 MHz, these were configured by U-Boot
30bfee95bbSGrant Likely			bus-frequency = <132000000>;		// 132 MHz
31bfee95bbSGrant Likely			clock-frequency = <396000000>;		// 396 MHz
32bfee95bbSGrant Likely		};
33bfee95bbSGrant Likely	};
34bfee95bbSGrant Likely
35*aed2886aSAnatolij Gustschin	memory@0 {
36bfee95bbSGrant Likely		reg = <0x00000000 0x08000000>;	// 128MB RAM
37bfee95bbSGrant Likely	};
38bfee95bbSGrant Likely
39c8bf6b52SJohn Bonesio	soc5200@f0000000 {
40bfee95bbSGrant Likely		bus-frequency = <132000000>;// 132 MHz
41bfee95bbSGrant Likely
42c8bf6b52SJohn Bonesio		psc@2000 {	// PSC1
43c8bf6b52SJohn Bonesio			status = "disabled";
44bfee95bbSGrant Likely		};
45bfee95bbSGrant Likely
46c8bf6b52SJohn Bonesio		psc@2200 {	// PSC2
47c8bf6b52SJohn Bonesio			status = "disabled";
48bfee95bbSGrant Likely		};
49bfee95bbSGrant Likely
50c8bf6b52SJohn Bonesio		psc@2400 {	// PSC3
51c8bf6b52SJohn Bonesio			status = "disabled";
52bfee95bbSGrant Likely		};
53bfee95bbSGrant Likely
54c8bf6b52SJohn Bonesio		psc@2600 {	// PSC4
55c8bf6b52SJohn Bonesio			status = "disabled";
56bfee95bbSGrant Likely		};
57bfee95bbSGrant Likely
58c8bf6b52SJohn Bonesio		psc@2800 {	// PSC5
59c8bf6b52SJohn Bonesio			status = "disabled";
60bfee95bbSGrant Likely		};
61bfee95bbSGrant Likely
62bfee95bbSGrant Likely		// PSC6 in uart mode
63abf1e27fSJohn Bonesio		console: psc@2c00 {		// PSC6
64bfee95bbSGrant Likely			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
65bfee95bbSGrant Likely		};
66bfee95bbSGrant Likely
67c8bf6b52SJohn Bonesio		ethernet@3000 {
68bfee95bbSGrant Likely			phy-handle = <&phy0>;
69bfee95bbSGrant Likely		};
70bfee95bbSGrant Likely
71bfee95bbSGrant Likely		mdio@3000 {
72bfee95bbSGrant Likely			phy0: ethernet-phy@0 {
73bfee95bbSGrant Likely				reg = <0>;
74bfee95bbSGrant Likely			};
75bfee95bbSGrant Likely		};
76bfee95bbSGrant Likely
77c8bf6b52SJohn Bonesio		usb@1000 {
78c8bf6b52SJohn Bonesio			reg = <0x1000 0x100>;
79bfee95bbSGrant Likely		};
80bfee95bbSGrant Likely	};
81bfee95bbSGrant Likely
82bfee95bbSGrant Likely	pci@f0000d00 {
83bfee95bbSGrant Likely		interrupt-map-mask = <0xf800 0 0 7>;
84bfee95bbSGrant Likely		interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
85bfee95bbSGrant Likely				 0xc000 0 0 2 &media5200_fpga 0 3
86bfee95bbSGrant Likely				 0xc000 0 0 3 &media5200_fpga 0 4
87bfee95bbSGrant Likely				 0xc000 0 0 4 &media5200_fpga 0 5
88bfee95bbSGrant Likely
89bfee95bbSGrant Likely				 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
90bfee95bbSGrant Likely				 0xc800 0 0 2 &media5200_fpga 0 4
91bfee95bbSGrant Likely				 0xc800 0 0 3 &media5200_fpga 0 5
92bfee95bbSGrant Likely				 0xc800 0 0 4 &media5200_fpga 0 2
93bfee95bbSGrant Likely
94bfee95bbSGrant Likely				 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
95bfee95bbSGrant Likely				 0xd000 0 0 2 &media5200_fpga 0 5
96bfee95bbSGrant Likely
97bfee95bbSGrant Likely				 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
98bfee95bbSGrant Likely				>;
997855b6c6SAnatolij Gustschin		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000>,
1007855b6c6SAnatolij Gustschin			 <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>,
1017855b6c6SAnatolij Gustschin			 <0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
102c8bf6b52SJohn Bonesio		interrupt-parent = <&mpc5200_pic>;
103bfee95bbSGrant Likely	};
104bfee95bbSGrant Likely
105bfee95bbSGrant Likely	localbus {
106bfee95bbSGrant Likely		ranges = < 0 0 0xfc000000 0x02000000
107bfee95bbSGrant Likely			   1 0 0xfe000000 0x02000000
108bfee95bbSGrant Likely			   2 0 0xf0010000 0x00010000
109bfee95bbSGrant Likely			   3 0 0xf0020000 0x00010000 >;
110bfee95bbSGrant Likely		flash@0,0 {
111bfee95bbSGrant Likely			compatible = "amd,am29lv28ml", "cfi-flash";
112bfee95bbSGrant Likely			reg = <0 0x0 0x2000000>;                // 32 MB
113bfee95bbSGrant Likely			bank-width = <4>;                       // Width in bytes of the flash bank
114bfee95bbSGrant Likely			device-width = <2>;                     // Two devices on each bank
115bfee95bbSGrant Likely		};
116bfee95bbSGrant Likely
117bfee95bbSGrant Likely		flash@1,0 {
118bfee95bbSGrant Likely			compatible = "amd,am29lv28ml", "cfi-flash";
119bfee95bbSGrant Likely			reg = <1 0 0x2000000>;                  // 32 MB
120bfee95bbSGrant Likely			bank-width = <4>;                       // Width in bytes of the flash bank
121bfee95bbSGrant Likely			device-width = <2>;                     // Two devices on each bank
122bfee95bbSGrant Likely		};
123bfee95bbSGrant Likely
124bfee95bbSGrant Likely		media5200_fpga: fpga@2,0 {
125bfee95bbSGrant Likely			compatible = "fsl,media5200-fpga";
126bfee95bbSGrant Likely			interrupt-controller;
127bfee95bbSGrant Likely			#interrupt-cells = <2>;	// 0:bank 1:id; no type field
128bfee95bbSGrant Likely			reg = <2 0 0x10000>;
129bfee95bbSGrant Likely
130bfee95bbSGrant Likely			interrupt-parent = <&mpc5200_pic>;
131bfee95bbSGrant Likely			interrupts = <0 0 3	// IRQ bank 0
132bfee95bbSGrant Likely			              1 1 3>;	// IRQ bank 1
133bfee95bbSGrant Likely		};
134bfee95bbSGrant Likely
135bfee95bbSGrant Likely		uart@3,0 {
136bfee95bbSGrant Likely			compatible = "ti,tl16c752bpt";
137bfee95bbSGrant Likely			reg = <3 0 0x10000>;
138bfee95bbSGrant Likely			interrupt-parent = <&media5200_fpga>;
139bfee95bbSGrant Likely			interrupts = <0 0  0 1>; // 2 irqs
140bfee95bbSGrant Likely		};
141bfee95bbSGrant Likely	};
142bfee95bbSGrant Likely};
143