11b55883aSStefan Roese/* 21b55883aSStefan Roese * Device Tree Source for AMCC Makalu (405EX) 31b55883aSStefan Roese * 41b55883aSStefan Roese * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> 51b55883aSStefan Roese * 61b55883aSStefan Roese * This file is licensed under the terms of the GNU General Public 71b55883aSStefan Roese * License version 2. This program is licensed "as is" without 81b55883aSStefan Roese * any warranty of any kind, whether express or implied. 91b55883aSStefan Roese */ 101b55883aSStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 131b55883aSStefan Roese/ { 141b55883aSStefan Roese #address-cells = <1>; 151b55883aSStefan Roese #size-cells = <1>; 161b55883aSStefan Roese model = "amcc,makalu"; 171b55883aSStefan Roese compatible = "amcc,makalu"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 191b55883aSStefan Roese 201b55883aSStefan Roese aliases { 211b55883aSStefan Roese ethernet0 = &EMAC0; 221b55883aSStefan Roese ethernet1 = &EMAC1; 231b55883aSStefan Roese serial0 = &UART0; 241b55883aSStefan Roese serial1 = &UART1; 251b55883aSStefan Roese }; 261b55883aSStefan Roese 271b55883aSStefan Roese cpus { 281b55883aSStefan Roese #address-cells = <1>; 291b55883aSStefan Roese #size-cells = <0>; 301b55883aSStefan Roese 311b55883aSStefan Roese cpu@0 { 321b55883aSStefan Roese device_type = "cpu"; 331b55883aSStefan Roese model = "PowerPC,405EX"; 3471f34979SDavid Gibson reg = <0x00000000>; 351b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 361b55883aSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3771f34979SDavid Gibson i-cache-line-size = <32>; 3871f34979SDavid Gibson d-cache-line-size = <32>; 3971f34979SDavid Gibson i-cache-size = <16384>; /* 16 kB */ 4071f34979SDavid Gibson d-cache-size = <16384>; /* 16 kB */ 411b55883aSStefan Roese dcr-controller; 421b55883aSStefan Roese dcr-access-method = "native"; 431b55883aSStefan Roese }; 441b55883aSStefan Roese }; 451b55883aSStefan Roese 461b55883aSStefan Roese memory { 471b55883aSStefan Roese device_type = "memory"; 4871f34979SDavid Gibson reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ 491b55883aSStefan Roese }; 501b55883aSStefan Roese 511b55883aSStefan Roese UIC0: interrupt-controller { 521b55883aSStefan Roese compatible = "ibm,uic-405ex", "ibm,uic"; 531b55883aSStefan Roese interrupt-controller; 541b55883aSStefan Roese cell-index = <0>; 5571f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 561b55883aSStefan Roese #address-cells = <0>; 571b55883aSStefan Roese #size-cells = <0>; 581b55883aSStefan Roese #interrupt-cells = <2>; 591b55883aSStefan Roese }; 601b55883aSStefan Roese 611b55883aSStefan Roese UIC1: interrupt-controller1 { 621b55883aSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 631b55883aSStefan Roese interrupt-controller; 641b55883aSStefan Roese cell-index = <1>; 6571f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 661b55883aSStefan Roese #address-cells = <0>; 671b55883aSStefan Roese #size-cells = <0>; 681b55883aSStefan Roese #interrupt-cells = <2>; 6971f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 701b55883aSStefan Roese interrupt-parent = <&UIC0>; 711b55883aSStefan Roese }; 721b55883aSStefan Roese 731b55883aSStefan Roese UIC2: interrupt-controller2 { 741b55883aSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 751b55883aSStefan Roese interrupt-controller; 761b55883aSStefan Roese cell-index = <2>; 7771f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 781b55883aSStefan Roese #address-cells = <0>; 791b55883aSStefan Roese #size-cells = <0>; 801b55883aSStefan Roese #interrupt-cells = <2>; 8171f34979SDavid Gibson interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ 821b55883aSStefan Roese interrupt-parent = <&UIC0>; 831b55883aSStefan Roese }; 841b55883aSStefan Roese 851b55883aSStefan Roese plb { 861b55883aSStefan Roese compatible = "ibm,plb-405ex", "ibm,plb4"; 871b55883aSStefan Roese #address-cells = <1>; 881b55883aSStefan Roese #size-cells = <1>; 891b55883aSStefan Roese ranges; 901b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 911b55883aSStefan Roese 921b55883aSStefan Roese SDRAM0: memory-controller { 931b55883aSStefan Roese compatible = "ibm,sdram-405ex"; 9471f34979SDavid Gibson dcr-reg = <0x010 0x002>; 951b55883aSStefan Roese }; 961b55883aSStefan Roese 971b55883aSStefan Roese MAL0: mcmal { 981b55883aSStefan Roese compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 9971f34979SDavid Gibson dcr-reg = <0x180 0x062>; 1001b55883aSStefan Roese num-tx-chans = <2>; 1011b55883aSStefan Roese num-rx-chans = <2>; 1021b55883aSStefan Roese interrupt-parent = <&MAL0>; 10371f34979SDavid Gibson interrupts = <0x0 0x1 0x2 0x3 0x4>; 1041b55883aSStefan Roese #interrupt-cells = <1>; 1051b55883aSStefan Roese #address-cells = <0>; 1061b55883aSStefan Roese #size-cells = <0>; 10771f34979SDavid Gibson interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 10871f34979SDavid Gibson /*RXEOB*/ 0x1 &UIC0 0xb 0x4 10971f34979SDavid Gibson /*SERR*/ 0x2 &UIC1 0x0 0x4 11071f34979SDavid Gibson /*TXDE*/ 0x3 &UIC1 0x1 0x4 11171f34979SDavid Gibson /*RXDE*/ 0x4 &UIC1 0x2 0x4>; 11271f34979SDavid Gibson interrupt-map-mask = <0xffffffff>; 1131b55883aSStefan Roese }; 1141b55883aSStefan Roese 1151b55883aSStefan Roese POB0: opb { 1161b55883aSStefan Roese compatible = "ibm,opb-405ex", "ibm,opb"; 1171b55883aSStefan Roese #address-cells = <1>; 1181b55883aSStefan Roese #size-cells = <1>; 11971f34979SDavid Gibson ranges = <0x80000000 0x80000000 0x10000000 12071f34979SDavid Gibson 0xef600000 0xef600000 0x00a00000 12171f34979SDavid Gibson 0xf0000000 0xf0000000 0x10000000>; 12271f34979SDavid Gibson dcr-reg = <0x0a0 0x005>; 1231b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1241b55883aSStefan Roese 1251b55883aSStefan Roese EBC0: ebc { 1261b55883aSStefan Roese compatible = "ibm,ebc-405ex", "ibm,ebc"; 12771f34979SDavid Gibson dcr-reg = <0x012 0x002>; 1281b55883aSStefan Roese #address-cells = <2>; 1291b55883aSStefan Roese #size-cells = <1>; 1301b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1311b55883aSStefan Roese /* ranges property is supplied by U-Boot */ 13271f34979SDavid Gibson interrupts = <0x5 0x1>; 1331b55883aSStefan Roese interrupt-parent = <&UIC1>; 1341b55883aSStefan Roese 1351b55883aSStefan Roese nor_flash@0,0 { 1361b55883aSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 1371b55883aSStefan Roese bank-width = <2>; 13871f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 1391b55883aSStefan Roese #address-cells = <1>; 1401b55883aSStefan Roese #size-cells = <1>; 1411b55883aSStefan Roese partition@0 { 1421b55883aSStefan Roese label = "kernel"; 14371f34979SDavid Gibson reg = <0x00000000 0x00200000>; 1441b55883aSStefan Roese }; 1451b55883aSStefan Roese partition@200000 { 1461b55883aSStefan Roese label = "root"; 14771f34979SDavid Gibson reg = <0x00200000 0x00200000>; 1481b55883aSStefan Roese }; 1491b55883aSStefan Roese partition@400000 { 1501b55883aSStefan Roese label = "user"; 15171f34979SDavid Gibson reg = <0x00400000 0x03b60000>; 1521b55883aSStefan Roese }; 1531b55883aSStefan Roese partition@3f60000 { 1541b55883aSStefan Roese label = "env"; 15571f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 1561b55883aSStefan Roese }; 1571b55883aSStefan Roese partition@3fa0000 { 1581b55883aSStefan Roese label = "u-boot"; 15971f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 1601b55883aSStefan Roese }; 1611b55883aSStefan Roese }; 1621b55883aSStefan Roese }; 1631b55883aSStefan Roese 1641b55883aSStefan Roese UART0: serial@ef600200 { 1651b55883aSStefan Roese device_type = "serial"; 1661b55883aSStefan Roese compatible = "ns16550"; 16771f34979SDavid Gibson reg = <0xef600200 0x00000008>; 16871f34979SDavid Gibson virtual-reg = <0xef600200>; 1691b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1701b55883aSStefan Roese current-speed = <0>; 1711b55883aSStefan Roese interrupt-parent = <&UIC0>; 17271f34979SDavid Gibson interrupts = <0x1a 0x4>; 1731b55883aSStefan Roese }; 1741b55883aSStefan Roese 1751b55883aSStefan Roese UART1: serial@ef600300 { 1761b55883aSStefan Roese device_type = "serial"; 1771b55883aSStefan Roese compatible = "ns16550"; 17871f34979SDavid Gibson reg = <0xef600300 0x00000008>; 17971f34979SDavid Gibson virtual-reg = <0xef600300>; 1801b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1811b55883aSStefan Roese current-speed = <0>; 1821b55883aSStefan Roese interrupt-parent = <&UIC0>; 18371f34979SDavid Gibson interrupts = <0x1 0x4>; 1841b55883aSStefan Roese }; 1851b55883aSStefan Roese 1861b55883aSStefan Roese IIC0: i2c@ef600400 { 1871b55883aSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 18871f34979SDavid Gibson reg = <0xef600400 0x00000014>; 1891b55883aSStefan Roese interrupt-parent = <&UIC0>; 19071f34979SDavid Gibson interrupts = <0x2 0x4>; 1911b55883aSStefan Roese }; 1921b55883aSStefan Roese 1931b55883aSStefan Roese IIC1: i2c@ef600500 { 1941b55883aSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 19571f34979SDavid Gibson reg = <0xef600500 0x00000014>; 1961b55883aSStefan Roese interrupt-parent = <&UIC0>; 19771f34979SDavid Gibson interrupts = <0x7 0x4>; 1981b55883aSStefan Roese }; 1991b55883aSStefan Roese 2001b55883aSStefan Roese 2011b55883aSStefan Roese RGMII0: emac-rgmii@ef600b00 { 2021b55883aSStefan Roese compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 20371f34979SDavid Gibson reg = <0xef600b00 0x00000104>; 2041b55883aSStefan Roese has-mdio; 2051b55883aSStefan Roese }; 2061b55883aSStefan Roese 2071b55883aSStefan Roese EMAC0: ethernet@ef600900 { 20871f34979SDavid Gibson linux,network-index = <0x0>; 2091b55883aSStefan Roese device_type = "network"; 2101b55883aSStefan Roese compatible = "ibm,emac-405ex", "ibm,emac4"; 2111b55883aSStefan Roese interrupt-parent = <&EMAC0>; 21271f34979SDavid Gibson interrupts = <0x0 0x1>; 2131b55883aSStefan Roese #interrupt-cells = <1>; 2141b55883aSStefan Roese #address-cells = <0>; 2151b55883aSStefan Roese #size-cells = <0>; 21671f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 21771f34979SDavid Gibson /*Wake*/ 0x1 &UIC1 0x1d 0x4>; 21871f34979SDavid Gibson reg = <0xef600900 0x00000070>; 2191b55883aSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 2201b55883aSStefan Roese mal-device = <&MAL0>; 2211b55883aSStefan Roese mal-tx-channel = <0>; 2221b55883aSStefan Roese mal-rx-channel = <0>; 2231b55883aSStefan Roese cell-index = <0>; 22471f34979SDavid Gibson max-frame-size = <9000>; 22571f34979SDavid Gibson rx-fifo-size = <4096>; 22671f34979SDavid Gibson tx-fifo-size = <2048>; 2271b55883aSStefan Roese phy-mode = "rgmii"; 22871f34979SDavid Gibson phy-map = <0x0000003f>; /* Start at 6 */ 2291b55883aSStefan Roese rgmii-device = <&RGMII0>; 2301b55883aSStefan Roese rgmii-channel = <0>; 2311b55883aSStefan Roese has-inverted-stacr-oc; 2321b55883aSStefan Roese has-new-stacr-staopc; 2331b55883aSStefan Roese }; 2341b55883aSStefan Roese 2351b55883aSStefan Roese EMAC1: ethernet@ef600a00 { 23671f34979SDavid Gibson linux,network-index = <0x1>; 2371b55883aSStefan Roese device_type = "network"; 2381b55883aSStefan Roese compatible = "ibm,emac-405ex", "ibm,emac4"; 2391b55883aSStefan Roese interrupt-parent = <&EMAC1>; 24071f34979SDavid Gibson interrupts = <0x0 0x1>; 2411b55883aSStefan Roese #interrupt-cells = <1>; 2421b55883aSStefan Roese #address-cells = <0>; 2431b55883aSStefan Roese #size-cells = <0>; 24471f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4 24571f34979SDavid Gibson /*Wake*/ 0x1 &UIC1 0x1f 0x4>; 24671f34979SDavid Gibson reg = <0xef600a00 0x00000070>; 2471b55883aSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 2481b55883aSStefan Roese mal-device = <&MAL0>; 2491b55883aSStefan Roese mal-tx-channel = <1>; 2501b55883aSStefan Roese mal-rx-channel = <1>; 2511b55883aSStefan Roese cell-index = <1>; 25271f34979SDavid Gibson max-frame-size = <9000>; 25371f34979SDavid Gibson rx-fifo-size = <4096>; 25471f34979SDavid Gibson tx-fifo-size = <2048>; 2551b55883aSStefan Roese phy-mode = "rgmii"; 25671f34979SDavid Gibson phy-map = <0x00000000>; 2571b55883aSStefan Roese rgmii-device = <&RGMII0>; 2581b55883aSStefan Roese rgmii-channel = <1>; 2591b55883aSStefan Roese has-inverted-stacr-oc; 2601b55883aSStefan Roese has-new-stacr-staopc; 2611b55883aSStefan Roese }; 2621b55883aSStefan Roese }; 2631b55883aSStefan Roese 2641b55883aSStefan Roese PCIE0: pciex@0a0000000 { 2651b55883aSStefan Roese device_type = "pci"; 2661b55883aSStefan Roese #interrupt-cells = <1>; 2671b55883aSStefan Roese #size-cells = <2>; 2681b55883aSStefan Roese #address-cells = <3>; 2691b55883aSStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 2701b55883aSStefan Roese primary; 27171f34979SDavid Gibson port = <0x0>; /* port number */ 27271f34979SDavid Gibson reg = <0xa0000000 0x20000000 /* Config space access */ 27371f34979SDavid Gibson 0xef000000 0x00001000>; /* Registers */ 27471f34979SDavid Gibson dcr-reg = <0x040 0x020>; 27571f34979SDavid Gibson sdr-base = <0x400>; 2761b55883aSStefan Roese 2771b55883aSStefan Roese /* Outbound ranges, one memory and one IO, 2781b55883aSStefan Roese * later cannot be changed 2791b55883aSStefan Roese */ 28071f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 28171f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; 2821b55883aSStefan Roese 2831b55883aSStefan Roese /* Inbound 2GB range starting at 0 */ 28471f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 2851b55883aSStefan Roese 2861b55883aSStefan Roese /* This drives busses 0x00 to 0x3f */ 28771f34979SDavid Gibson bus-range = <0x0 0x3f>; 2881b55883aSStefan Roese 2891b55883aSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 2901b55883aSStefan Roese * to invert PCIe legacy interrupts). 2911b55883aSStefan Roese * We are de-swizzling here because the numbers are actually for 2921b55883aSStefan Roese * port of the root complex virtual P2P bridge. But I want 2931b55883aSStefan Roese * to avoid putting a node for it in the tree, so the numbers 2941b55883aSStefan Roese * below are basically de-swizzled numbers. 2951b55883aSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 2961b55883aSStefan Roese */ 29771f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 2981b55883aSStefan Roese interrupt-map = < 29971f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ 30071f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ 30171f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ 30271f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; 3031b55883aSStefan Roese }; 3041b55883aSStefan Roese 3051b55883aSStefan Roese PCIE1: pciex@0c0000000 { 3061b55883aSStefan Roese device_type = "pci"; 3071b55883aSStefan Roese #interrupt-cells = <1>; 3081b55883aSStefan Roese #size-cells = <2>; 3091b55883aSStefan Roese #address-cells = <3>; 3101b55883aSStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 3111b55883aSStefan Roese primary; 31271f34979SDavid Gibson port = <0x1>; /* port number */ 31371f34979SDavid Gibson reg = <0xc0000000 0x20000000 /* Config space access */ 31471f34979SDavid Gibson 0xef001000 0x00001000>; /* Registers */ 31571f34979SDavid Gibson dcr-reg = <0x060 0x020>; 31671f34979SDavid Gibson sdr-base = <0x440>; 3171b55883aSStefan Roese 3181b55883aSStefan Roese /* Outbound ranges, one memory and one IO, 3191b55883aSStefan Roese * later cannot be changed 3201b55883aSStefan Roese */ 32171f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 32271f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; 3231b55883aSStefan Roese 3241b55883aSStefan Roese /* Inbound 2GB range starting at 0 */ 32571f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 3261b55883aSStefan Roese 3271b55883aSStefan Roese /* This drives busses 0x40 to 0x7f */ 32871f34979SDavid Gibson bus-range = <0x40 0x7f>; 3291b55883aSStefan Roese 3301b55883aSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 3311b55883aSStefan Roese * to invert PCIe legacy interrupts). 3321b55883aSStefan Roese * We are de-swizzling here because the numbers are actually for 3331b55883aSStefan Roese * port of the root complex virtual P2P bridge. But I want 3341b55883aSStefan Roese * to avoid putting a node for it in the tree, so the numbers 3351b55883aSStefan Roese * below are basically de-swizzled numbers. 3361b55883aSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 3371b55883aSStefan Roese */ 33871f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 3391b55883aSStefan Roese interrupt-map = < 34071f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ 34171f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ 34271f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ 34371f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; 3441b55883aSStefan Roese }; 3451b55883aSStefan Roese }; 3461b55883aSStefan Roese}; 347