11b55883aSStefan Roese/* 21b55883aSStefan Roese * Device Tree Source for AMCC Makalu (405EX) 31b55883aSStefan Roese * 41b55883aSStefan Roese * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> 51b55883aSStefan Roese * 61b55883aSStefan Roese * This file is licensed under the terms of the GNU General Public 71b55883aSStefan Roese * License version 2. This program is licensed "as is" without 81b55883aSStefan Roese * any warranty of any kind, whether express or implied. 91b55883aSStefan Roese */ 101b55883aSStefan Roese 111b55883aSStefan Roese/ { 121b55883aSStefan Roese #address-cells = <1>; 131b55883aSStefan Roese #size-cells = <1>; 141b55883aSStefan Roese model = "amcc,makalu"; 151b55883aSStefan Roese compatible = "amcc,makalu"; 161b55883aSStefan Roese dcr-parent = <&/cpus/cpu@0>; 171b55883aSStefan Roese 181b55883aSStefan Roese aliases { 191b55883aSStefan Roese ethernet0 = &EMAC0; 201b55883aSStefan Roese ethernet1 = &EMAC1; 211b55883aSStefan Roese serial0 = &UART0; 221b55883aSStefan Roese serial1 = &UART1; 231b55883aSStefan Roese }; 241b55883aSStefan Roese 251b55883aSStefan Roese cpus { 261b55883aSStefan Roese #address-cells = <1>; 271b55883aSStefan Roese #size-cells = <0>; 281b55883aSStefan Roese 291b55883aSStefan Roese cpu@0 { 301b55883aSStefan Roese device_type = "cpu"; 311b55883aSStefan Roese model = "PowerPC,405EX"; 321b55883aSStefan Roese reg = <0>; 331b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 341b55883aSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 351b55883aSStefan Roese i-cache-line-size = <20>; 361b55883aSStefan Roese d-cache-line-size = <20>; 371b55883aSStefan Roese i-cache-size = <4000>; /* 16 kB */ 381b55883aSStefan Roese d-cache-size = <4000>; /* 16 kB */ 391b55883aSStefan Roese dcr-controller; 401b55883aSStefan Roese dcr-access-method = "native"; 411b55883aSStefan Roese }; 421b55883aSStefan Roese }; 431b55883aSStefan Roese 441b55883aSStefan Roese memory { 451b55883aSStefan Roese device_type = "memory"; 461b55883aSStefan Roese reg = <0 0>; /* Filled in by U-Boot */ 471b55883aSStefan Roese }; 481b55883aSStefan Roese 491b55883aSStefan Roese UIC0: interrupt-controller { 501b55883aSStefan Roese compatible = "ibm,uic-405ex", "ibm,uic"; 511b55883aSStefan Roese interrupt-controller; 521b55883aSStefan Roese cell-index = <0>; 531b55883aSStefan Roese dcr-reg = <0c0 009>; 541b55883aSStefan Roese #address-cells = <0>; 551b55883aSStefan Roese #size-cells = <0>; 561b55883aSStefan Roese #interrupt-cells = <2>; 571b55883aSStefan Roese }; 581b55883aSStefan Roese 591b55883aSStefan Roese UIC1: interrupt-controller1 { 601b55883aSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 611b55883aSStefan Roese interrupt-controller; 621b55883aSStefan Roese cell-index = <1>; 631b55883aSStefan Roese dcr-reg = <0d0 009>; 641b55883aSStefan Roese #address-cells = <0>; 651b55883aSStefan Roese #size-cells = <0>; 661b55883aSStefan Roese #interrupt-cells = <2>; 671b55883aSStefan Roese interrupts = <1e 4 1f 4>; /* cascade */ 681b55883aSStefan Roese interrupt-parent = <&UIC0>; 691b55883aSStefan Roese }; 701b55883aSStefan Roese 711b55883aSStefan Roese UIC2: interrupt-controller2 { 721b55883aSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 731b55883aSStefan Roese interrupt-controller; 741b55883aSStefan Roese cell-index = <2>; 751b55883aSStefan Roese dcr-reg = <0e0 009>; 761b55883aSStefan Roese #address-cells = <0>; 771b55883aSStefan Roese #size-cells = <0>; 781b55883aSStefan Roese #interrupt-cells = <2>; 791b55883aSStefan Roese interrupts = <1c 4 1d 4>; /* cascade */ 801b55883aSStefan Roese interrupt-parent = <&UIC0>; 811b55883aSStefan Roese }; 821b55883aSStefan Roese 831b55883aSStefan Roese plb { 841b55883aSStefan Roese compatible = "ibm,plb-405ex", "ibm,plb4"; 851b55883aSStefan Roese #address-cells = <1>; 861b55883aSStefan Roese #size-cells = <1>; 871b55883aSStefan Roese ranges; 881b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 891b55883aSStefan Roese 901b55883aSStefan Roese SDRAM0: memory-controller { 911b55883aSStefan Roese compatible = "ibm,sdram-405ex"; 921b55883aSStefan Roese dcr-reg = <010 2>; 931b55883aSStefan Roese }; 941b55883aSStefan Roese 951b55883aSStefan Roese MAL0: mcmal { 961b55883aSStefan Roese compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 971b55883aSStefan Roese dcr-reg = <180 62>; 981b55883aSStefan Roese num-tx-chans = <2>; 991b55883aSStefan Roese num-rx-chans = <2>; 1001b55883aSStefan Roese interrupt-parent = <&MAL0>; 1011b55883aSStefan Roese interrupts = <0 1 2 3 4>; 1021b55883aSStefan Roese #interrupt-cells = <1>; 1031b55883aSStefan Roese #address-cells = <0>; 1041b55883aSStefan Roese #size-cells = <0>; 1051b55883aSStefan Roese interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 1061b55883aSStefan Roese /*RXEOB*/ 1 &UIC0 b 4 1071b55883aSStefan Roese /*SERR*/ 2 &UIC1 0 4 1081b55883aSStefan Roese /*TXDE*/ 3 &UIC1 1 4 1091b55883aSStefan Roese /*RXDE*/ 4 &UIC1 2 4>; 1101b55883aSStefan Roese interrupt-map-mask = <ffffffff>; 1111b55883aSStefan Roese }; 1121b55883aSStefan Roese 1131b55883aSStefan Roese POB0: opb { 1141b55883aSStefan Roese compatible = "ibm,opb-405ex", "ibm,opb"; 1151b55883aSStefan Roese #address-cells = <1>; 1161b55883aSStefan Roese #size-cells = <1>; 1171b55883aSStefan Roese ranges = <80000000 80000000 10000000 1181b55883aSStefan Roese ef600000 ef600000 a00000 1191b55883aSStefan Roese f0000000 f0000000 10000000>; 1201b55883aSStefan Roese dcr-reg = <0a0 5>; 1211b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1221b55883aSStefan Roese 1231b55883aSStefan Roese EBC0: ebc { 1241b55883aSStefan Roese compatible = "ibm,ebc-405ex", "ibm,ebc"; 1251b55883aSStefan Roese dcr-reg = <012 2>; 1261b55883aSStefan Roese #address-cells = <2>; 1271b55883aSStefan Roese #size-cells = <1>; 1281b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1291b55883aSStefan Roese /* ranges property is supplied by U-Boot */ 1301b55883aSStefan Roese interrupts = <5 1>; 1311b55883aSStefan Roese interrupt-parent = <&UIC1>; 1321b55883aSStefan Roese 1331b55883aSStefan Roese nor_flash@0,0 { 1341b55883aSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 1351b55883aSStefan Roese bank-width = <2>; 1361b55883aSStefan Roese reg = <0 000000 4000000>; 1371b55883aSStefan Roese #address-cells = <1>; 1381b55883aSStefan Roese #size-cells = <1>; 1391b55883aSStefan Roese partition@0 { 1401b55883aSStefan Roese label = "kernel"; 1411b55883aSStefan Roese reg = <0 200000>; 1421b55883aSStefan Roese }; 1431b55883aSStefan Roese partition@200000 { 1441b55883aSStefan Roese label = "root"; 1451b55883aSStefan Roese reg = <200000 200000>; 1461b55883aSStefan Roese }; 1471b55883aSStefan Roese partition@400000 { 1481b55883aSStefan Roese label = "user"; 1491b55883aSStefan Roese reg = <400000 3b60000>; 1501b55883aSStefan Roese }; 1511b55883aSStefan Roese partition@3f60000 { 1521b55883aSStefan Roese label = "env"; 1531b55883aSStefan Roese reg = <3f60000 40000>; 1541b55883aSStefan Roese }; 1551b55883aSStefan Roese partition@3fa0000 { 1561b55883aSStefan Roese label = "u-boot"; 1571b55883aSStefan Roese reg = <3fa0000 60000>; 1581b55883aSStefan Roese }; 1591b55883aSStefan Roese }; 1601b55883aSStefan Roese }; 1611b55883aSStefan Roese 1621b55883aSStefan Roese UART0: serial@ef600200 { 1631b55883aSStefan Roese device_type = "serial"; 1641b55883aSStefan Roese compatible = "ns16550"; 1651b55883aSStefan Roese reg = <ef600200 8>; 1661b55883aSStefan Roese virtual-reg = <ef600200>; 1671b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1681b55883aSStefan Roese current-speed = <0>; 1691b55883aSStefan Roese interrupt-parent = <&UIC0>; 1701b55883aSStefan Roese interrupts = <1a 4>; 1711b55883aSStefan Roese }; 1721b55883aSStefan Roese 1731b55883aSStefan Roese UART1: serial@ef600300 { 1741b55883aSStefan Roese device_type = "serial"; 1751b55883aSStefan Roese compatible = "ns16550"; 1761b55883aSStefan Roese reg = <ef600300 8>; 1771b55883aSStefan Roese virtual-reg = <ef600300>; 1781b55883aSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1791b55883aSStefan Roese current-speed = <0>; 1801b55883aSStefan Roese interrupt-parent = <&UIC0>; 1811b55883aSStefan Roese interrupts = <1 4>; 1821b55883aSStefan Roese }; 1831b55883aSStefan Roese 1841b55883aSStefan Roese IIC0: i2c@ef600400 { 1851b55883aSStefan Roese device_type = "i2c"; 1861b55883aSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 1871b55883aSStefan Roese reg = <ef600400 14>; 1881b55883aSStefan Roese interrupt-parent = <&UIC0>; 1891b55883aSStefan Roese interrupts = <2 4>; 1901b55883aSStefan Roese }; 1911b55883aSStefan Roese 1921b55883aSStefan Roese IIC1: i2c@ef600500 { 1931b55883aSStefan Roese device_type = "i2c"; 1941b55883aSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 1951b55883aSStefan Roese reg = <ef600500 14>; 1961b55883aSStefan Roese interrupt-parent = <&UIC0>; 1971b55883aSStefan Roese interrupts = <7 4>; 1981b55883aSStefan Roese }; 1991b55883aSStefan Roese 2001b55883aSStefan Roese 2011b55883aSStefan Roese RGMII0: emac-rgmii@ef600b00 { 2021b55883aSStefan Roese device_type = "rgmii-interface"; 2031b55883aSStefan Roese compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 2041b55883aSStefan Roese reg = <ef600b00 104>; 2051b55883aSStefan Roese has-mdio; 2061b55883aSStefan Roese }; 2071b55883aSStefan Roese 2081b55883aSStefan Roese EMAC0: ethernet@ef600900 { 2091b55883aSStefan Roese linux,network-index = <0>; 2101b55883aSStefan Roese device_type = "network"; 2111b55883aSStefan Roese compatible = "ibm,emac-405ex", "ibm,emac4"; 2121b55883aSStefan Roese interrupt-parent = <&EMAC0>; 2131b55883aSStefan Roese interrupts = <0 1>; 2141b55883aSStefan Roese #interrupt-cells = <1>; 2151b55883aSStefan Roese #address-cells = <0>; 2161b55883aSStefan Roese #size-cells = <0>; 2171b55883aSStefan Roese interrupt-map = </*Status*/ 0 &UIC0 18 4 2181b55883aSStefan Roese /*Wake*/ 1 &UIC1 1d 4>; 2191b55883aSStefan Roese reg = <ef600900 70>; 2201b55883aSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 2211b55883aSStefan Roese mal-device = <&MAL0>; 2221b55883aSStefan Roese mal-tx-channel = <0>; 2231b55883aSStefan Roese mal-rx-channel = <0>; 2241b55883aSStefan Roese cell-index = <0>; 2251b55883aSStefan Roese max-frame-size = <5dc>; 2261b55883aSStefan Roese rx-fifo-size = <1000>; 2271b55883aSStefan Roese tx-fifo-size = <800>; 2281b55883aSStefan Roese phy-mode = "rgmii"; 2291b55883aSStefan Roese phy-map = <0000003f>; /* Start at 6 */ 2301b55883aSStefan Roese rgmii-device = <&RGMII0>; 2311b55883aSStefan Roese rgmii-channel = <0>; 2321b55883aSStefan Roese has-inverted-stacr-oc; 2331b55883aSStefan Roese has-new-stacr-staopc; 2341b55883aSStefan Roese }; 2351b55883aSStefan Roese 2361b55883aSStefan Roese EMAC1: ethernet@ef600a00 { 2371b55883aSStefan Roese linux,network-index = <1>; 2381b55883aSStefan Roese device_type = "network"; 2391b55883aSStefan Roese compatible = "ibm,emac-405ex", "ibm,emac4"; 2401b55883aSStefan Roese interrupt-parent = <&EMAC1>; 2411b55883aSStefan Roese interrupts = <0 1>; 2421b55883aSStefan Roese #interrupt-cells = <1>; 2431b55883aSStefan Roese #address-cells = <0>; 2441b55883aSStefan Roese #size-cells = <0>; 2451b55883aSStefan Roese interrupt-map = </*Status*/ 0 &UIC0 19 4 2461b55883aSStefan Roese /*Wake*/ 1 &UIC1 1f 4>; 2471b55883aSStefan Roese reg = <ef600a00 70>; 2481b55883aSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 2491b55883aSStefan Roese mal-device = <&MAL0>; 2501b55883aSStefan Roese mal-tx-channel = <1>; 2511b55883aSStefan Roese mal-rx-channel = <1>; 2521b55883aSStefan Roese cell-index = <1>; 2531b55883aSStefan Roese max-frame-size = <5dc>; 2541b55883aSStefan Roese rx-fifo-size = <1000>; 2551b55883aSStefan Roese tx-fifo-size = <800>; 2561b55883aSStefan Roese phy-mode = "rgmii"; 2571b55883aSStefan Roese phy-map = <00000000>; 2581b55883aSStefan Roese rgmii-device = <&RGMII0>; 2591b55883aSStefan Roese rgmii-channel = <1>; 2601b55883aSStefan Roese has-inverted-stacr-oc; 2611b55883aSStefan Roese has-new-stacr-staopc; 2621b55883aSStefan Roese }; 2631b55883aSStefan Roese }; 2641b55883aSStefan Roese 2651b55883aSStefan Roese PCIE0: pciex@0a0000000 { 2661b55883aSStefan Roese device_type = "pci"; 2671b55883aSStefan Roese #interrupt-cells = <1>; 2681b55883aSStefan Roese #size-cells = <2>; 2691b55883aSStefan Roese #address-cells = <3>; 2701b55883aSStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 2711b55883aSStefan Roese primary; 2721b55883aSStefan Roese port = <0>; /* port number */ 2731b55883aSStefan Roese reg = <a0000000 20000000 /* Config space access */ 2741b55883aSStefan Roese ef000000 00001000>; /* Registers */ 2751b55883aSStefan Roese dcr-reg = <040 020>; 2761b55883aSStefan Roese sdr-base = <400>; 2771b55883aSStefan Roese 2781b55883aSStefan Roese /* Outbound ranges, one memory and one IO, 2791b55883aSStefan Roese * later cannot be changed 2801b55883aSStefan Roese */ 2811b55883aSStefan Roese ranges = <02000000 0 80000000 90000000 0 08000000 2821b55883aSStefan Roese 01000000 0 00000000 e0000000 0 00010000>; 2831b55883aSStefan Roese 2841b55883aSStefan Roese /* Inbound 2GB range starting at 0 */ 2851b55883aSStefan Roese dma-ranges = <42000000 0 0 0 0 80000000>; 2861b55883aSStefan Roese 2871b55883aSStefan Roese /* This drives busses 0x00 to 0x3f */ 2881b55883aSStefan Roese bus-range = <00 3f>; 2891b55883aSStefan Roese 2901b55883aSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 2911b55883aSStefan Roese * to invert PCIe legacy interrupts). 2921b55883aSStefan Roese * We are de-swizzling here because the numbers are actually for 2931b55883aSStefan Roese * port of the root complex virtual P2P bridge. But I want 2941b55883aSStefan Roese * to avoid putting a node for it in the tree, so the numbers 2951b55883aSStefan Roese * below are basically de-swizzled numbers. 2961b55883aSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 2971b55883aSStefan Roese */ 2981b55883aSStefan Roese interrupt-map-mask = <0000 0 0 7>; 2991b55883aSStefan Roese interrupt-map = < 3001b55883aSStefan Roese 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ 3011b55883aSStefan Roese 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ 3021b55883aSStefan Roese 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ 3031b55883aSStefan Roese 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; 3041b55883aSStefan Roese }; 3051b55883aSStefan Roese 3061b55883aSStefan Roese PCIE1: pciex@0c0000000 { 3071b55883aSStefan Roese device_type = "pci"; 3081b55883aSStefan Roese #interrupt-cells = <1>; 3091b55883aSStefan Roese #size-cells = <2>; 3101b55883aSStefan Roese #address-cells = <3>; 3111b55883aSStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 3121b55883aSStefan Roese primary; 3131b55883aSStefan Roese port = <1>; /* port number */ 3141b55883aSStefan Roese reg = <c0000000 20000000 /* Config space access */ 3151b55883aSStefan Roese ef001000 00001000>; /* Registers */ 3161b55883aSStefan Roese dcr-reg = <060 020>; 3171b55883aSStefan Roese sdr-base = <440>; 3181b55883aSStefan Roese 3191b55883aSStefan Roese /* Outbound ranges, one memory and one IO, 3201b55883aSStefan Roese * later cannot be changed 3211b55883aSStefan Roese */ 3221b55883aSStefan Roese ranges = <02000000 0 80000000 98000000 0 08000000 3231b55883aSStefan Roese 01000000 0 00000000 e0010000 0 00010000>; 3241b55883aSStefan Roese 3251b55883aSStefan Roese /* Inbound 2GB range starting at 0 */ 3261b55883aSStefan Roese dma-ranges = <42000000 0 0 0 0 80000000>; 3271b55883aSStefan Roese 3281b55883aSStefan Roese /* This drives busses 0x40 to 0x7f */ 3291b55883aSStefan Roese bus-range = <40 7f>; 3301b55883aSStefan Roese 3311b55883aSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 3321b55883aSStefan Roese * to invert PCIe legacy interrupts). 3331b55883aSStefan Roese * We are de-swizzling here because the numbers are actually for 3341b55883aSStefan Roese * port of the root complex virtual P2P bridge. But I want 3351b55883aSStefan Roese * to avoid putting a node for it in the tree, so the numbers 3361b55883aSStefan Roese * below are basically de-swizzled numbers. 3371b55883aSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 3381b55883aSStefan Roese */ 3391b55883aSStefan Roese interrupt-map-mask = <0000 0 0 7>; 3401b55883aSStefan Roese interrupt-map = < 3411b55883aSStefan Roese 0000 0 0 1 &UIC2 b 4 /* swizzled int A */ 3421b55883aSStefan Roese 0000 0 0 2 &UIC2 c 4 /* swizzled int B */ 3431b55883aSStefan Roese 0000 0 0 3 &UIC2 d 4 /* swizzled int C */ 3441b55883aSStefan Roese 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>; 3451b55883aSStefan Roese }; 3461b55883aSStefan Roese }; 3471b55883aSStefan Roese}; 348