1/* 2 * Lite5200B board Device Tree Source 3 * 4 * Copyright 2006 Secret Lab Technologies Ltd. 5 * Grant Likely <grant.likely@secretlab.ca> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/ { 14 model = "Lite5200b"; 15 compatible = "lite5200b\0lite52xx\0mpc5200b\0mpc52xx"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #cpus = <1>; 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 PowerPC,5200@0 { 25 device_type = "cpu"; 26 reg = <0>; 27 d-cache-line-size = <20>; 28 i-cache-line-size = <20>; 29 d-cache-size = <4000>; // L1, 16K 30 i-cache-size = <4000>; // L1, 16K 31 timebase-frequency = <0>; // from bootloader 32 bus-frequency = <0>; // from bootloader 33 clock-frequency = <0>; // from bootloader 34 32-bit; 35 }; 36 }; 37 38 memory { 39 device_type = "memory"; 40 reg = <00000000 10000000>; // 256MB 41 }; 42 43 soc5200@f0000000 { 44 #interrupt-cells = <3>; 45 device_type = "soc"; 46 ranges = <0 f0000000 f0010000>; 47 reg = <f0000000 00010000>; 48 bus-frequency = <0>; // from bootloader 49 50 cdm@200 { 51 compatible = "mpc5200b-cdm\0mpc52xx-cdm"; 52 reg = <200 38>; 53 }; 54 55 pic@500 { 56 // 5200 interrupts are encoded into two levels; 57 linux,phandle = <500>; 58 interrupt-controller; 59 #interrupt-cells = <3>; 60 device_type = "interrupt-controller"; 61 compatible = "mpc5200b-pic\0mpc52xx-pic"; 62 reg = <500 80>; 63 built-in; 64 }; 65 66 gpt@600 { // General Purpose Timer 67 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 68 device_type = "gpt"; 69 reg = <600 10>; 70 interrupts = <1 9 0>; 71 interrupt-parent = <500>; 72 }; 73 74 gpt@610 { // General Purpose Timer 75 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 76 device_type = "gpt"; 77 reg = <610 10>; 78 interrupts = <1 a 0>; 79 interrupt-parent = <500>; 80 }; 81 82 gpt@620 { // General Purpose Timer 83 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 84 device_type = "gpt"; 85 reg = <620 10>; 86 interrupts = <1 b 0>; 87 interrupt-parent = <500>; 88 }; 89 90 gpt@630 { // General Purpose Timer 91 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 92 device_type = "gpt"; 93 reg = <630 10>; 94 interrupts = <1 c 0>; 95 interrupt-parent = <500>; 96 }; 97 98 gpt@640 { // General Purpose Timer 99 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 100 device_type = "gpt"; 101 reg = <640 10>; 102 interrupts = <1 d 0>; 103 interrupt-parent = <500>; 104 }; 105 106 gpt@650 { // General Purpose Timer 107 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 108 device_type = "gpt"; 109 reg = <650 10>; 110 interrupts = <1 e 0>; 111 interrupt-parent = <500>; 112 }; 113 114 gpt@660 { // General Purpose Timer 115 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 116 device_type = "gpt"; 117 reg = <660 10>; 118 interrupts = <1 f 0>; 119 interrupt-parent = <500>; 120 }; 121 122 gpt@670 { // General Purpose Timer 123 compatible = "mpc5200b-gpt\0mpc52xx-gpt"; 124 device_type = "gpt"; 125 reg = <670 10>; 126 interrupts = <1 10 0>; 127 interrupt-parent = <500>; 128 }; 129 130 rtc@800 { // Real time clock 131 compatible = "mpc5200b-rtc\0mpc52xx-rtc"; 132 device_type = "rtc"; 133 reg = <800 100>; 134 interrupts = <1 5 0 1 6 0>; 135 interrupt-parent = <500>; 136 }; 137 138 mscan@900 { 139 device_type = "mscan"; 140 compatible = "mpc5200b-mscan\0mpc52xx-mscan"; 141 interrupts = <2 11 0>; 142 interrupt-parent = <500>; 143 reg = <900 80>; 144 }; 145 146 mscan@980 { 147 device_type = "mscan"; 148 compatible = "mpc5200b-mscan\0mpc52xx-mscan"; 149 interrupts = <1 12 0>; 150 interrupt-parent = <500>; 151 reg = <980 80>; 152 }; 153 154 gpio@b00 { 155 compatible = "mpc5200b-gpio\0mpc52xx-gpio"; 156 reg = <b00 40>; 157 interrupts = <1 7 0>; 158 interrupt-parent = <500>; 159 }; 160 161 gpio-wkup@b00 { 162 compatible = "mpc5200b-gpio-wkup\0mpc52xx-gpio-wkup"; 163 reg = <c00 40>; 164 interrupts = <1 8 0 0 3 0>; 165 interrupt-parent = <500>; 166 }; 167 168 pci@0d00 { 169 #interrupt-cells = <1>; 170 #size-cells = <2>; 171 #address-cells = <3>; 172 device_type = "pci"; 173 compatible = "mpc5200b-pci\0mpc52xx-pci"; 174 reg = <d00 100>; 175 interrupt-map-mask = <f800 0 0 7>; 176 interrupt-map = <c000 0 0 1 500 0 0 3 // 1st slot 177 c000 0 0 2 500 1 1 3 178 c000 0 0 3 500 1 2 3 179 c000 0 0 4 500 1 3 3 180 181 c800 0 0 1 500 1 1 3 // 2nd slot 182 c800 0 0 2 500 1 2 3 183 c800 0 0 3 500 1 3 3 184 c800 0 0 4 500 0 0 3>; 185 clock-frequency = <0>; // From boot loader 186 interrupts = <2 8 0 2 9 0 2 a 0>; 187 interrupt-parent = <500>; 188 bus-range = <0 0>; 189 ranges = <42000000 0 80000000 80000000 0 20000000 190 02000000 0 a0000000 a0000000 0 10000000 191 01000000 0 00000000 b0000000 0 01000000>; 192 }; 193 194 spi@f00 { 195 device_type = "spi"; 196 compatible = "mpc5200b-spi\0mpc52xx-spi"; 197 reg = <f00 20>; 198 interrupts = <2 d 0 2 e 0>; 199 interrupt-parent = <500>; 200 }; 201 202 usb@1000 { 203 device_type = "usb-ohci-be"; 204 compatible = "mpc5200b-ohci\0mpc52xx-ohci\0ohci-be"; 205 reg = <1000 ff>; 206 interrupts = <2 6 0>; 207 interrupt-parent = <500>; 208 }; 209 210 bestcomm@1200 { 211 device_type = "dma-controller"; 212 compatible = "mpc5200b-bestcomm\0mpc52xx-bestcomm"; 213 reg = <1200 80>; 214 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 215 3 4 0 3 5 0 3 6 0 3 7 0 216 3 8 0 3 9 0 3 a 0 3 b 0 217 3 c 0 3 d 0 3 e 0 3 f 0>; 218 interrupt-parent = <500>; 219 }; 220 221 xlb@1f00 { 222 compatible = "mpc5200b-xlb\0mpc52xx-xlb"; 223 reg = <1f00 100>; 224 }; 225 226 serial@2000 { // PSC1 227 device_type = "serial"; 228 compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart"; 229 port-number = <0>; // Logical port assignment 230 reg = <2000 100>; 231 interrupts = <2 1 0>; 232 interrupt-parent = <500>; 233 }; 234 235 // PSC2 in spi mode example 236 spi@2200 { // PSC2 237 device_type = "spi"; 238 compatible = "mpc5200b-psc-spi\0mpc52xx-psc-spi"; 239 reg = <2200 100>; 240 interrupts = <2 2 0>; 241 interrupt-parent = <500>; 242 }; 243 244 // PSC3 in CODEC mode example 245 i2s@2400 { // PSC3 246 device_type = "sound"; 247 compatible = "mpc5200b-psc-i2s\0mpc52xx-psc-i2s"; 248 reg = <2400 100>; 249 interrupts = <2 3 0>; 250 interrupt-parent = <500>; 251 }; 252 253 // PSC4 unconfigured 254 //serial@2600 { // PSC4 255 // device_type = "serial"; 256 // compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart"; 257 // reg = <2600 100>; 258 // interrupts = <2 b 0>; 259 // interrupt-parent = <500>; 260 //}; 261 262 // PSC5 unconfigured 263 //serial@2800 { // PSC5 264 // device_type = "serial"; 265 // compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart"; 266 // reg = <2800 100>; 267 // interrupts = <2 c 0>; 268 // interrupt-parent = <500>; 269 //}; 270 271 // PSC6 in AC97 mode example 272 ac97@2c00 { // PSC6 273 device_type = "sound"; 274 compatible = "mpc5200b-psc-ac97\0mpc52xx-psc-ac97"; 275 reg = <2c00 100>; 276 interrupts = <2 4 0>; 277 interrupt-parent = <500>; 278 }; 279 280 ethernet@3000 { 281 device_type = "network"; 282 compatible = "mpc5200b-fec\0mpc52xx-fec"; 283 reg = <3000 800>; 284 mac-address = [ 02 03 04 05 06 07 ]; // Bad! 285 interrupts = <2 5 0>; 286 interrupt-parent = <500>; 287 }; 288 289 ata@3a00 { 290 device_type = "ata"; 291 compatible = "mpc5200b-ata\0mpc52xx-ata"; 292 reg = <3a00 100>; 293 interrupts = <2 7 0>; 294 interrupt-parent = <500>; 295 }; 296 297 i2c@3d00 { 298 device_type = "i2c"; 299 compatible = "mpc5200b-i2c\0mpc52xx-i2c"; 300 reg = <3d00 40>; 301 interrupts = <2 f 0>; 302 interrupt-parent = <500>; 303 }; 304 305 i2c@3d40 { 306 device_type = "i2c"; 307 compatible = "mpc5200b-i2c\0mpc52xx-i2c"; 308 reg = <3d40 40>; 309 interrupts = <2 10 0>; 310 interrupt-parent = <500>; 311 }; 312 sram@8000 { 313 device_type = "sram"; 314 compatible = "mpc5200b-sram\0mpc52xx-sram\0sram"; 315 reg = <8000 4000>; 316 }; 317 }; 318}; 319