1/* 2 * Lite5200B board Device Tree Source 3 * 4 * Copyright 2006-2007 Secret Lab Technologies Ltd. 5 * Grant Likely <grant.likely@secretlab.ca> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14 15/ { 16 model = "fsl,lite5200b"; 17 compatible = "fsl,lite5200b"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 PowerPC,5200@0 { 26 device_type = "cpu"; 27 reg = <0>; 28 d-cache-line-size = <32>; 29 i-cache-line-size = <32>; 30 d-cache-size = <0x4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K 32 timebase-frequency = <0>; // from bootloader 33 bus-frequency = <0>; // from bootloader 34 clock-frequency = <0>; // from bootloader 35 }; 36 }; 37 38 memory { 39 device_type = "memory"; 40 reg = <0x00000000 0x10000000>; // 256MB 41 }; 42 43 soc5200@f0000000 { 44 #address-cells = <1>; 45 #size-cells = <1>; 46 compatible = "fsl,mpc5200b-immr"; 47 ranges = <0 0xf0000000 0x0000c000>; 48 reg = <0xf0000000 0x00000100>; 49 bus-frequency = <0>; // from bootloader 50 system-frequency = <0>; // from bootloader 51 52 cdm@200 { 53 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 54 reg = <0x200 0x38>; 55 }; 56 57 mpc5200_pic: interrupt-controller@500 { 58 // 5200 interrupts are encoded into two levels; 59 interrupt-controller; 60 #interrupt-cells = <3>; 61 device_type = "interrupt-controller"; 62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 63 reg = <0x500 0x80>; 64 }; 65 66 timer@600 { // General Purpose Timer 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 68 cell-index = <0>; 69 reg = <0x600 0x10>; 70 interrupts = <1 9 0>; 71 interrupt-parent = <&mpc5200_pic>; 72 fsl,has-wdt; 73 }; 74 75 timer@610 { // General Purpose Timer 76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 77 cell-index = <1>; 78 reg = <0x610 0x10>; 79 interrupts = <1 10 0>; 80 interrupt-parent = <&mpc5200_pic>; 81 }; 82 83 timer@620 { // General Purpose Timer 84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 85 cell-index = <2>; 86 reg = <0x620 0x10>; 87 interrupts = <1 11 0>; 88 interrupt-parent = <&mpc5200_pic>; 89 }; 90 91 timer@630 { // General Purpose Timer 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 93 cell-index = <3>; 94 reg = <0x630 0x10>; 95 interrupts = <1 12 0>; 96 interrupt-parent = <&mpc5200_pic>; 97 }; 98 99 timer@640 { // General Purpose Timer 100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 101 cell-index = <4>; 102 reg = <0x640 0x10>; 103 interrupts = <1 13 0>; 104 interrupt-parent = <&mpc5200_pic>; 105 }; 106 107 timer@650 { // General Purpose Timer 108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 109 cell-index = <5>; 110 reg = <0x650 0x10>; 111 interrupts = <1 14 0>; 112 interrupt-parent = <&mpc5200_pic>; 113 }; 114 115 timer@660 { // General Purpose Timer 116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 117 cell-index = <6>; 118 reg = <0x660 0x10>; 119 interrupts = <1 15 0>; 120 interrupt-parent = <&mpc5200_pic>; 121 }; 122 123 timer@670 { // General Purpose Timer 124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 125 cell-index = <7>; 126 reg = <0x670 0x10>; 127 interrupts = <1 16 0>; 128 interrupt-parent = <&mpc5200_pic>; 129 }; 130 131 rtc@800 { // Real time clock 132 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 133 reg = <0x800 0x100>; 134 interrupts = <1 5 0 1 6 0>; 135 interrupt-parent = <&mpc5200_pic>; 136 }; 137 138 can@900 { 139 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 140 cell-index = <0>; 141 interrupts = <2 17 0>; 142 interrupt-parent = <&mpc5200_pic>; 143 reg = <0x900 0x80>; 144 }; 145 146 can@980 { 147 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 148 cell-index = <1>; 149 interrupts = <2 18 0>; 150 interrupt-parent = <&mpc5200_pic>; 151 reg = <0x980 0x80>; 152 }; 153 154 gpio@b00 { 155 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 156 reg = <0xb00 0x40>; 157 interrupts = <1 7 0>; 158 interrupt-parent = <&mpc5200_pic>; 159 }; 160 161 gpio@c00 { 162 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 163 reg = <0xc00 0x40>; 164 interrupts = <1 8 0 0 3 0>; 165 interrupt-parent = <&mpc5200_pic>; 166 }; 167 168 spi@f00 { 169 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 170 reg = <0xf00 0x20>; 171 interrupts = <2 13 0 2 14 0>; 172 interrupt-parent = <&mpc5200_pic>; 173 }; 174 175 usb@1000 { 176 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 177 reg = <0x1000 0xff>; 178 interrupts = <2 6 0>; 179 interrupt-parent = <&mpc5200_pic>; 180 }; 181 182 dma-controller@1200 { 183 device_type = "dma-controller"; 184 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 185 reg = <0x1200 0x80>; 186 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 187 3 4 0 3 5 0 3 6 0 3 7 0 188 3 8 0 3 9 0 3 10 0 3 11 0 189 3 12 0 3 13 0 3 14 0 3 15 0>; 190 interrupt-parent = <&mpc5200_pic>; 191 }; 192 193 xlb@1f00 { 194 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 195 reg = <0x1f00 0x100>; 196 }; 197 198 serial@2000 { // PSC1 199 device_type = "serial"; 200 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 201 port-number = <0>; // Logical port assignment 202 cell-index = <0>; 203 reg = <0x2000 0x100>; 204 interrupts = <2 1 0>; 205 interrupt-parent = <&mpc5200_pic>; 206 }; 207 208 // PSC2 in ac97 mode example 209 //ac97@2200 { // PSC2 210 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 211 // cell-index = <1>; 212 // reg = <0x2200 0x100>; 213 // interrupts = <2 2 0>; 214 // interrupt-parent = <&mpc5200_pic>; 215 //}; 216 217 // PSC3 in CODEC mode example 218 //i2s@2400 { // PSC3 219 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible 220 // cell-index = <2>; 221 // reg = <0x2400 0x100>; 222 // interrupts = <2 3 0>; 223 // interrupt-parent = <&mpc5200_pic>; 224 //}; 225 226 // PSC4 in uart mode example 227 //serial@2600 { // PSC4 228 // device_type = "serial"; 229 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 230 // cell-index = <3>; 231 // reg = <0x2600 0x100>; 232 // interrupts = <2 11 0>; 233 // interrupt-parent = <&mpc5200_pic>; 234 //}; 235 236 // PSC5 in uart mode example 237 //serial@2800 { // PSC5 238 // device_type = "serial"; 239 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 240 // cell-index = <4>; 241 // reg = <0x2800 0x100>; 242 // interrupts = <2 12 0>; 243 // interrupt-parent = <&mpc5200_pic>; 244 //}; 245 246 // PSC6 in spi mode example 247 //spi@2c00 { // PSC6 248 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; 249 // cell-index = <5>; 250 // reg = <0x2c00 0x100>; 251 // interrupts = <2 4 0>; 252 // interrupt-parent = <&mpc5200_pic>; 253 //}; 254 255 ethernet@3000 { 256 device_type = "network"; 257 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 258 reg = <0x3000 0x400>; 259 local-mac-address = [ 00 00 00 00 00 00 ]; 260 interrupts = <2 5 0>; 261 interrupt-parent = <&mpc5200_pic>; 262 phy-handle = <&phy0>; 263 }; 264 265 mdio@3000 { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 269 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 270 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 271 interrupt-parent = <&mpc5200_pic>; 272 273 phy0: ethernet-phy@0 { 274 device_type = "ethernet-phy"; 275 reg = <0>; 276 }; 277 }; 278 279 ata@3a00 { 280 device_type = "ata"; 281 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 282 reg = <0x3a00 0x100>; 283 interrupts = <2 7 0>; 284 interrupt-parent = <&mpc5200_pic>; 285 }; 286 287 i2c@3d00 { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 291 cell-index = <0>; 292 reg = <0x3d00 0x40>; 293 interrupts = <2 15 0>; 294 interrupt-parent = <&mpc5200_pic>; 295 fsl5200-clocking; 296 }; 297 298 i2c@3d40 { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 302 cell-index = <1>; 303 reg = <0x3d40 0x40>; 304 interrupts = <2 16 0>; 305 interrupt-parent = <&mpc5200_pic>; 306 fsl5200-clocking; 307 }; 308 sram@8000 { 309 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 310 reg = <0x8000 0x4000>; 311 }; 312 }; 313 314 pci@f0000d00 { 315 #interrupt-cells = <1>; 316 #size-cells = <2>; 317 #address-cells = <3>; 318 device_type = "pci"; 319 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 320 reg = <0xf0000d00 0x100>; 321 interrupt-map-mask = <0xf800 0 0 7>; 322 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 323 0xc000 0 0 2 &mpc5200_pic 1 1 3 324 0xc000 0 0 3 &mpc5200_pic 1 2 3 325 0xc000 0 0 4 &mpc5200_pic 1 3 3 326 327 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot 328 0xc800 0 0 2 &mpc5200_pic 1 2 3 329 0xc800 0 0 3 &mpc5200_pic 1 3 3 330 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 331 clock-frequency = <0>; // From boot loader 332 interrupts = <2 8 0 2 9 0 2 10 0>; 333 interrupt-parent = <&mpc5200_pic>; 334 bus-range = <0 0>; 335 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 336 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 337 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 338 }; 339}; 340