1/*
2 * Lite5200B board Device Tree Source
3 *
4 * Copyright 2006-2007 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 */
12
13/*
14 * WARNING: Do not depend on this tree layout remaining static just yet.
15 * The MPC5200 device tree conventions are still in flux
16 * Keep an eye on the linuxppc-dev mailing list for more details
17 */
18
19/ {
20	model = "fsl,lite5200b";
21	// revision = "1.0";
22	compatible = "fsl,lite5200b\0generic-mpc5200";
23	#address-cells = <1>;
24	#size-cells = <1>;
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		PowerPC,5200@0 {
31			device_type = "cpu";
32			reg = <0>;
33			d-cache-line-size = <20>;
34			i-cache-line-size = <20>;
35			d-cache-size = <4000>;		// L1, 16K
36			i-cache-size = <4000>;		// L1, 16K
37			timebase-frequency = <0>;	// from bootloader
38			bus-frequency = <0>;		// from bootloader
39			clock-frequency = <0>;		// from bootloader
40			32-bit;
41		};
42	};
43
44	memory {
45		device_type = "memory";
46		reg = <00000000 10000000>;	// 256MB
47	};
48
49	soc5200@f0000000 {
50		model = "fsl,mpc5200b";
51		compatible = "mpc5200";
52		revision = "";			// from bootloader
53		#interrupt-cells = <3>;
54		device_type = "soc";
55		ranges = <0 f0000000 f0010000>;
56		reg = <f0000000 00010000>;
57		bus-frequency = <0>;		// from bootloader
58		system-frequency = <0>;		// from bootloader
59
60		cdm@200 {
61			compatible = "mpc5200b-cdm\0mpc5200-cdm";
62			reg = <200 38>;
63		};
64
65		pic@500 {
66			// 5200 interrupts are encoded into two levels;
67			linux,phandle = <500>;
68			interrupt-controller;
69			#interrupt-cells = <3>;
70			device_type = "interrupt-controller";
71			compatible = "mpc5200b-pic\0mpc5200-pic";
72			reg = <500 80>;
73			built-in;
74		};
75
76		gpt@600 {	// General Purpose Timer
77			compatible = "mpc5200b-gpt\0mpc5200-gpt";
78			device_type = "gpt";
79			cell-index = <0>;
80			reg = <600 10>;
81			interrupts = <1 9 0>;
82			interrupt-parent = <500>;
83			has-wdt;
84		};
85
86		gpt@610 {	// General Purpose Timer
87			compatible = "mpc5200b-gpt\0mpc5200-gpt";
88			device_type = "gpt";
89			cell-index = <1>;
90			reg = <610 10>;
91			interrupts = <1 a 0>;
92			interrupt-parent = <500>;
93		};
94
95		gpt@620 {	// General Purpose Timer
96			compatible = "mpc5200b-gpt\0mpc5200-gpt";
97			device_type = "gpt";
98			cell-index = <2>;
99			reg = <620 10>;
100			interrupts = <1 b 0>;
101			interrupt-parent = <500>;
102		};
103
104		gpt@630 {	// General Purpose Timer
105			compatible = "mpc5200b-gpt\0mpc5200-gpt";
106			device_type = "gpt";
107			cell-index = <3>;
108			reg = <630 10>;
109			interrupts = <1 c 0>;
110			interrupt-parent = <500>;
111		};
112
113		gpt@640 {	// General Purpose Timer
114			compatible = "mpc5200b-gpt\0mpc5200-gpt";
115			device_type = "gpt";
116			cell-index = <4>;
117			reg = <640 10>;
118			interrupts = <1 d 0>;
119			interrupt-parent = <500>;
120		};
121
122		gpt@650 {	// General Purpose Timer
123			compatible = "mpc5200b-gpt\0mpc5200-gpt";
124			device_type = "gpt";
125			cell-index = <5>;
126			reg = <650 10>;
127			interrupts = <1 e 0>;
128			interrupt-parent = <500>;
129		};
130
131		gpt@660 {	// General Purpose Timer
132			compatible = "mpc5200b-gpt\0mpc5200-gpt";
133			device_type = "gpt";
134			cell-index = <6>;
135			reg = <660 10>;
136			interrupts = <1 f 0>;
137			interrupt-parent = <500>;
138		};
139
140		gpt@670 {	// General Purpose Timer
141			compatible = "mpc5200b-gpt\0mpc5200-gpt";
142			device_type = "gpt";
143			cell-index = <7>;
144			reg = <670 10>;
145			interrupts = <1 10 0>;
146			interrupt-parent = <500>;
147		};
148
149		rtc@800 {	// Real time clock
150			compatible = "mpc5200b-rtc\0mpc5200-rtc";
151			device_type = "rtc";
152			reg = <800 100>;
153			interrupts = <1 5 0 1 6 0>;
154			interrupt-parent = <500>;
155		};
156
157		mscan@900 {
158			device_type = "mscan";
159			compatible = "mpc5200b-mscan\0mpc5200-mscan";
160			cell-index = <0>;
161			interrupts = <2 11 0>;
162			interrupt-parent = <500>;
163			reg = <900 80>;
164		};
165
166		mscan@980 {
167			device_type = "mscan";
168			compatible = "mpc5200b-mscan\0mpc5200-mscan";
169			cell-index = <1>;
170			interrupts = <2 12 0>;
171			interrupt-parent = <500>;
172			reg = <980 80>;
173		};
174
175		gpio@b00 {
176			compatible = "mpc5200b-gpio\0mpc5200-gpio";
177			reg = <b00 40>;
178			interrupts = <1 7 0>;
179			interrupt-parent = <500>;
180		};
181
182		gpio-wkup@c00 {
183			compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup";
184			reg = <c00 40>;
185			interrupts = <1 8 0 0 3 0>;
186			interrupt-parent = <500>;
187		};
188
189		pci@0d00 {
190			#interrupt-cells = <1>;
191			#size-cells = <2>;
192			#address-cells = <3>;
193			device_type = "pci";
194			compatible = "mpc5200b-pci\0mpc5200-pci";
195			reg = <d00 100>;
196			interrupt-map-mask = <f800 0 0 7>;
197			interrupt-map = <c000 0 0 1 500 0 0 3 // 1st slot
198			                 c000 0 0 2 500 1 1 3
199			                 c000 0 0 3 500 1 2 3
200			                 c000 0 0 4 500 1 3 3
201
202			                 c800 0 0 1 500 1 1 3 // 2nd slot
203			                 c800 0 0 2 500 1 2 3
204			                 c800 0 0 3 500 1 3 3
205			                 c800 0 0 4 500 0 0 3>;
206			clock-frequency = <0>; // From boot loader
207			interrupts = <2 8 0 2 9 0 2 a 0>;
208			interrupt-parent = <500>;
209			bus-range = <0 0>;
210			ranges = <42000000 0 80000000 80000000 0 20000000
211			          02000000 0 a0000000 a0000000 0 10000000
212			          01000000 0 00000000 b0000000 0 01000000>;
213		};
214
215		spi@f00 {
216			device_type = "spi";
217			compatible = "mpc5200b-spi\0mpc5200-spi";
218			reg = <f00 20>;
219			interrupts = <2 d 0 2 e 0>;
220			interrupt-parent = <500>;
221		};
222
223		usb@1000 {
224			device_type = "usb-ohci-be";
225			compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be";
226			reg = <1000 ff>;
227			interrupts = <2 6 0>;
228			interrupt-parent = <500>;
229		};
230
231		bestcomm@1200 {
232			device_type = "dma-controller";
233			compatible = "mpc5200b-bestcomm\0mpc5200-bestcomm";
234			reg = <1200 80>;
235			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
236			              3 4 0  3 5 0  3 6 0  3 7 0
237			              3 8 0  3 9 0  3 a 0  3 b 0
238			              3 c 0  3 d 0  3 e 0  3 f 0>;
239			interrupt-parent = <500>;
240		};
241
242		xlb@1f00 {
243			compatible = "mpc5200b-xlb\0mpc5200-xlb";
244			reg = <1f00 100>;
245		};
246
247		serial@2000 {		// PSC1
248			device_type = "serial";
249			compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
250			port-number = <0>;  // Logical port assignment
251			cell-index = <0>;
252			reg = <2000 100>;
253			interrupts = <2 1 0>;
254			interrupt-parent = <500>;
255		};
256
257		// PSC2 in ac97 mode example
258		//ac97@2200 {		// PSC2
259		//	device_type = "sound";
260		//	compatible = "mpc5200b-psc-ac97\0mpc5200-psc-ac97";
261		//	cell-index = <1>;
262		//	reg = <2200 100>;
263		//	interrupts = <2 2 0>;
264		//	interrupt-parent = <500>;
265		//};
266
267		// PSC3 in CODEC mode example
268		//i2s@2400 {		// PSC3
269		//	device_type = "sound";
270		//	compatible = "mpc5200b-psc-i2s"; //not 5200 compatible
271		//	cell-index = <2>;
272		//	reg = <2400 100>;
273		//	interrupts = <2 3 0>;
274		//	interrupt-parent = <500>;
275		//};
276
277		// PSC4 in uart mode example
278		//serial@2600 {		// PSC4
279		//	device_type = "serial";
280		//	compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
281		//	cell-index = <3>;
282		//	reg = <2600 100>;
283		//	interrupts = <2 b 0>;
284		//	interrupt-parent = <500>;
285		//};
286
287		// PSC5 in uart mode example
288		//serial@2800 {		// PSC5
289		//	device_type = "serial";
290		//	compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
291		//	cell-index = <4>;
292		//	reg = <2800 100>;
293		//	interrupts = <2 c 0>;
294		//	interrupt-parent = <500>;
295		//};
296
297		// PSC6 in spi mode example
298		//spi@2c00 {		// PSC6
299		//	device_type = "spi";
300		//	compatible = "mpc5200b-psc-spi\0mpc5200-psc-spi";
301		//	cell-index = <5>;
302		//	reg = <2c00 100>;
303		//	interrupts = <2 4 0>;
304		//	interrupt-parent = <500>;
305		//};
306
307		ethernet@3000 {
308			device_type = "network";
309			compatible = "mpc5200b-fec\0mpc5200-fec";
310			reg = <3000 800>;
311			mac-address = [ 02 03 04 05 06 07 ]; // Bad!
312			interrupts = <2 5 0>;
313			interrupt-parent = <500>;
314		};
315
316		ata@3a00 {
317			device_type = "ata";
318			compatible = "mpc5200b-ata\0mpc5200-ata";
319			reg = <3a00 100>;
320			interrupts = <2 7 0>;
321			interrupt-parent = <500>;
322		};
323
324		i2c@3d00 {
325			device_type = "i2c";
326			compatible = "mpc5200b-i2c\0mpc5200-i2c";
327			cell-index = <0>;
328			reg = <3d00 40>;
329			interrupts = <2 f 0>;
330			interrupt-parent = <500>;
331		};
332
333		i2c@3d40 {
334			device_type = "i2c";
335			compatible = "mpc5200b-i2c\0mpc5200-i2c";
336			cell-index = <1>;
337			reg = <3d40 40>;
338			interrupts = <2 10 0>;
339			interrupt-parent = <500>;
340		};
341		sram@8000 {
342			device_type = "sram";
343			compatible = "mpc5200b-sram\0mpc5200-sram\0sram";
344			reg = <8000 4000>;
345		};
346	};
347};
348