1/* 2 * Lite5200 board Device Tree Source 3 * 4 * Copyright 2006-2007 Secret Lab Technologies Ltd. 5 * Grant Likely <grant.likely@secretlab.ca> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14 15/ { 16 model = "fsl,lite5200"; 17 compatible = "fsl,lite5200"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 PowerPC,5200@0 { 26 device_type = "cpu"; 27 reg = <0>; 28 d-cache-line-size = <32>; 29 i-cache-line-size = <32>; 30 d-cache-size = <0x4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K 32 timebase-frequency = <0>; // from bootloader 33 bus-frequency = <0>; // from bootloader 34 clock-frequency = <0>; // from bootloader 35 }; 36 }; 37 38 memory { 39 device_type = "memory"; 40 reg = <0x00000000 0x04000000>; // 64MB 41 }; 42 43 soc5200@f0000000 { 44 #address-cells = <1>; 45 #size-cells = <1>; 46 compatible = "fsl,mpc5200-immr"; 47 ranges = <0 0xf0000000 0x0000c000>; 48 reg = <0xf0000000 0x00000100>; 49 bus-frequency = <0>; // from bootloader 50 system-frequency = <0>; // from bootloader 51 52 cdm@200 { 53 compatible = "fsl,mpc5200-cdm"; 54 reg = <0x200 0x38>; 55 }; 56 57 mpc5200_pic: interrupt-controller@500 { 58 // 5200 interrupts are encoded into two levels; 59 interrupt-controller; 60 #interrupt-cells = <3>; 61 device_type = "interrupt-controller"; 62 compatible = "fsl,mpc5200-pic"; 63 reg = <0x500 0x80>; 64 }; 65 66 timer@600 { // General Purpose Timer 67 compatible = "fsl,mpc5200-gpt"; 68 cell-index = <0>; 69 reg = <0x600 0x10>; 70 interrupts = <1 9 0>; 71 interrupt-parent = <&mpc5200_pic>; 72 fsl,has-wdt; 73 }; 74 75 timer@610 { // General Purpose Timer 76 compatible = "fsl,mpc5200-gpt"; 77 cell-index = <1>; 78 reg = <0x610 0x10>; 79 interrupts = <1 10 0>; 80 interrupt-parent = <&mpc5200_pic>; 81 }; 82 83 timer@620 { // General Purpose Timer 84 compatible = "fsl,mpc5200-gpt"; 85 cell-index = <2>; 86 reg = <0x620 0x10>; 87 interrupts = <1 11 0>; 88 interrupt-parent = <&mpc5200_pic>; 89 }; 90 91 timer@630 { // General Purpose Timer 92 compatible = "fsl,mpc5200-gpt"; 93 cell-index = <3>; 94 reg = <0x630 0x10>; 95 interrupts = <1 12 0>; 96 interrupt-parent = <&mpc5200_pic>; 97 }; 98 99 timer@640 { // General Purpose Timer 100 compatible = "fsl,mpc5200-gpt"; 101 cell-index = <4>; 102 reg = <0x640 0x10>; 103 interrupts = <1 13 0>; 104 interrupt-parent = <&mpc5200_pic>; 105 }; 106 107 timer@650 { // General Purpose Timer 108 compatible = "fsl,mpc5200-gpt"; 109 cell-index = <5>; 110 reg = <0x650 0x10>; 111 interrupts = <1 14 0>; 112 interrupt-parent = <&mpc5200_pic>; 113 }; 114 115 timer@660 { // General Purpose Timer 116 compatible = "fsl,mpc5200-gpt"; 117 cell-index = <6>; 118 reg = <0x660 0x10>; 119 interrupts = <1 15 0>; 120 interrupt-parent = <&mpc5200_pic>; 121 }; 122 123 timer@670 { // General Purpose Timer 124 compatible = "fsl,mpc5200-gpt"; 125 cell-index = <7>; 126 reg = <0x670 0x10>; 127 interrupts = <1 16 0>; 128 interrupt-parent = <&mpc5200_pic>; 129 }; 130 131 rtc@800 { // Real time clock 132 compatible = "fsl,mpc5200-rtc"; 133 device_type = "rtc"; 134 reg = <0x800 0x100>; 135 interrupts = <1 5 0 1 6 0>; 136 interrupt-parent = <&mpc5200_pic>; 137 }; 138 139 can@900 { 140 compatible = "fsl,mpc5200-mscan"; 141 cell-index = <0>; 142 interrupts = <2 17 0>; 143 interrupt-parent = <&mpc5200_pic>; 144 reg = <0x900 0x80>; 145 }; 146 147 can@980 { 148 compatible = "fsl,mpc5200-mscan"; 149 cell-index = <1>; 150 interrupts = <2 18 0>; 151 interrupt-parent = <&mpc5200_pic>; 152 reg = <0x980 0x80>; 153 }; 154 155 gpio@b00 { 156 compatible = "fsl,mpc5200-gpio"; 157 reg = <0xb00 0x40>; 158 interrupts = <1 7 0>; 159 interrupt-parent = <&mpc5200_pic>; 160 }; 161 162 gpio@c00 { 163 compatible = "fsl,mpc5200-gpio-wkup"; 164 reg = <0xc00 0x40>; 165 interrupts = <1 8 0 0 3 0>; 166 interrupt-parent = <&mpc5200_pic>; 167 }; 168 169 spi@f00 { 170 compatible = "fsl,mpc5200-spi"; 171 reg = <0xf00 0x20>; 172 interrupts = <2 13 0 2 14 0>; 173 interrupt-parent = <&mpc5200_pic>; 174 }; 175 176 usb@1000 { 177 compatible = "fsl,mpc5200-ohci","ohci-be"; 178 reg = <0x1000 0xff>; 179 interrupts = <2 6 0>; 180 interrupt-parent = <&mpc5200_pic>; 181 }; 182 183 dma-controller@1200 { 184 device_type = "dma-controller"; 185 compatible = "fsl,mpc5200-bestcomm"; 186 reg = <0x1200 0x80>; 187 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 188 3 4 0 3 5 0 3 6 0 3 7 0 189 3 8 0 3 9 0 3 10 0 3 11 0 190 3 12 0 3 13 0 3 14 0 3 15 0>; 191 interrupt-parent = <&mpc5200_pic>; 192 }; 193 194 xlb@1f00 { 195 compatible = "fsl,mpc5200-xlb"; 196 reg = <0x1f00 0x100>; 197 }; 198 199 serial@2000 { // PSC1 200 device_type = "serial"; 201 compatible = "fsl,mpc5200-psc-uart"; 202 port-number = <0>; // Logical port assignment 203 cell-index = <0>; 204 reg = <0x2000 0x100>; 205 interrupts = <2 1 0>; 206 interrupt-parent = <&mpc5200_pic>; 207 }; 208 209 // PSC2 in ac97 mode example 210 //ac97@2200 { // PSC2 211 // compatible = "fsl,mpc5200-psc-ac97"; 212 // cell-index = <1>; 213 // reg = <0x2200 0x100>; 214 // interrupts = <2 2 0>; 215 // interrupt-parent = <&mpc5200_pic>; 216 //}; 217 218 // PSC3 in CODEC mode example 219 //i2s@2400 { // PSC3 220 // compatible = "fsl,mpc5200-psc-i2s"; 221 // cell-index = <2>; 222 // reg = <0x2400 0x100>; 223 // interrupts = <2 3 0>; 224 // interrupt-parent = <&mpc5200_pic>; 225 //}; 226 227 // PSC4 in uart mode example 228 //serial@2600 { // PSC4 229 // device_type = "serial"; 230 // compatible = "fsl,mpc5200-psc-uart"; 231 // cell-index = <3>; 232 // reg = <0x2600 0x100>; 233 // interrupts = <2 11 0>; 234 // interrupt-parent = <&mpc5200_pic>; 235 //}; 236 237 // PSC5 in uart mode example 238 //serial@2800 { // PSC5 239 // device_type = "serial"; 240 // compatible = "fsl,mpc5200-psc-uart"; 241 // cell-index = <4>; 242 // reg = <0x2800 0x100>; 243 // interrupts = <2 12 0>; 244 // interrupt-parent = <&mpc5200_pic>; 245 //}; 246 247 // PSC6 in spi mode example 248 //spi@2c00 { // PSC6 249 // compatible = "fsl,mpc5200-psc-spi"; 250 // cell-index = <5>; 251 // reg = <0x2c00 0x100>; 252 // interrupts = <2 4 0>; 253 // interrupt-parent = <&mpc5200_pic>; 254 //}; 255 256 ethernet@3000 { 257 device_type = "network"; 258 compatible = "fsl,mpc5200-fec"; 259 reg = <0x3000 0x400>; 260 local-mac-address = [ 00 00 00 00 00 00 ]; 261 interrupts = <2 5 0>; 262 interrupt-parent = <&mpc5200_pic>; 263 phy-handle = <&phy0>; 264 }; 265 266 mdio@3000 { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 compatible = "fsl,mpc5200-mdio"; 270 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 271 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 272 interrupt-parent = <&mpc5200_pic>; 273 274 phy0: ethernet-phy@1 { 275 device_type = "ethernet-phy"; 276 reg = <1>; 277 }; 278 }; 279 280 ata@3a00 { 281 device_type = "ata"; 282 compatible = "fsl,mpc5200-ata"; 283 reg = <0x3a00 0x100>; 284 interrupts = <2 7 0>; 285 interrupt-parent = <&mpc5200_pic>; 286 }; 287 288 i2c@3d00 { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 292 cell-index = <0>; 293 reg = <0x3d00 0x40>; 294 interrupts = <2 15 0>; 295 interrupt-parent = <&mpc5200_pic>; 296 fsl5200-clocking; 297 }; 298 299 i2c@3d40 { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 303 cell-index = <1>; 304 reg = <0x3d40 0x40>; 305 interrupts = <2 16 0>; 306 interrupt-parent = <&mpc5200_pic>; 307 fsl5200-clocking; 308 }; 309 sram@8000 { 310 compatible = "fsl,mpc5200-sram","sram"; 311 reg = <0x8000 0x4000>; 312 }; 313 }; 314 315 pci@f0000d00 { 316 #interrupt-cells = <1>; 317 #size-cells = <2>; 318 #address-cells = <3>; 319 device_type = "pci"; 320 compatible = "fsl,mpc5200-pci"; 321 reg = <0xf0000d00 0x100>; 322 interrupt-map-mask = <0xf800 0 0 7>; 323 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 324 0xc000 0 0 2 &mpc5200_pic 0 0 3 325 0xc000 0 0 3 &mpc5200_pic 0 0 3 326 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 327 clock-frequency = <0>; // From boot loader 328 interrupts = <2 8 0 2 9 0 2 10 0>; 329 interrupt-parent = <&mpc5200_pic>; 330 bus-range = <0 0>; 331 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 332 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 333 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 334 }; 335}; 336