1/* 2 * Keymile KMETER1 Device Tree Source 3 * 4 * 2008 DENX Software Engineering GmbH 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "KMETER1"; 16 compatible = "keymile,KMETER1"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet_piggy2; 22 ethernet1 = &enet_estar1; 23 ethernet2 = &enet_estar2; 24 ethernet3 = &enet_eth1; 25 ethernet4 = &enet_eth2; 26 ethernet5 = &enet_eth3; 27 ethernet6 = &enet_eth4; 28 serial0 = &serial0; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 PowerPC,8360@0 { 36 device_type = "cpu"; 37 reg = <0x0>; 38 d-cache-line-size = <32>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes 40 d-cache-size = <32768>; // L1, 32K 41 i-cache-size = <32768>; // L1, 32K 42 timebase-frequency = <0>; /* Filled in by U-Boot */ 43 bus-frequency = <0>; /* Filled in by U-Boot */ 44 clock-frequency = <0>; /* Filled in by U-Boot */ 45 }; 46 }; 47 48 memory { 49 device_type = "memory"; 50 reg = <0 0>; /* Filled in by U-Boot */ 51 }; 52 53 soc8360@e0000000 { 54 #address-cells = <1>; 55 #size-cells = <1>; 56 device_type = "soc"; 57 compatible = "fsl,mpc8360-immr", "simple-bus"; 58 ranges = <0x0 0xe0000000 0x00200000>; 59 reg = <0xe0000000 0x00000200>; 60 bus-frequency = <0>; /* Filled in by U-Boot */ 61 62 i2c@3000 { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 cell-index = <0>; 66 compatible = "fsl-i2c"; 67 reg = <0x3000 0x100>; 68 interrupts = <14 0x8>; 69 interrupt-parent = <&ipic>; 70 dfsrr; 71 }; 72 73 serial0: serial@4500 { 74 cell-index = <0>; 75 device_type = "serial"; 76 compatible = "ns16550"; 77 reg = <0x4500 0x100>; 78 clock-frequency = <264000000>; 79 interrupts = <9 0x8>; 80 interrupt-parent = <&ipic>; 81 }; 82 83 dma@82a8 { 84 #address-cells = <1>; 85 #size-cells = <1>; 86 compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; 87 reg = <0x82a8 4>; 88 ranges = <0 0x8100 0x1a8>; 89 interrupt-parent = <&ipic>; 90 interrupts = <71 8>; 91 cell-index = <0>; 92 dma-channel@0 { 93 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 94 reg = <0 0x80>; 95 interrupt-parent = <&ipic>; 96 interrupts = <71 8>; 97 }; 98 dma-channel@80 { 99 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 100 reg = <0x80 0x80>; 101 interrupt-parent = <&ipic>; 102 interrupts = <71 8>; 103 }; 104 dma-channel@100 { 105 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 106 reg = <0x100 0x80>; 107 interrupt-parent = <&ipic>; 108 interrupts = <71 8>; 109 }; 110 dma-channel@180 { 111 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 112 reg = <0x180 0x28>; 113 interrupt-parent = <&ipic>; 114 interrupts = <71 8>; 115 }; 116 }; 117 118 ipic: pic@700 { 119 #address-cells = <0>; 120 #interrupt-cells = <2>; 121 compatible = "fsl,pq2pro-pic", "fsl,ipic"; 122 interrupt-controller; 123 reg = <0x700 0x100>; 124 }; 125 126 par_io@1400 { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 reg = <0x1400 0x100>; 130 compatible = "fsl,mpc8360-par_io"; 131 num-ports = <7>; 132 133 pio_ucc1: ucc_pin@0 { 134 reg = <0>; 135 136 pio-map = < 137 /* port pin dir open_drain assignment has_irq */ 138 0 1 3 0 2 0 /* MDIO */ 139 0 2 1 0 1 0 /* MDC */ 140 141 0 3 1 0 1 0 /* TxD0 */ 142 0 4 1 0 1 0 /* TxD1 */ 143 0 5 1 0 1 0 /* TxD2 */ 144 0 6 1 0 1 0 /* TxD3 */ 145 0 9 2 0 1 0 /* RxD0 */ 146 0 10 2 0 1 0 /* RxD1 */ 147 0 11 2 0 1 0 /* RxD2 */ 148 0 12 2 0 1 0 /* RxD3 */ 149 0 7 1 0 1 0 /* TX_EN */ 150 0 8 1 0 1 0 /* TX_ER */ 151 0 15 2 0 1 0 /* RX_DV */ 152 0 16 2 0 1 0 /* RX_ER */ 153 0 0 2 0 1 0 /* RX_CLK */ 154 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ 155 2 8 2 0 1 0 /* GTX125 - CLK9 */ 156 >; 157 }; 158 159 pio_ucc2: ucc_pin@1 { 160 reg = <1>; 161 162 pio-map = < 163 /* port pin dir open_drain assignment has_irq */ 164 0 1 3 0 2 0 /* MDIO */ 165 0 2 1 0 1 0 /* MDC */ 166 167 0 17 1 0 1 0 /* TxD0 */ 168 0 18 1 0 1 0 /* TxD1 */ 169 0 19 1 0 1 0 /* TxD2 */ 170 0 20 1 0 1 0 /* TxD3 */ 171 0 23 2 0 1 0 /* RxD0 */ 172 0 24 2 0 1 0 /* RxD1 */ 173 0 25 2 0 1 0 /* RxD2 */ 174 0 26 2 0 1 0 /* RxD3 */ 175 0 21 1 0 1 0 /* TX_EN */ 176 0 22 1 0 1 0 /* TX_ER */ 177 0 29 2 0 1 0 /* RX_DV */ 178 0 30 2 0 1 0 /* RX_ER */ 179 0 31 2 0 1 0 /* RX_CLK */ 180 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ 181 2 3 2 0 1 0 /* GTX125 - CLK4 */ 182 >; 183 }; 184 185 pio_ucc4: ucc_pin@3 { 186 reg = <3>; 187 188 pio-map = < 189 /* port pin dir open_drain assignment has_irq */ 190 0 1 3 0 2 0 /* MDIO */ 191 0 2 1 0 1 0 /* MDC */ 192 193 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ 194 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ 195 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ 196 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ 197 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ 198 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ 199 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ 200 201 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ 202 >; 203 }; 204 205 pio_ucc5: ucc_pin@4 { 206 reg = <4>; 207 208 pio-map = < 209 /* port pin dir open_drain assignment has_irq */ 210 0 1 3 0 2 0 /* MDIO */ 211 0 2 1 0 1 0 /* MDC */ 212 213 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ 214 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ 215 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ 216 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ 217 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ 218 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ 219 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ 220 >; 221 }; 222 223 pio_ucc6: ucc_pin@5 { 224 reg = <5>; 225 226 pio-map = < 227 /* port pin dir open_drain assignment has_irq */ 228 0 1 3 0 2 0 /* MDIO */ 229 0 2 1 0 1 0 /* MDC */ 230 231 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ 232 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ 233 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ 234 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ 235 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ 236 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ 237 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ 238 >; 239 }; 240 241 pio_ucc7: ucc_pin@6 { 242 reg = <6>; 243 244 pio-map = < 245 /* port pin dir open_drain assignment has_irq */ 246 0 1 3 0 2 0 /* MDIO */ 247 0 2 1 0 1 0 /* MDC */ 248 249 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ 250 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ 251 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ 252 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ 253 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ 254 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ 255 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ 256 >; 257 }; 258 259 pio_ucc8: ucc_pin@7 { 260 reg = <7>; 261 262 pio-map = < 263 /* port pin dir open_drain assignment has_irq */ 264 0 1 3 0 2 0 /* MDIO */ 265 0 2 1 0 1 0 /* MDC */ 266 267 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ 268 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ 269 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ 270 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ 271 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ 272 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ 273 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ 274 275 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ 276 >; 277 }; 278 279 }; 280 281 qe@100000 { 282 #address-cells = <1>; 283 #size-cells = <1>; 284 compatible = "fsl,qe"; 285 ranges = <0x0 0x100000 0x100000>; 286 reg = <0x100000 0x480>; 287 clock-frequency = <0>; /* Filled in by U-Boot */ 288 brg-frequency = <0>; /* Filled in by U-Boot */ 289 bus-frequency = <0>; /* Filled in by U-Boot */ 290 291 muram@10000 { 292 #address-cells = <1>; 293 #size-cells = <1>; 294 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 295 ranges = <0x0 0x00010000 0x0000c000>; 296 297 data-only@0 { 298 compatible = "fsl,qe-muram-data", 299 "fsl,cpm-muram-data"; 300 reg = <0x0 0xc000>; 301 }; 302 }; 303 304 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ 305 enet_estar1: ucc@2000 { 306 device_type = "network"; 307 compatible = "ucc_geth"; 308 cell-index = <1>; 309 reg = <0x2000 0x200>; 310 interrupts = <32>; 311 interrupt-parent = <&qeic>; 312 local-mac-address = [ 00 00 00 00 00 00 ]; 313 rx-clock-name = "none"; 314 tx-clock-name = "clk9"; 315 phy-handle = <&phy_estar1>; 316 phy-connection-type = "rgmii-id"; 317 pio-handle = <&pio_ucc1>; 318 }; 319 320 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ 321 enet_estar2: ucc@3000 { 322 device_type = "network"; 323 compatible = "ucc_geth"; 324 cell-index = <2>; 325 reg = <0x3000 0x200>; 326 interrupts = <33>; 327 interrupt-parent = <&qeic>; 328 local-mac-address = [ 00 00 00 00 00 00 ]; 329 rx-clock-name = "none"; 330 tx-clock-name = "clk4"; 331 phy-handle = <&phy_estar2>; 332 phy-connection-type = "rgmii-id"; 333 pio-handle = <&pio_ucc2>; 334 }; 335 336 /* Piggy2 (UCC4, MDIO 0x00, RMII) */ 337 enet_piggy2: ucc@3200 { 338 device_type = "network"; 339 compatible = "ucc_geth"; 340 cell-index = <4>; 341 reg = <0x3200 0x200>; 342 interrupts = <35>; 343 interrupt-parent = <&qeic>; 344 local-mac-address = [ 00 00 00 00 00 00 ]; 345 rx-clock-name = "none"; 346 tx-clock-name = "clk17"; 347 phy-handle = <&phy_piggy2>; 348 phy-connection-type = "rmii"; 349 pio-handle = <&pio_ucc4>; 350 }; 351 352 /* Eth-1 (UCC5, MDIO 0x08, RMII) */ 353 enet_eth1: ucc@2400 { 354 device_type = "network"; 355 compatible = "ucc_geth"; 356 cell-index = <5>; 357 reg = <0x2400 0x200>; 358 interrupts = <40>; 359 interrupt-parent = <&qeic>; 360 local-mac-address = [ 00 00 00 00 00 00 ]; 361 rx-clock-name = "none"; 362 tx-clock-name = "clk16"; 363 phy-handle = <&phy_eth1>; 364 phy-connection-type = "rmii"; 365 pio-handle = <&pio_ucc5>; 366 }; 367 368 /* Eth-2 (UCC6, MDIO 0x09, RMII) */ 369 enet_eth2: ucc@3400 { 370 device_type = "network"; 371 compatible = "ucc_geth"; 372 cell-index = <6>; 373 reg = <0x3400 0x200>; 374 interrupts = <41>; 375 interrupt-parent = <&qeic>; 376 local-mac-address = [ 00 00 00 00 00 00 ]; 377 rx-clock-name = "none"; 378 tx-clock-name = "clk16"; 379 phy-handle = <&phy_eth2>; 380 phy-connection-type = "rmii"; 381 pio-handle = <&pio_ucc6>; 382 }; 383 384 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ 385 enet_eth3: ucc@2600 { 386 device_type = "network"; 387 compatible = "ucc_geth"; 388 cell-index = <7>; 389 reg = <0x2600 0x200>; 390 interrupts = <42>; 391 interrupt-parent = <&qeic>; 392 local-mac-address = [ 00 00 00 00 00 00 ]; 393 rx-clock-name = "none"; 394 tx-clock-name = "clk16"; 395 phy-handle = <&phy_eth3>; 396 phy-connection-type = "rmii"; 397 pio-handle = <&pio_ucc7>; 398 }; 399 400 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ 401 enet_eth4: ucc@3600 { 402 device_type = "network"; 403 compatible = "ucc_geth"; 404 cell-index = <8>; 405 reg = <0x3600 0x200>; 406 interrupts = <43>; 407 interrupt-parent = <&qeic>; 408 local-mac-address = [ 00 00 00 00 00 00 ]; 409 rx-clock-name = "none"; 410 tx-clock-name = "clk16"; 411 phy-handle = <&phy_eth4>; 412 phy-connection-type = "rmii"; 413 pio-handle = <&pio_ucc8>; 414 }; 415 416 mdio@3320 { 417 #address-cells = <1>; 418 #size-cells = <0>; 419 reg = <0x3320 0x18>; 420 compatible = "fsl,ucc-mdio"; 421 422 /* Piggy2 (UCC4, MDIO 0x00, RMII) */ 423 phy_piggy2: ethernet-phy@00 { 424 reg = <0x0>; 425 }; 426 427 /* Eth-1 (UCC5, MDIO 0x08, RMII) */ 428 phy_eth1: ethernet-phy@08 { 429 reg = <0x08>; 430 }; 431 432 /* Eth-2 (UCC6, MDIO 0x09, RMII) */ 433 phy_eth2: ethernet-phy@09 { 434 reg = <0x09>; 435 }; 436 437 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ 438 phy_eth3: ethernet-phy@0a { 439 reg = <0x0a>; 440 }; 441 442 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ 443 phy_eth4: ethernet-phy@0b { 444 reg = <0x0b>; 445 }; 446 447 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ 448 phy_estar1: ethernet-phy@10 { 449 interrupt-parent = <&ipic>; 450 interrupts = <17 0x8>; 451 reg = <0x10>; 452 }; 453 454 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ 455 phy_estar2: ethernet-phy@11 { 456 interrupt-parent = <&ipic>; 457 interrupts = <18 0x8>; 458 reg = <0x11>; 459 }; 460 }; 461 462 qeic: interrupt-controller@80 { 463 interrupt-controller; 464 compatible = "fsl,qe-ic"; 465 #address-cells = <0>; 466 #interrupt-cells = <1>; 467 reg = <0x80 0x80>; 468 interrupts = <32 8 33 8>; 469 interrupt-parent = <&ipic>; 470 }; 471 }; 472 }; 473 474 localbus@e0005000 { 475 #address-cells = <2>; 476 #size-cells = <1>; 477 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", 478 "simple-bus"; 479 reg = <0xe0005000 0xd8>; 480 ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */ 481 482 flash@f0000000,0 { 483 compatible = "cfi-flash"; 484 /* 485 * The Intel P30 chip has 2 non-identical chips on 486 * one die, so we need to define 2 seperate regions 487 * that are scanned by physmap_of independantly. 488 */ 489 reg = <0 0x00000000 0x02000000 490 0 0x02000000 0x02000000>; /* Filled in by U-Boot */ 491 bank-width = <2>; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 partition@0 { 495 label = "u-boot"; 496 reg = <0 0x40000>; 497 }; 498 partition@40000 { 499 label = "env"; 500 reg = <0x40000 0x40000>; 501 }; 502 partition@80000 { 503 label = "dtb"; 504 reg = <0x80000 0x20000>; 505 }; 506 partition@a0000 { 507 label = "kernel"; 508 reg = <0xa0000 0x300000>; 509 }; 510 partition@3a0000 { 511 label = "ramdisk"; 512 reg = <0x3a0000 0x800000>; 513 }; 514 partition@ba0000 { 515 label = "user"; 516 reg = <0xba0000 0x3460000>; 517 }; 518 }; 519 }; 520}; 521