18159df72SHeiko Schocher/* 28159df72SHeiko Schocher * Keymile KMETER1 Device Tree Source 38159df72SHeiko Schocher * 493e2b95cSHolger Brunck * 2008-2011 DENX Software Engineering GmbH 58159df72SHeiko Schocher * 68159df72SHeiko Schocher * This program is free software; you can redistribute it and/or modify it 78159df72SHeiko Schocher * under the terms of the GNU General Public License as published by the 88159df72SHeiko Schocher * Free Software Foundation; either version 2 of the License, or (at your 98159df72SHeiko Schocher * option) any later version. 108159df72SHeiko Schocher */ 118159df72SHeiko Schocher 128159df72SHeiko Schocher/dts-v1/; 138159df72SHeiko Schocher 148159df72SHeiko Schocher/ { 158159df72SHeiko Schocher model = "KMETER1"; 168159df72SHeiko Schocher compatible = "keymile,KMETER1"; 178159df72SHeiko Schocher #address-cells = <1>; 188159df72SHeiko Schocher #size-cells = <1>; 198159df72SHeiko Schocher 208159df72SHeiko Schocher aliases { 218159df72SHeiko Schocher ethernet0 = &enet_piggy2; 228159df72SHeiko Schocher ethernet1 = &enet_estar1; 238159df72SHeiko Schocher ethernet2 = &enet_estar2; 248159df72SHeiko Schocher ethernet3 = &enet_eth1; 258159df72SHeiko Schocher ethernet4 = &enet_eth2; 268159df72SHeiko Schocher ethernet5 = &enet_eth3; 278159df72SHeiko Schocher ethernet6 = &enet_eth4; 288159df72SHeiko Schocher serial0 = &serial0; 298159df72SHeiko Schocher }; 308159df72SHeiko Schocher 318159df72SHeiko Schocher cpus { 328159df72SHeiko Schocher #address-cells = <1>; 338159df72SHeiko Schocher #size-cells = <0>; 348159df72SHeiko Schocher 358159df72SHeiko Schocher PowerPC,8360@0 { 368159df72SHeiko Schocher device_type = "cpu"; 378159df72SHeiko Schocher reg = <0x0>; 388159df72SHeiko Schocher d-cache-line-size = <32>; // 32 bytes 398159df72SHeiko Schocher i-cache-line-size = <32>; // 32 bytes 408159df72SHeiko Schocher d-cache-size = <32768>; // L1, 32K 418159df72SHeiko Schocher i-cache-size = <32768>; // L1, 32K 428159df72SHeiko Schocher timebase-frequency = <0>; /* Filled in by U-Boot */ 438159df72SHeiko Schocher bus-frequency = <0>; /* Filled in by U-Boot */ 448159df72SHeiko Schocher clock-frequency = <0>; /* Filled in by U-Boot */ 458159df72SHeiko Schocher }; 468159df72SHeiko Schocher }; 478159df72SHeiko Schocher 488159df72SHeiko Schocher memory { 498159df72SHeiko Schocher device_type = "memory"; 508159df72SHeiko Schocher reg = <0 0>; /* Filled in by U-Boot */ 518159df72SHeiko Schocher }; 528159df72SHeiko Schocher 538159df72SHeiko Schocher soc8360@e0000000 { 548159df72SHeiko Schocher #address-cells = <1>; 558159df72SHeiko Schocher #size-cells = <1>; 568159df72SHeiko Schocher device_type = "soc"; 578159df72SHeiko Schocher compatible = "fsl,mpc8360-immr", "simple-bus"; 588159df72SHeiko Schocher ranges = <0x0 0xe0000000 0x00200000>; 598159df72SHeiko Schocher reg = <0xe0000000 0x00000200>; 608159df72SHeiko Schocher bus-frequency = <0>; /* Filled in by U-Boot */ 618159df72SHeiko Schocher 621f8a25d4SAnton Vorontsov pmc: power@b00 { 631f8a25d4SAnton Vorontsov compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; 641f8a25d4SAnton Vorontsov reg = <0xb00 0x100 0xa00 0x100>; 651f8a25d4SAnton Vorontsov interrupts = <80 0x8>; 661f8a25d4SAnton Vorontsov interrupt-parent = <&ipic>; 671f8a25d4SAnton Vorontsov }; 681f8a25d4SAnton Vorontsov 698159df72SHeiko Schocher i2c@3000 { 708159df72SHeiko Schocher #address-cells = <1>; 718159df72SHeiko Schocher #size-cells = <0>; 728159df72SHeiko Schocher cell-index = <0>; 7393e2b95cSHolger Brunck compatible = "fsl,mpc8313-i2c","fsl-i2c"; 748159df72SHeiko Schocher reg = <0x3000 0x100>; 758159df72SHeiko Schocher interrupts = <14 0x8>; 768159df72SHeiko Schocher interrupt-parent = <&ipic>; 7793e2b95cSHolger Brunck clock-frequency = <400000>; 788159df72SHeiko Schocher }; 798159df72SHeiko Schocher 808159df72SHeiko Schocher serial0: serial@4500 { 818159df72SHeiko Schocher cell-index = <0>; 828159df72SHeiko Schocher device_type = "serial"; 838159df72SHeiko Schocher compatible = "ns16550"; 848159df72SHeiko Schocher reg = <0x4500 0x100>; 858159df72SHeiko Schocher clock-frequency = <264000000>; 868159df72SHeiko Schocher interrupts = <9 0x8>; 878159df72SHeiko Schocher interrupt-parent = <&ipic>; 888159df72SHeiko Schocher }; 898159df72SHeiko Schocher 908159df72SHeiko Schocher dma@82a8 { 918159df72SHeiko Schocher #address-cells = <1>; 928159df72SHeiko Schocher #size-cells = <1>; 938159df72SHeiko Schocher compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; 948159df72SHeiko Schocher reg = <0x82a8 4>; 958159df72SHeiko Schocher ranges = <0 0x8100 0x1a8>; 968159df72SHeiko Schocher interrupt-parent = <&ipic>; 978159df72SHeiko Schocher interrupts = <71 8>; 988159df72SHeiko Schocher cell-index = <0>; 998159df72SHeiko Schocher dma-channel@0 { 1008159df72SHeiko Schocher compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 1018159df72SHeiko Schocher reg = <0 0x80>; 1028159df72SHeiko Schocher interrupt-parent = <&ipic>; 1038159df72SHeiko Schocher interrupts = <71 8>; 1048159df72SHeiko Schocher }; 1058159df72SHeiko Schocher dma-channel@80 { 1068159df72SHeiko Schocher compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 1078159df72SHeiko Schocher reg = <0x80 0x80>; 1088159df72SHeiko Schocher interrupt-parent = <&ipic>; 1098159df72SHeiko Schocher interrupts = <71 8>; 1108159df72SHeiko Schocher }; 1118159df72SHeiko Schocher dma-channel@100 { 1128159df72SHeiko Schocher compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 1138159df72SHeiko Schocher reg = <0x100 0x80>; 1148159df72SHeiko Schocher interrupt-parent = <&ipic>; 1158159df72SHeiko Schocher interrupts = <71 8>; 1168159df72SHeiko Schocher }; 1178159df72SHeiko Schocher dma-channel@180 { 1188159df72SHeiko Schocher compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 1198159df72SHeiko Schocher reg = <0x180 0x28>; 1208159df72SHeiko Schocher interrupt-parent = <&ipic>; 1218159df72SHeiko Schocher interrupts = <71 8>; 1228159df72SHeiko Schocher }; 1238159df72SHeiko Schocher }; 1248159df72SHeiko Schocher 1258159df72SHeiko Schocher ipic: pic@700 { 1268159df72SHeiko Schocher #address-cells = <0>; 1278159df72SHeiko Schocher #interrupt-cells = <2>; 1288159df72SHeiko Schocher compatible = "fsl,pq2pro-pic", "fsl,ipic"; 1298159df72SHeiko Schocher interrupt-controller; 1308159df72SHeiko Schocher reg = <0x700 0x100>; 1318159df72SHeiko Schocher }; 1328159df72SHeiko Schocher 1338159df72SHeiko Schocher par_io@1400 { 1348159df72SHeiko Schocher #address-cells = <1>; 1358159df72SHeiko Schocher #size-cells = <0>; 1368159df72SHeiko Schocher reg = <0x1400 0x100>; 1378159df72SHeiko Schocher compatible = "fsl,mpc8360-par_io"; 1388159df72SHeiko Schocher num-ports = <7>; 1398159df72SHeiko Schocher 14093e2b95cSHolger Brunck qe_pio_c: gpio-controller@30 { 14193e2b95cSHolger Brunck #gpio-cells = <2>; 14293e2b95cSHolger Brunck compatible = "fsl,mpc8360-qe-pario-bank", 14393e2b95cSHolger Brunck "fsl,mpc8323-qe-pario-bank"; 14493e2b95cSHolger Brunck reg = <0x1430 0x18>; 14593e2b95cSHolger Brunck gpio-controller; 14693e2b95cSHolger Brunck }; 1478159df72SHeiko Schocher pio_ucc1: ucc_pin@0 { 1488159df72SHeiko Schocher reg = <0>; 1498159df72SHeiko Schocher 1508159df72SHeiko Schocher pio-map = < 1518159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 1528159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 1538159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 1548159df72SHeiko Schocher 1558159df72SHeiko Schocher 0 3 1 0 1 0 /* TxD0 */ 1568159df72SHeiko Schocher 0 4 1 0 1 0 /* TxD1 */ 1578159df72SHeiko Schocher 0 5 1 0 1 0 /* TxD2 */ 1588159df72SHeiko Schocher 0 6 1 0 1 0 /* TxD3 */ 1598159df72SHeiko Schocher 0 9 2 0 1 0 /* RxD0 */ 1608159df72SHeiko Schocher 0 10 2 0 1 0 /* RxD1 */ 1618159df72SHeiko Schocher 0 11 2 0 1 0 /* RxD2 */ 1628159df72SHeiko Schocher 0 12 2 0 1 0 /* RxD3 */ 1638159df72SHeiko Schocher 0 7 1 0 1 0 /* TX_EN */ 1648159df72SHeiko Schocher 0 8 1 0 1 0 /* TX_ER */ 1658159df72SHeiko Schocher 0 15 2 0 1 0 /* RX_DV */ 1668159df72SHeiko Schocher 0 16 2 0 1 0 /* RX_ER */ 1678159df72SHeiko Schocher 0 0 2 0 1 0 /* RX_CLK */ 1688159df72SHeiko Schocher 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ 1698159df72SHeiko Schocher 2 8 2 0 1 0 /* GTX125 - CLK9 */ 1708159df72SHeiko Schocher >; 1718159df72SHeiko Schocher }; 1728159df72SHeiko Schocher 1738159df72SHeiko Schocher pio_ucc2: ucc_pin@1 { 1748159df72SHeiko Schocher reg = <1>; 1758159df72SHeiko Schocher 1768159df72SHeiko Schocher pio-map = < 1778159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 1788159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 1798159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 1808159df72SHeiko Schocher 1818159df72SHeiko Schocher 0 17 1 0 1 0 /* TxD0 */ 1828159df72SHeiko Schocher 0 18 1 0 1 0 /* TxD1 */ 1838159df72SHeiko Schocher 0 19 1 0 1 0 /* TxD2 */ 1848159df72SHeiko Schocher 0 20 1 0 1 0 /* TxD3 */ 1858159df72SHeiko Schocher 0 23 2 0 1 0 /* RxD0 */ 1868159df72SHeiko Schocher 0 24 2 0 1 0 /* RxD1 */ 1878159df72SHeiko Schocher 0 25 2 0 1 0 /* RxD2 */ 1888159df72SHeiko Schocher 0 26 2 0 1 0 /* RxD3 */ 1898159df72SHeiko Schocher 0 21 1 0 1 0 /* TX_EN */ 1908159df72SHeiko Schocher 0 22 1 0 1 0 /* TX_ER */ 1918159df72SHeiko Schocher 0 29 2 0 1 0 /* RX_DV */ 1928159df72SHeiko Schocher 0 30 2 0 1 0 /* RX_ER */ 1938159df72SHeiko Schocher 0 31 2 0 1 0 /* RX_CLK */ 1948159df72SHeiko Schocher 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ 1958159df72SHeiko Schocher 2 3 2 0 1 0 /* GTX125 - CLK4 */ 1968159df72SHeiko Schocher >; 1978159df72SHeiko Schocher }; 1988159df72SHeiko Schocher 1998159df72SHeiko Schocher pio_ucc4: ucc_pin@3 { 2008159df72SHeiko Schocher reg = <3>; 2018159df72SHeiko Schocher 2028159df72SHeiko Schocher pio-map = < 2038159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 2048159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 2058159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 2068159df72SHeiko Schocher 2078159df72SHeiko Schocher 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ 2088159df72SHeiko Schocher 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ 2098159df72SHeiko Schocher 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ 2108159df72SHeiko Schocher 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ 2118159df72SHeiko Schocher 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ 2128159df72SHeiko Schocher 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ 2138159df72SHeiko Schocher 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ 2148159df72SHeiko Schocher 2158159df72SHeiko Schocher 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ 2168159df72SHeiko Schocher >; 2178159df72SHeiko Schocher }; 2188159df72SHeiko Schocher 2198159df72SHeiko Schocher pio_ucc5: ucc_pin@4 { 2208159df72SHeiko Schocher reg = <4>; 2218159df72SHeiko Schocher 2228159df72SHeiko Schocher pio-map = < 2238159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 2248159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 2258159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 2268159df72SHeiko Schocher 2278159df72SHeiko Schocher 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ 2288159df72SHeiko Schocher 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ 2298159df72SHeiko Schocher 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ 2308159df72SHeiko Schocher 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ 2318159df72SHeiko Schocher 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ 2328159df72SHeiko Schocher 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ 2338159df72SHeiko Schocher 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ 2348159df72SHeiko Schocher >; 2358159df72SHeiko Schocher }; 2368159df72SHeiko Schocher 2378159df72SHeiko Schocher pio_ucc6: ucc_pin@5 { 2388159df72SHeiko Schocher reg = <5>; 2398159df72SHeiko Schocher 2408159df72SHeiko Schocher pio-map = < 2418159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 2428159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 2438159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 2448159df72SHeiko Schocher 2458159df72SHeiko Schocher 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ 2468159df72SHeiko Schocher 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ 2478159df72SHeiko Schocher 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ 2488159df72SHeiko Schocher 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ 2498159df72SHeiko Schocher 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ 2508159df72SHeiko Schocher 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ 2518159df72SHeiko Schocher 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ 2528159df72SHeiko Schocher >; 2538159df72SHeiko Schocher }; 2548159df72SHeiko Schocher 2558159df72SHeiko Schocher pio_ucc7: ucc_pin@6 { 2568159df72SHeiko Schocher reg = <6>; 2578159df72SHeiko Schocher 2588159df72SHeiko Schocher pio-map = < 2598159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 2608159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 2618159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 2628159df72SHeiko Schocher 2638159df72SHeiko Schocher 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ 2648159df72SHeiko Schocher 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ 2658159df72SHeiko Schocher 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ 2668159df72SHeiko Schocher 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ 2678159df72SHeiko Schocher 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ 2688159df72SHeiko Schocher 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ 2698159df72SHeiko Schocher 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ 2708159df72SHeiko Schocher >; 2718159df72SHeiko Schocher }; 2728159df72SHeiko Schocher 2738159df72SHeiko Schocher pio_ucc8: ucc_pin@7 { 2748159df72SHeiko Schocher reg = <7>; 2758159df72SHeiko Schocher 2768159df72SHeiko Schocher pio-map = < 2778159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 2788159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 2798159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 2808159df72SHeiko Schocher 2818159df72SHeiko Schocher 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ 2828159df72SHeiko Schocher 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ 2838159df72SHeiko Schocher 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ 2848159df72SHeiko Schocher 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ 2858159df72SHeiko Schocher 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ 2868159df72SHeiko Schocher 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ 2878159df72SHeiko Schocher 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ 2888159df72SHeiko Schocher 2898159df72SHeiko Schocher 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ 2908159df72SHeiko Schocher >; 2918159df72SHeiko Schocher }; 2928159df72SHeiko Schocher 2938159df72SHeiko Schocher }; 2948159df72SHeiko Schocher 2958159df72SHeiko Schocher qe@100000 { 2968159df72SHeiko Schocher #address-cells = <1>; 2978159df72SHeiko Schocher #size-cells = <1>; 2988159df72SHeiko Schocher compatible = "fsl,qe"; 2998159df72SHeiko Schocher ranges = <0x0 0x100000 0x100000>; 3008159df72SHeiko Schocher reg = <0x100000 0x480>; 3018159df72SHeiko Schocher clock-frequency = <0>; /* Filled in by U-Boot */ 3028159df72SHeiko Schocher brg-frequency = <0>; /* Filled in by U-Boot */ 3038159df72SHeiko Schocher bus-frequency = <0>; /* Filled in by U-Boot */ 3048159df72SHeiko Schocher 3058159df72SHeiko Schocher muram@10000 { 3068159df72SHeiko Schocher #address-cells = <1>; 3078159df72SHeiko Schocher #size-cells = <1>; 3088159df72SHeiko Schocher compatible = "fsl,qe-muram", "fsl,cpm-muram"; 3098159df72SHeiko Schocher ranges = <0x0 0x00010000 0x0000c000>; 3108159df72SHeiko Schocher 3118159df72SHeiko Schocher data-only@0 { 3128159df72SHeiko Schocher compatible = "fsl,qe-muram-data", 3138159df72SHeiko Schocher "fsl,cpm-muram-data"; 3148159df72SHeiko Schocher reg = <0x0 0xc000>; 3158159df72SHeiko Schocher }; 3168159df72SHeiko Schocher }; 3178159df72SHeiko Schocher 3188159df72SHeiko Schocher /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ 3198159df72SHeiko Schocher enet_estar1: ucc@2000 { 3208159df72SHeiko Schocher device_type = "network"; 3218159df72SHeiko Schocher compatible = "ucc_geth"; 3228159df72SHeiko Schocher cell-index = <1>; 3238159df72SHeiko Schocher reg = <0x2000 0x200>; 3248159df72SHeiko Schocher interrupts = <32>; 3258159df72SHeiko Schocher interrupt-parent = <&qeic>; 3268159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3278159df72SHeiko Schocher rx-clock-name = "none"; 3288159df72SHeiko Schocher tx-clock-name = "clk9"; 3298159df72SHeiko Schocher phy-handle = <&phy_estar1>; 3308159df72SHeiko Schocher phy-connection-type = "rgmii-id"; 3318159df72SHeiko Schocher pio-handle = <&pio_ucc1>; 3328159df72SHeiko Schocher }; 3338159df72SHeiko Schocher 3348159df72SHeiko Schocher /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ 3358159df72SHeiko Schocher enet_estar2: ucc@3000 { 3368159df72SHeiko Schocher device_type = "network"; 3378159df72SHeiko Schocher compatible = "ucc_geth"; 3388159df72SHeiko Schocher cell-index = <2>; 3398159df72SHeiko Schocher reg = <0x3000 0x200>; 3408159df72SHeiko Schocher interrupts = <33>; 3418159df72SHeiko Schocher interrupt-parent = <&qeic>; 3428159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3438159df72SHeiko Schocher rx-clock-name = "none"; 3448159df72SHeiko Schocher tx-clock-name = "clk4"; 3458159df72SHeiko Schocher phy-handle = <&phy_estar2>; 3468159df72SHeiko Schocher phy-connection-type = "rgmii-id"; 3478159df72SHeiko Schocher pio-handle = <&pio_ucc2>; 3488159df72SHeiko Schocher }; 3498159df72SHeiko Schocher 3508159df72SHeiko Schocher /* Piggy2 (UCC4, MDIO 0x00, RMII) */ 3518159df72SHeiko Schocher enet_piggy2: ucc@3200 { 3528159df72SHeiko Schocher device_type = "network"; 3538159df72SHeiko Schocher compatible = "ucc_geth"; 3548159df72SHeiko Schocher cell-index = <4>; 3558159df72SHeiko Schocher reg = <0x3200 0x200>; 3568159df72SHeiko Schocher interrupts = <35>; 3578159df72SHeiko Schocher interrupt-parent = <&qeic>; 3588159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3598159df72SHeiko Schocher rx-clock-name = "none"; 3608159df72SHeiko Schocher tx-clock-name = "clk17"; 3618159df72SHeiko Schocher phy-handle = <&phy_piggy2>; 3628159df72SHeiko Schocher phy-connection-type = "rmii"; 3638159df72SHeiko Schocher pio-handle = <&pio_ucc4>; 3648159df72SHeiko Schocher }; 3658159df72SHeiko Schocher 3668159df72SHeiko Schocher /* Eth-1 (UCC5, MDIO 0x08, RMII) */ 3678159df72SHeiko Schocher enet_eth1: ucc@2400 { 3688159df72SHeiko Schocher device_type = "network"; 3698159df72SHeiko Schocher compatible = "ucc_geth"; 3708159df72SHeiko Schocher cell-index = <5>; 3718159df72SHeiko Schocher reg = <0x2400 0x200>; 3728159df72SHeiko Schocher interrupts = <40>; 3738159df72SHeiko Schocher interrupt-parent = <&qeic>; 3748159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3758159df72SHeiko Schocher rx-clock-name = "none"; 3768159df72SHeiko Schocher tx-clock-name = "clk16"; 3778159df72SHeiko Schocher phy-handle = <&phy_eth1>; 3788159df72SHeiko Schocher phy-connection-type = "rmii"; 3798159df72SHeiko Schocher pio-handle = <&pio_ucc5>; 3808159df72SHeiko Schocher }; 3818159df72SHeiko Schocher 3828159df72SHeiko Schocher /* Eth-2 (UCC6, MDIO 0x09, RMII) */ 3838159df72SHeiko Schocher enet_eth2: ucc@3400 { 3848159df72SHeiko Schocher device_type = "network"; 3858159df72SHeiko Schocher compatible = "ucc_geth"; 3868159df72SHeiko Schocher cell-index = <6>; 3878159df72SHeiko Schocher reg = <0x3400 0x200>; 3888159df72SHeiko Schocher interrupts = <41>; 3898159df72SHeiko Schocher interrupt-parent = <&qeic>; 3908159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3918159df72SHeiko Schocher rx-clock-name = "none"; 3928159df72SHeiko Schocher tx-clock-name = "clk16"; 3938159df72SHeiko Schocher phy-handle = <&phy_eth2>; 3948159df72SHeiko Schocher phy-connection-type = "rmii"; 3958159df72SHeiko Schocher pio-handle = <&pio_ucc6>; 3968159df72SHeiko Schocher }; 3978159df72SHeiko Schocher 3988159df72SHeiko Schocher /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ 3998159df72SHeiko Schocher enet_eth3: ucc@2600 { 4008159df72SHeiko Schocher device_type = "network"; 4018159df72SHeiko Schocher compatible = "ucc_geth"; 4028159df72SHeiko Schocher cell-index = <7>; 4038159df72SHeiko Schocher reg = <0x2600 0x200>; 4048159df72SHeiko Schocher interrupts = <42>; 4058159df72SHeiko Schocher interrupt-parent = <&qeic>; 4068159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 4078159df72SHeiko Schocher rx-clock-name = "none"; 4088159df72SHeiko Schocher tx-clock-name = "clk16"; 4098159df72SHeiko Schocher phy-handle = <&phy_eth3>; 4108159df72SHeiko Schocher phy-connection-type = "rmii"; 4118159df72SHeiko Schocher pio-handle = <&pio_ucc7>; 4128159df72SHeiko Schocher }; 4138159df72SHeiko Schocher 4148159df72SHeiko Schocher /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ 4158159df72SHeiko Schocher enet_eth4: ucc@3600 { 4168159df72SHeiko Schocher device_type = "network"; 4178159df72SHeiko Schocher compatible = "ucc_geth"; 4188159df72SHeiko Schocher cell-index = <8>; 4198159df72SHeiko Schocher reg = <0x3600 0x200>; 4208159df72SHeiko Schocher interrupts = <43>; 4218159df72SHeiko Schocher interrupt-parent = <&qeic>; 4228159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 4238159df72SHeiko Schocher rx-clock-name = "none"; 4248159df72SHeiko Schocher tx-clock-name = "clk16"; 4258159df72SHeiko Schocher phy-handle = <&phy_eth4>; 4268159df72SHeiko Schocher phy-connection-type = "rmii"; 4278159df72SHeiko Schocher pio-handle = <&pio_ucc8>; 4288159df72SHeiko Schocher }; 4298159df72SHeiko Schocher 4308159df72SHeiko Schocher mdio@3320 { 4318159df72SHeiko Schocher #address-cells = <1>; 4328159df72SHeiko Schocher #size-cells = <0>; 4338159df72SHeiko Schocher reg = <0x3320 0x18>; 4348159df72SHeiko Schocher compatible = "fsl,ucc-mdio"; 4358159df72SHeiko Schocher 4368159df72SHeiko Schocher /* Piggy2 (UCC4, MDIO 0x00, RMII) */ 4378159df72SHeiko Schocher phy_piggy2: ethernet-phy@00 { 4388159df72SHeiko Schocher reg = <0x0>; 4398159df72SHeiko Schocher }; 4408159df72SHeiko Schocher 4418159df72SHeiko Schocher /* Eth-1 (UCC5, MDIO 0x08, RMII) */ 4428159df72SHeiko Schocher phy_eth1: ethernet-phy@08 { 4438159df72SHeiko Schocher reg = <0x08>; 4448159df72SHeiko Schocher }; 4458159df72SHeiko Schocher 4468159df72SHeiko Schocher /* Eth-2 (UCC6, MDIO 0x09, RMII) */ 4478159df72SHeiko Schocher phy_eth2: ethernet-phy@09 { 4488159df72SHeiko Schocher reg = <0x09>; 4498159df72SHeiko Schocher }; 4508159df72SHeiko Schocher 4518159df72SHeiko Schocher /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ 4528159df72SHeiko Schocher phy_eth3: ethernet-phy@0a { 4538159df72SHeiko Schocher reg = <0x0a>; 4548159df72SHeiko Schocher }; 4558159df72SHeiko Schocher 4568159df72SHeiko Schocher /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ 4578159df72SHeiko Schocher phy_eth4: ethernet-phy@0b { 4588159df72SHeiko Schocher reg = <0x0b>; 4598159df72SHeiko Schocher }; 4608159df72SHeiko Schocher 4618159df72SHeiko Schocher /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ 4628159df72SHeiko Schocher phy_estar1: ethernet-phy@10 { 4638159df72SHeiko Schocher interrupt-parent = <&ipic>; 4648159df72SHeiko Schocher interrupts = <17 0x8>; 4658159df72SHeiko Schocher reg = <0x10>; 4668159df72SHeiko Schocher }; 4678159df72SHeiko Schocher 4688159df72SHeiko Schocher /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ 4698159df72SHeiko Schocher phy_estar2: ethernet-phy@11 { 4708159df72SHeiko Schocher interrupt-parent = <&ipic>; 4718159df72SHeiko Schocher interrupts = <18 0x8>; 4728159df72SHeiko Schocher reg = <0x11>; 4738159df72SHeiko Schocher }; 4748159df72SHeiko Schocher }; 4758159df72SHeiko Schocher 4768159df72SHeiko Schocher qeic: interrupt-controller@80 { 4778159df72SHeiko Schocher interrupt-controller; 4788159df72SHeiko Schocher compatible = "fsl,qe-ic"; 4798159df72SHeiko Schocher #address-cells = <0>; 4808159df72SHeiko Schocher #interrupt-cells = <1>; 4818159df72SHeiko Schocher reg = <0x80 0x80>; 48293e2b95cSHolger Brunck big-endian; 48393e2b95cSHolger Brunck interrupts = < 48493e2b95cSHolger Brunck 32 0x8 48593e2b95cSHolger Brunck 33 0x8 48693e2b95cSHolger Brunck 34 0x8 48793e2b95cSHolger Brunck 35 0x8 48893e2b95cSHolger Brunck 40 0x8 48993e2b95cSHolger Brunck 41 0x8 49093e2b95cSHolger Brunck 42 0x8 49193e2b95cSHolger Brunck 43 0x8 49293e2b95cSHolger Brunck >; 4938159df72SHeiko Schocher interrupt-parent = <&ipic>; 4948159df72SHeiko Schocher }; 4958159df72SHeiko Schocher }; 4968159df72SHeiko Schocher }; 4978159df72SHeiko Schocher 4988159df72SHeiko Schocher localbus@e0005000 { 4998159df72SHeiko Schocher #address-cells = <2>; 5008159df72SHeiko Schocher #size-cells = <1>; 5018159df72SHeiko Schocher compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", 5028159df72SHeiko Schocher "simple-bus"; 5038159df72SHeiko Schocher reg = <0xe0005000 0xd8>; 50493e2b95cSHolger Brunck ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */ 50593e2b95cSHolger Brunck 1 0 0xe8000000 0x01000000 /* LB 1 */ 50693e2b95cSHolger Brunck 3 0 0xa0000000 0x10000000>; /* LB 3 */ 5078159df72SHeiko Schocher 50893e2b95cSHolger Brunck flash@0,0 { 5098159df72SHeiko Schocher compatible = "cfi-flash"; 51093e2b95cSHolger Brunck reg = <0 0 0x04000000>; 5118159df72SHeiko Schocher #address-cells = <1>; 5128159df72SHeiko Schocher #size-cells = <1>; 51393e2b95cSHolger Brunck bank-width = <2>; 51493e2b95cSHolger Brunck partition@0 { /* 768KB */ 5158159df72SHeiko Schocher label = "u-boot"; 51693e2b95cSHolger Brunck reg = <0 0xC0000>; 5178159df72SHeiko Schocher }; 51893e2b95cSHolger Brunck partition@c0000 { /* 128KB */ 5198159df72SHeiko Schocher label = "env"; 52093e2b95cSHolger Brunck reg = <0xC0000 0x20000>; 5218159df72SHeiko Schocher }; 52293e2b95cSHolger Brunck partition@e0000 { /* 128KB */ 52393e2b95cSHolger Brunck label = "envred"; 52493e2b95cSHolger Brunck reg = <0xE0000 0x20000>; 5258159df72SHeiko Schocher }; 52693e2b95cSHolger Brunck partition@100000 { /* 64512KB */ 52793e2b95cSHolger Brunck label = "ubi0"; 52893e2b95cSHolger Brunck reg = <0x100000 0x3F00000>; 5298159df72SHeiko Schocher }; 5308159df72SHeiko Schocher }; 5318159df72SHeiko Schocher }; 5328159df72SHeiko Schocher}; 533