18159df72SHeiko Schocher/* 28159df72SHeiko Schocher * Keymile KMETER1 Device Tree Source 38159df72SHeiko Schocher * 48159df72SHeiko Schocher * 2008 DENX Software Engineering GmbH 58159df72SHeiko Schocher * 68159df72SHeiko Schocher * This program is free software; you can redistribute it and/or modify it 78159df72SHeiko Schocher * under the terms of the GNU General Public License as published by the 88159df72SHeiko Schocher * Free Software Foundation; either version 2 of the License, or (at your 98159df72SHeiko Schocher * option) any later version. 108159df72SHeiko Schocher */ 118159df72SHeiko Schocher 128159df72SHeiko Schocher/dts-v1/; 138159df72SHeiko Schocher 148159df72SHeiko Schocher/ { 158159df72SHeiko Schocher model = "KMETER1"; 168159df72SHeiko Schocher compatible = "keymile,KMETER1"; 178159df72SHeiko Schocher #address-cells = <1>; 188159df72SHeiko Schocher #size-cells = <1>; 198159df72SHeiko Schocher 208159df72SHeiko Schocher aliases { 218159df72SHeiko Schocher ethernet0 = &enet_piggy2; 228159df72SHeiko Schocher ethernet1 = &enet_estar1; 238159df72SHeiko Schocher ethernet2 = &enet_estar2; 248159df72SHeiko Schocher ethernet3 = &enet_eth1; 258159df72SHeiko Schocher ethernet4 = &enet_eth2; 268159df72SHeiko Schocher ethernet5 = &enet_eth3; 278159df72SHeiko Schocher ethernet6 = &enet_eth4; 288159df72SHeiko Schocher serial0 = &serial0; 298159df72SHeiko Schocher }; 308159df72SHeiko Schocher 318159df72SHeiko Schocher cpus { 328159df72SHeiko Schocher #address-cells = <1>; 338159df72SHeiko Schocher #size-cells = <0>; 348159df72SHeiko Schocher 358159df72SHeiko Schocher PowerPC,8360@0 { 368159df72SHeiko Schocher device_type = "cpu"; 378159df72SHeiko Schocher reg = <0x0>; 388159df72SHeiko Schocher d-cache-line-size = <32>; // 32 bytes 398159df72SHeiko Schocher i-cache-line-size = <32>; // 32 bytes 408159df72SHeiko Schocher d-cache-size = <32768>; // L1, 32K 418159df72SHeiko Schocher i-cache-size = <32768>; // L1, 32K 428159df72SHeiko Schocher timebase-frequency = <0>; /* Filled in by U-Boot */ 438159df72SHeiko Schocher bus-frequency = <0>; /* Filled in by U-Boot */ 448159df72SHeiko Schocher clock-frequency = <0>; /* Filled in by U-Boot */ 458159df72SHeiko Schocher }; 468159df72SHeiko Schocher }; 478159df72SHeiko Schocher 488159df72SHeiko Schocher memory { 498159df72SHeiko Schocher device_type = "memory"; 508159df72SHeiko Schocher reg = <0 0>; /* Filled in by U-Boot */ 518159df72SHeiko Schocher }; 528159df72SHeiko Schocher 538159df72SHeiko Schocher soc8360@e0000000 { 548159df72SHeiko Schocher #address-cells = <1>; 558159df72SHeiko Schocher #size-cells = <1>; 568159df72SHeiko Schocher device_type = "soc"; 578159df72SHeiko Schocher compatible = "fsl,mpc8360-immr", "simple-bus"; 588159df72SHeiko Schocher ranges = <0x0 0xe0000000 0x00200000>; 598159df72SHeiko Schocher reg = <0xe0000000 0x00000200>; 608159df72SHeiko Schocher bus-frequency = <0>; /* Filled in by U-Boot */ 618159df72SHeiko Schocher 628159df72SHeiko Schocher i2c@3000 { 638159df72SHeiko Schocher #address-cells = <1>; 648159df72SHeiko Schocher #size-cells = <0>; 658159df72SHeiko Schocher cell-index = <0>; 668159df72SHeiko Schocher compatible = "fsl-i2c"; 678159df72SHeiko Schocher reg = <0x3000 0x100>; 688159df72SHeiko Schocher interrupts = <14 0x8>; 698159df72SHeiko Schocher interrupt-parent = <&ipic>; 708159df72SHeiko Schocher dfsrr; 718159df72SHeiko Schocher }; 728159df72SHeiko Schocher 738159df72SHeiko Schocher serial0: serial@4500 { 748159df72SHeiko Schocher cell-index = <0>; 758159df72SHeiko Schocher device_type = "serial"; 768159df72SHeiko Schocher compatible = "ns16550"; 778159df72SHeiko Schocher reg = <0x4500 0x100>; 788159df72SHeiko Schocher clock-frequency = <264000000>; 798159df72SHeiko Schocher interrupts = <9 0x8>; 808159df72SHeiko Schocher interrupt-parent = <&ipic>; 818159df72SHeiko Schocher }; 828159df72SHeiko Schocher 838159df72SHeiko Schocher dma@82a8 { 848159df72SHeiko Schocher #address-cells = <1>; 858159df72SHeiko Schocher #size-cells = <1>; 868159df72SHeiko Schocher compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; 878159df72SHeiko Schocher reg = <0x82a8 4>; 888159df72SHeiko Schocher ranges = <0 0x8100 0x1a8>; 898159df72SHeiko Schocher interrupt-parent = <&ipic>; 908159df72SHeiko Schocher interrupts = <71 8>; 918159df72SHeiko Schocher cell-index = <0>; 928159df72SHeiko Schocher dma-channel@0 { 938159df72SHeiko Schocher compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 948159df72SHeiko Schocher reg = <0 0x80>; 958159df72SHeiko Schocher interrupt-parent = <&ipic>; 968159df72SHeiko Schocher interrupts = <71 8>; 978159df72SHeiko Schocher }; 988159df72SHeiko Schocher dma-channel@80 { 998159df72SHeiko Schocher compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 1008159df72SHeiko Schocher reg = <0x80 0x80>; 1018159df72SHeiko Schocher interrupt-parent = <&ipic>; 1028159df72SHeiko Schocher interrupts = <71 8>; 1038159df72SHeiko Schocher }; 1048159df72SHeiko Schocher dma-channel@100 { 1058159df72SHeiko Schocher compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 1068159df72SHeiko Schocher reg = <0x100 0x80>; 1078159df72SHeiko Schocher interrupt-parent = <&ipic>; 1088159df72SHeiko Schocher interrupts = <71 8>; 1098159df72SHeiko Schocher }; 1108159df72SHeiko Schocher dma-channel@180 { 1118159df72SHeiko Schocher compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 1128159df72SHeiko Schocher reg = <0x180 0x28>; 1138159df72SHeiko Schocher interrupt-parent = <&ipic>; 1148159df72SHeiko Schocher interrupts = <71 8>; 1158159df72SHeiko Schocher }; 1168159df72SHeiko Schocher }; 1178159df72SHeiko Schocher 1188159df72SHeiko Schocher ipic: pic@700 { 1198159df72SHeiko Schocher #address-cells = <0>; 1208159df72SHeiko Schocher #interrupt-cells = <2>; 1218159df72SHeiko Schocher compatible = "fsl,pq2pro-pic", "fsl,ipic"; 1228159df72SHeiko Schocher interrupt-controller; 1238159df72SHeiko Schocher reg = <0x700 0x100>; 1248159df72SHeiko Schocher }; 1258159df72SHeiko Schocher 1268159df72SHeiko Schocher par_io@1400 { 1278159df72SHeiko Schocher #address-cells = <1>; 1288159df72SHeiko Schocher #size-cells = <0>; 1298159df72SHeiko Schocher reg = <0x1400 0x100>; 1308159df72SHeiko Schocher compatible = "fsl,mpc8360-par_io"; 1318159df72SHeiko Schocher num-ports = <7>; 1328159df72SHeiko Schocher 1338159df72SHeiko Schocher pio_ucc1: ucc_pin@0 { 1348159df72SHeiko Schocher reg = <0>; 1358159df72SHeiko Schocher 1368159df72SHeiko Schocher pio-map = < 1378159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 1388159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 1398159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 1408159df72SHeiko Schocher 1418159df72SHeiko Schocher 0 3 1 0 1 0 /* TxD0 */ 1428159df72SHeiko Schocher 0 4 1 0 1 0 /* TxD1 */ 1438159df72SHeiko Schocher 0 5 1 0 1 0 /* TxD2 */ 1448159df72SHeiko Schocher 0 6 1 0 1 0 /* TxD3 */ 1458159df72SHeiko Schocher 0 9 2 0 1 0 /* RxD0 */ 1468159df72SHeiko Schocher 0 10 2 0 1 0 /* RxD1 */ 1478159df72SHeiko Schocher 0 11 2 0 1 0 /* RxD2 */ 1488159df72SHeiko Schocher 0 12 2 0 1 0 /* RxD3 */ 1498159df72SHeiko Schocher 0 7 1 0 1 0 /* TX_EN */ 1508159df72SHeiko Schocher 0 8 1 0 1 0 /* TX_ER */ 1518159df72SHeiko Schocher 0 15 2 0 1 0 /* RX_DV */ 1528159df72SHeiko Schocher 0 16 2 0 1 0 /* RX_ER */ 1538159df72SHeiko Schocher 0 0 2 0 1 0 /* RX_CLK */ 1548159df72SHeiko Schocher 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ 1558159df72SHeiko Schocher 2 8 2 0 1 0 /* GTX125 - CLK9 */ 1568159df72SHeiko Schocher >; 1578159df72SHeiko Schocher }; 1588159df72SHeiko Schocher 1598159df72SHeiko Schocher pio_ucc2: ucc_pin@1 { 1608159df72SHeiko Schocher reg = <1>; 1618159df72SHeiko Schocher 1628159df72SHeiko Schocher pio-map = < 1638159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 1648159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 1658159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 1668159df72SHeiko Schocher 1678159df72SHeiko Schocher 0 17 1 0 1 0 /* TxD0 */ 1688159df72SHeiko Schocher 0 18 1 0 1 0 /* TxD1 */ 1698159df72SHeiko Schocher 0 19 1 0 1 0 /* TxD2 */ 1708159df72SHeiko Schocher 0 20 1 0 1 0 /* TxD3 */ 1718159df72SHeiko Schocher 0 23 2 0 1 0 /* RxD0 */ 1728159df72SHeiko Schocher 0 24 2 0 1 0 /* RxD1 */ 1738159df72SHeiko Schocher 0 25 2 0 1 0 /* RxD2 */ 1748159df72SHeiko Schocher 0 26 2 0 1 0 /* RxD3 */ 1758159df72SHeiko Schocher 0 21 1 0 1 0 /* TX_EN */ 1768159df72SHeiko Schocher 0 22 1 0 1 0 /* TX_ER */ 1778159df72SHeiko Schocher 0 29 2 0 1 0 /* RX_DV */ 1788159df72SHeiko Schocher 0 30 2 0 1 0 /* RX_ER */ 1798159df72SHeiko Schocher 0 31 2 0 1 0 /* RX_CLK */ 1808159df72SHeiko Schocher 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ 1818159df72SHeiko Schocher 2 3 2 0 1 0 /* GTX125 - CLK4 */ 1828159df72SHeiko Schocher >; 1838159df72SHeiko Schocher }; 1848159df72SHeiko Schocher 1858159df72SHeiko Schocher pio_ucc4: ucc_pin@3 { 1868159df72SHeiko Schocher reg = <3>; 1878159df72SHeiko Schocher 1888159df72SHeiko Schocher pio-map = < 1898159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 1908159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 1918159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 1928159df72SHeiko Schocher 1938159df72SHeiko Schocher 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ 1948159df72SHeiko Schocher 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ 1958159df72SHeiko Schocher 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ 1968159df72SHeiko Schocher 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ 1978159df72SHeiko Schocher 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ 1988159df72SHeiko Schocher 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ 1998159df72SHeiko Schocher 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ 2008159df72SHeiko Schocher 2018159df72SHeiko Schocher 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ 2028159df72SHeiko Schocher >; 2038159df72SHeiko Schocher }; 2048159df72SHeiko Schocher 2058159df72SHeiko Schocher pio_ucc5: ucc_pin@4 { 2068159df72SHeiko Schocher reg = <4>; 2078159df72SHeiko Schocher 2088159df72SHeiko Schocher pio-map = < 2098159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 2108159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 2118159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 2128159df72SHeiko Schocher 2138159df72SHeiko Schocher 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ 2148159df72SHeiko Schocher 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ 2158159df72SHeiko Schocher 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ 2168159df72SHeiko Schocher 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ 2178159df72SHeiko Schocher 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ 2188159df72SHeiko Schocher 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ 2198159df72SHeiko Schocher 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ 2208159df72SHeiko Schocher >; 2218159df72SHeiko Schocher }; 2228159df72SHeiko Schocher 2238159df72SHeiko Schocher pio_ucc6: ucc_pin@5 { 2248159df72SHeiko Schocher reg = <5>; 2258159df72SHeiko Schocher 2268159df72SHeiko Schocher pio-map = < 2278159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 2288159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 2298159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 2308159df72SHeiko Schocher 2318159df72SHeiko Schocher 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ 2328159df72SHeiko Schocher 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ 2338159df72SHeiko Schocher 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ 2348159df72SHeiko Schocher 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ 2358159df72SHeiko Schocher 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ 2368159df72SHeiko Schocher 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ 2378159df72SHeiko Schocher 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ 2388159df72SHeiko Schocher >; 2398159df72SHeiko Schocher }; 2408159df72SHeiko Schocher 2418159df72SHeiko Schocher pio_ucc7: ucc_pin@6 { 2428159df72SHeiko Schocher reg = <6>; 2438159df72SHeiko Schocher 2448159df72SHeiko Schocher pio-map = < 2458159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 2468159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 2478159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 2488159df72SHeiko Schocher 2498159df72SHeiko Schocher 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ 2508159df72SHeiko Schocher 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ 2518159df72SHeiko Schocher 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ 2528159df72SHeiko Schocher 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ 2538159df72SHeiko Schocher 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ 2548159df72SHeiko Schocher 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ 2558159df72SHeiko Schocher 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ 2568159df72SHeiko Schocher >; 2578159df72SHeiko Schocher }; 2588159df72SHeiko Schocher 2598159df72SHeiko Schocher pio_ucc8: ucc_pin@7 { 2608159df72SHeiko Schocher reg = <7>; 2618159df72SHeiko Schocher 2628159df72SHeiko Schocher pio-map = < 2638159df72SHeiko Schocher /* port pin dir open_drain assignment has_irq */ 2648159df72SHeiko Schocher 0 1 3 0 2 0 /* MDIO */ 2658159df72SHeiko Schocher 0 2 1 0 1 0 /* MDC */ 2668159df72SHeiko Schocher 2678159df72SHeiko Schocher 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ 2688159df72SHeiko Schocher 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ 2698159df72SHeiko Schocher 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ 2708159df72SHeiko Schocher 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ 2718159df72SHeiko Schocher 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ 2728159df72SHeiko Schocher 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ 2738159df72SHeiko Schocher 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ 2748159df72SHeiko Schocher 2758159df72SHeiko Schocher 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ 2768159df72SHeiko Schocher >; 2778159df72SHeiko Schocher }; 2788159df72SHeiko Schocher 2798159df72SHeiko Schocher }; 2808159df72SHeiko Schocher 2818159df72SHeiko Schocher qe@100000 { 2828159df72SHeiko Schocher #address-cells = <1>; 2838159df72SHeiko Schocher #size-cells = <1>; 2848159df72SHeiko Schocher compatible = "fsl,qe"; 2858159df72SHeiko Schocher ranges = <0x0 0x100000 0x100000>; 2868159df72SHeiko Schocher reg = <0x100000 0x480>; 2878159df72SHeiko Schocher clock-frequency = <0>; /* Filled in by U-Boot */ 2888159df72SHeiko Schocher brg-frequency = <0>; /* Filled in by U-Boot */ 2898159df72SHeiko Schocher bus-frequency = <0>; /* Filled in by U-Boot */ 2908159df72SHeiko Schocher 2918159df72SHeiko Schocher muram@10000 { 2928159df72SHeiko Schocher #address-cells = <1>; 2938159df72SHeiko Schocher #size-cells = <1>; 2948159df72SHeiko Schocher compatible = "fsl,qe-muram", "fsl,cpm-muram"; 2958159df72SHeiko Schocher ranges = <0x0 0x00010000 0x0000c000>; 2968159df72SHeiko Schocher 2978159df72SHeiko Schocher data-only@0 { 2988159df72SHeiko Schocher compatible = "fsl,qe-muram-data", 2998159df72SHeiko Schocher "fsl,cpm-muram-data"; 3008159df72SHeiko Schocher reg = <0x0 0xc000>; 3018159df72SHeiko Schocher }; 3028159df72SHeiko Schocher }; 3038159df72SHeiko Schocher 3048159df72SHeiko Schocher /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ 3058159df72SHeiko Schocher enet_estar1: ucc@2000 { 3068159df72SHeiko Schocher device_type = "network"; 3078159df72SHeiko Schocher compatible = "ucc_geth"; 3088159df72SHeiko Schocher cell-index = <1>; 3098159df72SHeiko Schocher reg = <0x2000 0x200>; 3108159df72SHeiko Schocher interrupts = <32>; 3118159df72SHeiko Schocher interrupt-parent = <&qeic>; 3128159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3138159df72SHeiko Schocher rx-clock-name = "none"; 3148159df72SHeiko Schocher tx-clock-name = "clk9"; 3158159df72SHeiko Schocher phy-handle = <&phy_estar1>; 3168159df72SHeiko Schocher phy-connection-type = "rgmii-id"; 3178159df72SHeiko Schocher pio-handle = <&pio_ucc1>; 3188159df72SHeiko Schocher }; 3198159df72SHeiko Schocher 3208159df72SHeiko Schocher /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ 3218159df72SHeiko Schocher enet_estar2: ucc@3000 { 3228159df72SHeiko Schocher device_type = "network"; 3238159df72SHeiko Schocher compatible = "ucc_geth"; 3248159df72SHeiko Schocher cell-index = <2>; 3258159df72SHeiko Schocher reg = <0x3000 0x200>; 3268159df72SHeiko Schocher interrupts = <33>; 3278159df72SHeiko Schocher interrupt-parent = <&qeic>; 3288159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3298159df72SHeiko Schocher rx-clock-name = "none"; 3308159df72SHeiko Schocher tx-clock-name = "clk4"; 3318159df72SHeiko Schocher phy-handle = <&phy_estar2>; 3328159df72SHeiko Schocher phy-connection-type = "rgmii-id"; 3338159df72SHeiko Schocher pio-handle = <&pio_ucc2>; 3348159df72SHeiko Schocher }; 3358159df72SHeiko Schocher 3368159df72SHeiko Schocher /* Piggy2 (UCC4, MDIO 0x00, RMII) */ 3378159df72SHeiko Schocher enet_piggy2: ucc@3200 { 3388159df72SHeiko Schocher device_type = "network"; 3398159df72SHeiko Schocher compatible = "ucc_geth"; 3408159df72SHeiko Schocher cell-index = <4>; 3418159df72SHeiko Schocher reg = <0x3200 0x200>; 3428159df72SHeiko Schocher interrupts = <35>; 3438159df72SHeiko Schocher interrupt-parent = <&qeic>; 3448159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3458159df72SHeiko Schocher rx-clock-name = "none"; 3468159df72SHeiko Schocher tx-clock-name = "clk17"; 3478159df72SHeiko Schocher phy-handle = <&phy_piggy2>; 3488159df72SHeiko Schocher phy-connection-type = "rmii"; 3498159df72SHeiko Schocher pio-handle = <&pio_ucc4>; 3508159df72SHeiko Schocher }; 3518159df72SHeiko Schocher 3528159df72SHeiko Schocher /* Eth-1 (UCC5, MDIO 0x08, RMII) */ 3538159df72SHeiko Schocher enet_eth1: ucc@2400 { 3548159df72SHeiko Schocher device_type = "network"; 3558159df72SHeiko Schocher compatible = "ucc_geth"; 3568159df72SHeiko Schocher cell-index = <5>; 3578159df72SHeiko Schocher reg = <0x2400 0x200>; 3588159df72SHeiko Schocher interrupts = <40>; 3598159df72SHeiko Schocher interrupt-parent = <&qeic>; 3608159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3618159df72SHeiko Schocher rx-clock-name = "none"; 3628159df72SHeiko Schocher tx-clock-name = "clk16"; 3638159df72SHeiko Schocher phy-handle = <&phy_eth1>; 3648159df72SHeiko Schocher phy-connection-type = "rmii"; 3658159df72SHeiko Schocher pio-handle = <&pio_ucc5>; 3668159df72SHeiko Schocher }; 3678159df72SHeiko Schocher 3688159df72SHeiko Schocher /* Eth-2 (UCC6, MDIO 0x09, RMII) */ 3698159df72SHeiko Schocher enet_eth2: ucc@3400 { 3708159df72SHeiko Schocher device_type = "network"; 3718159df72SHeiko Schocher compatible = "ucc_geth"; 3728159df72SHeiko Schocher cell-index = <6>; 3738159df72SHeiko Schocher reg = <0x3400 0x200>; 3748159df72SHeiko Schocher interrupts = <41>; 3758159df72SHeiko Schocher interrupt-parent = <&qeic>; 3768159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3778159df72SHeiko Schocher rx-clock-name = "none"; 3788159df72SHeiko Schocher tx-clock-name = "clk16"; 3798159df72SHeiko Schocher phy-handle = <&phy_eth2>; 3808159df72SHeiko Schocher phy-connection-type = "rmii"; 3818159df72SHeiko Schocher pio-handle = <&pio_ucc6>; 3828159df72SHeiko Schocher }; 3838159df72SHeiko Schocher 3848159df72SHeiko Schocher /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ 3858159df72SHeiko Schocher enet_eth3: ucc@2600 { 3868159df72SHeiko Schocher device_type = "network"; 3878159df72SHeiko Schocher compatible = "ucc_geth"; 3888159df72SHeiko Schocher cell-index = <7>; 3898159df72SHeiko Schocher reg = <0x2600 0x200>; 3908159df72SHeiko Schocher interrupts = <42>; 3918159df72SHeiko Schocher interrupt-parent = <&qeic>; 3928159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 3938159df72SHeiko Schocher rx-clock-name = "none"; 3948159df72SHeiko Schocher tx-clock-name = "clk16"; 3958159df72SHeiko Schocher phy-handle = <&phy_eth3>; 3968159df72SHeiko Schocher phy-connection-type = "rmii"; 3978159df72SHeiko Schocher pio-handle = <&pio_ucc7>; 3988159df72SHeiko Schocher }; 3998159df72SHeiko Schocher 4008159df72SHeiko Schocher /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ 4018159df72SHeiko Schocher enet_eth4: ucc@3600 { 4028159df72SHeiko Schocher device_type = "network"; 4038159df72SHeiko Schocher compatible = "ucc_geth"; 4048159df72SHeiko Schocher cell-index = <8>; 4058159df72SHeiko Schocher reg = <0x3600 0x200>; 4068159df72SHeiko Schocher interrupts = <43>; 4078159df72SHeiko Schocher interrupt-parent = <&qeic>; 4088159df72SHeiko Schocher local-mac-address = [ 00 00 00 00 00 00 ]; 4098159df72SHeiko Schocher rx-clock-name = "none"; 4108159df72SHeiko Schocher tx-clock-name = "clk16"; 4118159df72SHeiko Schocher phy-handle = <&phy_eth4>; 4128159df72SHeiko Schocher phy-connection-type = "rmii"; 4138159df72SHeiko Schocher pio-handle = <&pio_ucc8>; 4148159df72SHeiko Schocher }; 4158159df72SHeiko Schocher 4168159df72SHeiko Schocher mdio@3320 { 4178159df72SHeiko Schocher #address-cells = <1>; 4188159df72SHeiko Schocher #size-cells = <0>; 4198159df72SHeiko Schocher reg = <0x3320 0x18>; 4208159df72SHeiko Schocher compatible = "fsl,ucc-mdio"; 4218159df72SHeiko Schocher 4228159df72SHeiko Schocher /* Piggy2 (UCC4, MDIO 0x00, RMII) */ 4238159df72SHeiko Schocher phy_piggy2: ethernet-phy@00 { 4248159df72SHeiko Schocher reg = <0x0>; 4258159df72SHeiko Schocher }; 4268159df72SHeiko Schocher 4278159df72SHeiko Schocher /* Eth-1 (UCC5, MDIO 0x08, RMII) */ 4288159df72SHeiko Schocher phy_eth1: ethernet-phy@08 { 4298159df72SHeiko Schocher reg = <0x08>; 4308159df72SHeiko Schocher }; 4318159df72SHeiko Schocher 4328159df72SHeiko Schocher /* Eth-2 (UCC6, MDIO 0x09, RMII) */ 4338159df72SHeiko Schocher phy_eth2: ethernet-phy@09 { 4348159df72SHeiko Schocher reg = <0x09>; 4358159df72SHeiko Schocher }; 4368159df72SHeiko Schocher 4378159df72SHeiko Schocher /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ 4388159df72SHeiko Schocher phy_eth3: ethernet-phy@0a { 4398159df72SHeiko Schocher reg = <0x0a>; 4408159df72SHeiko Schocher }; 4418159df72SHeiko Schocher 4428159df72SHeiko Schocher /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ 4438159df72SHeiko Schocher phy_eth4: ethernet-phy@0b { 4448159df72SHeiko Schocher reg = <0x0b>; 4458159df72SHeiko Schocher }; 4468159df72SHeiko Schocher 4478159df72SHeiko Schocher /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ 4488159df72SHeiko Schocher phy_estar1: ethernet-phy@10 { 4498159df72SHeiko Schocher interrupt-parent = <&ipic>; 4508159df72SHeiko Schocher interrupts = <17 0x8>; 4518159df72SHeiko Schocher reg = <0x10>; 4528159df72SHeiko Schocher }; 4538159df72SHeiko Schocher 4548159df72SHeiko Schocher /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ 4558159df72SHeiko Schocher phy_estar2: ethernet-phy@11 { 4568159df72SHeiko Schocher interrupt-parent = <&ipic>; 4578159df72SHeiko Schocher interrupts = <18 0x8>; 4588159df72SHeiko Schocher reg = <0x11>; 4598159df72SHeiko Schocher }; 4608159df72SHeiko Schocher }; 4618159df72SHeiko Schocher 4628159df72SHeiko Schocher qeic: interrupt-controller@80 { 4638159df72SHeiko Schocher interrupt-controller; 4648159df72SHeiko Schocher compatible = "fsl,qe-ic"; 4658159df72SHeiko Schocher #address-cells = <0>; 4668159df72SHeiko Schocher #interrupt-cells = <1>; 4678159df72SHeiko Schocher reg = <0x80 0x80>; 4688159df72SHeiko Schocher interrupts = <32 8 33 8>; 4698159df72SHeiko Schocher interrupt-parent = <&ipic>; 4708159df72SHeiko Schocher }; 4718159df72SHeiko Schocher }; 4728159df72SHeiko Schocher }; 4738159df72SHeiko Schocher 4748159df72SHeiko Schocher localbus@e0005000 { 4758159df72SHeiko Schocher #address-cells = <2>; 4768159df72SHeiko Schocher #size-cells = <1>; 4778159df72SHeiko Schocher compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", 4788159df72SHeiko Schocher "simple-bus"; 4798159df72SHeiko Schocher reg = <0xe0005000 0xd8>; 4808159df72SHeiko Schocher ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */ 4818159df72SHeiko Schocher 4828159df72SHeiko Schocher flash@f0000000,0 { 4838159df72SHeiko Schocher compatible = "cfi-flash"; 4848159df72SHeiko Schocher /* 4858159df72SHeiko Schocher * The Intel P30 chip has 2 non-identical chips on 4868159df72SHeiko Schocher * one die, so we need to define 2 seperate regions 4878159df72SHeiko Schocher * that are scanned by physmap_of independantly. 4888159df72SHeiko Schocher */ 4898159df72SHeiko Schocher reg = <0 0x00000000 0x02000000 4908159df72SHeiko Schocher 0 0x02000000 0x02000000>; /* Filled in by U-Boot */ 4918159df72SHeiko Schocher bank-width = <2>; 4928159df72SHeiko Schocher #address-cells = <1>; 4938159df72SHeiko Schocher #size-cells = <1>; 4948159df72SHeiko Schocher partition@0 { 4958159df72SHeiko Schocher label = "u-boot"; 4968159df72SHeiko Schocher reg = <0 0x40000>; 4978159df72SHeiko Schocher }; 4988159df72SHeiko Schocher partition@40000 { 4998159df72SHeiko Schocher label = "env"; 5008159df72SHeiko Schocher reg = <0x40000 0x40000>; 5018159df72SHeiko Schocher }; 5028159df72SHeiko Schocher partition@80000 { 5038159df72SHeiko Schocher label = "dtb"; 5048159df72SHeiko Schocher reg = <0x80000 0x20000>; 5058159df72SHeiko Schocher }; 5068159df72SHeiko Schocher partition@a0000 { 5078159df72SHeiko Schocher label = "kernel"; 5088159df72SHeiko Schocher reg = <0xa0000 0x300000>; 5098159df72SHeiko Schocher }; 5108159df72SHeiko Schocher partition@3a0000 { 5118159df72SHeiko Schocher label = "ramdisk"; 5128159df72SHeiko Schocher reg = <0x3a0000 0x800000>; 5138159df72SHeiko Schocher }; 5148159df72SHeiko Schocher partition@ba0000 { 5158159df72SHeiko Schocher label = "user"; 5168159df72SHeiko Schocher reg = <0xba0000 0x3460000>; 5178159df72SHeiko Schocher }; 5188159df72SHeiko Schocher }; 5198159df72SHeiko Schocher }; 5208159df72SHeiko Schocher}; 521