1a62f48deSStefan Roese/*
2a62f48deSStefan Roese * Device Tree Source for AMCC Kilauea (405EX)
3a62f48deSStefan Roese *
4a62f48deSStefan Roese * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
5a62f48deSStefan Roese *
6a62f48deSStefan Roese * This file is licensed under the terms of the GNU General Public
7a62f48deSStefan Roese * License version 2.  This program is licensed "as is" without
8a62f48deSStefan Roese * any warranty of any kind, whether express or implied.
9a62f48deSStefan Roese */
10a62f48deSStefan Roese
11a62f48deSStefan Roese/ {
12a62f48deSStefan Roese	#address-cells = <1>;
13a62f48deSStefan Roese	#size-cells = <1>;
14a62f48deSStefan Roese	model = "amcc,kilauea";
15a62f48deSStefan Roese	compatible = "amcc,kilauea";
16a62f48deSStefan Roese	dcr-parent = <&/cpus/PowerPC,405EX@0>;
17a62f48deSStefan Roese
18a62f48deSStefan Roese	cpus {
19a62f48deSStefan Roese		#address-cells = <1>;
20a62f48deSStefan Roese		#size-cells = <0>;
21a62f48deSStefan Roese
22a62f48deSStefan Roese		PowerPC,405EX@0 {
23a62f48deSStefan Roese			device_type = "cpu";
24a62f48deSStefan Roese			reg = <0>;
25a62f48deSStefan Roese			clock-frequency = <0>; /* Filled in by U-Boot */
26a62f48deSStefan Roese			timebase-frequency = <0>; /* Filled in by U-Boot */
27a62f48deSStefan Roese			i-cache-line-size = <20>;
28a62f48deSStefan Roese			d-cache-line-size = <20>;
29a62f48deSStefan Roese			i-cache-size = <4000>; /* 16 kB */
30a62f48deSStefan Roese			d-cache-size = <4000>; /* 16 kB */
31a62f48deSStefan Roese			dcr-controller;
32a62f48deSStefan Roese			dcr-access-method = "native";
33a62f48deSStefan Roese		};
34a62f48deSStefan Roese	};
35a62f48deSStefan Roese
36a62f48deSStefan Roese	memory {
37a62f48deSStefan Roese		device_type = "memory";
38a62f48deSStefan Roese		reg = <0 0>; /* Filled in by U-Boot */
39a62f48deSStefan Roese	};
40a62f48deSStefan Roese
41a62f48deSStefan Roese	UIC0: interrupt-controller {
42a62f48deSStefan Roese		compatible = "ibm,uic-405ex", "ibm,uic";
43a62f48deSStefan Roese		interrupt-controller;
44a62f48deSStefan Roese		cell-index = <0>;
45a62f48deSStefan Roese		dcr-reg = <0c0 009>;
46a62f48deSStefan Roese		#address-cells = <0>;
47a62f48deSStefan Roese		#size-cells = <0>;
48a62f48deSStefan Roese		#interrupt-cells = <2>;
49a62f48deSStefan Roese	};
50a62f48deSStefan Roese
51a62f48deSStefan Roese	UIC1: interrupt-controller1 {
52a62f48deSStefan Roese		compatible = "ibm,uic-405ex","ibm,uic";
53a62f48deSStefan Roese		interrupt-controller;
54a62f48deSStefan Roese		cell-index = <1>;
55a62f48deSStefan Roese		dcr-reg = <0d0 009>;
56a62f48deSStefan Roese		#address-cells = <0>;
57a62f48deSStefan Roese		#size-cells = <0>;
58a62f48deSStefan Roese		#interrupt-cells = <2>;
59a62f48deSStefan Roese		interrupts = <1e 4 1f 4>; /* cascade */
60a62f48deSStefan Roese		interrupt-parent = <&UIC0>;
61a62f48deSStefan Roese	};
62a62f48deSStefan Roese
63a62f48deSStefan Roese	UIC2: interrupt-controller2 {
64a62f48deSStefan Roese		compatible = "ibm,uic-405ex","ibm,uic";
65a62f48deSStefan Roese		interrupt-controller;
66a62f48deSStefan Roese		cell-index = <2>;
67a62f48deSStefan Roese		dcr-reg = <0e0 009>;
68a62f48deSStefan Roese		#address-cells = <0>;
69a62f48deSStefan Roese		#size-cells = <0>;
70a62f48deSStefan Roese		#interrupt-cells = <2>;
71a62f48deSStefan Roese		interrupts = <1c 4 1d 4>; /* cascade */
72a62f48deSStefan Roese		interrupt-parent = <&UIC0>;
73a62f48deSStefan Roese	};
74a62f48deSStefan Roese
75a62f48deSStefan Roese	plb {
76a62f48deSStefan Roese		compatible = "ibm,plb-405ex", "ibm,plb4";
77a62f48deSStefan Roese		#address-cells = <1>;
78a62f48deSStefan Roese		#size-cells = <1>;
79a62f48deSStefan Roese		ranges;
80a62f48deSStefan Roese		clock-frequency = <0>; /* Filled in by U-Boot */
81a62f48deSStefan Roese
82a62f48deSStefan Roese		SDRAM0: memory-controller {
83a62f48deSStefan Roese			compatible = "ibm,sdram-405ex";
84a62f48deSStefan Roese			dcr-reg = <010 2>;
85a62f48deSStefan Roese		};
86a62f48deSStefan Roese
87a62f48deSStefan Roese		MAL0: mcmal {
88a62f48deSStefan Roese			compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
89a62f48deSStefan Roese			dcr-reg = <180 62>;
90a62f48deSStefan Roese			num-tx-chans = <2>;
91a62f48deSStefan Roese			num-rx-chans = <2>;
92a62f48deSStefan Roese			interrupt-parent = <&MAL0>;
93a62f48deSStefan Roese			interrupts = <0 1 2 3 4>;
94a62f48deSStefan Roese			#interrupt-cells = <1>;
95a62f48deSStefan Roese			#address-cells = <0>;
96a62f48deSStefan Roese			#size-cells = <0>;
97a62f48deSStefan Roese			interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
98a62f48deSStefan Roese					/*RXEOB*/ 1 &UIC0 b 4
99a62f48deSStefan Roese					/*SERR*/  2 &UIC1 0 4
100a62f48deSStefan Roese					/*TXDE*/  3 &UIC1 1 4
101a62f48deSStefan Roese					/*RXDE*/  4 &UIC1 2 4>;
102a62f48deSStefan Roese			interrupt-map-mask = <ffffffff>;
103a62f48deSStefan Roese		};
104a62f48deSStefan Roese
105a62f48deSStefan Roese		POB0: opb {
106a62f48deSStefan Roese			compatible = "ibm,opb-405ex", "ibm,opb";
107a62f48deSStefan Roese			#address-cells = <1>;
108a62f48deSStefan Roese			#size-cells = <1>;
109a62f48deSStefan Roese			ranges = <80000000 80000000 10000000
110a62f48deSStefan Roese				  ef600000 ef600000 a00000
111a62f48deSStefan Roese				  f0000000 f0000000 10000000>;
112a62f48deSStefan Roese			dcr-reg = <0a0 5>;
113a62f48deSStefan Roese			clock-frequency = <0>; /* Filled in by U-Boot */
114a62f48deSStefan Roese
115a62f48deSStefan Roese			EBC0: ebc {
116a62f48deSStefan Roese				compatible = "ibm,ebc-405ex", "ibm,ebc";
117a62f48deSStefan Roese				dcr-reg = <012 2>;
118a62f48deSStefan Roese				#address-cells = <2>;
119a62f48deSStefan Roese				#size-cells = <1>;
120a62f48deSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
121a62f48deSStefan Roese				/* ranges property is supplied by U-Boot */
122a62f48deSStefan Roese				interrupts = <5 1>;
123a62f48deSStefan Roese				interrupt-parent = <&UIC1>;
124a62f48deSStefan Roese
125a62f48deSStefan Roese				nor_flash@0,0 {
126a62f48deSStefan Roese					compatible = "amd,s29gl512n", "cfi-flash";
127a62f48deSStefan Roese					bank-width = <2>;
128a62f48deSStefan Roese					reg = <0 000000 4000000>;
129a62f48deSStefan Roese					#address-cells = <1>;
130a62f48deSStefan Roese					#size-cells = <1>;
131a62f48deSStefan Roese					partition@0 {
132a62f48deSStefan Roese						label = "kernel";
133a62f48deSStefan Roese						reg = <0 200000>;
134a62f48deSStefan Roese					};
135a62f48deSStefan Roese					partition@200000 {
136a62f48deSStefan Roese						label = "root";
137a62f48deSStefan Roese						reg = <200000 200000>;
138a62f48deSStefan Roese					};
139a62f48deSStefan Roese					partition@400000 {
140a62f48deSStefan Roese						label = "user";
141a62f48deSStefan Roese						reg = <400000 3b60000>;
142a62f48deSStefan Roese					};
143a62f48deSStefan Roese					partition@3f60000 {
144a62f48deSStefan Roese						label = "env";
145a62f48deSStefan Roese						reg = <3f60000 40000>;
146a62f48deSStefan Roese					};
147a62f48deSStefan Roese					partition@3fa0000 {
148a62f48deSStefan Roese						label = "u-boot";
149a62f48deSStefan Roese						reg = <3fa0000 60000>;
150a62f48deSStefan Roese					};
151a62f48deSStefan Roese				};
152a62f48deSStefan Roese			};
153a62f48deSStefan Roese
154a62f48deSStefan Roese			UART0: serial@ef600200 {
155a62f48deSStefan Roese				device_type = "serial";
156a62f48deSStefan Roese				compatible = "ns16550";
157a62f48deSStefan Roese				reg = <ef600200 8>;
158a62f48deSStefan Roese				virtual-reg = <ef600200>;
159a62f48deSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
160a62f48deSStefan Roese				current-speed = <0>;
161a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
162a62f48deSStefan Roese				interrupts = <1a 4>;
163a62f48deSStefan Roese			};
164a62f48deSStefan Roese
165a62f48deSStefan Roese			UART1: serial@ef600300 {
166a62f48deSStefan Roese				device_type = "serial";
167a62f48deSStefan Roese				compatible = "ns16550";
168a62f48deSStefan Roese				reg = <ef600300 8>;
169a62f48deSStefan Roese				virtual-reg = <ef600300>;
170a62f48deSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
171a62f48deSStefan Roese				current-speed = <0>;
172a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
173a62f48deSStefan Roese				interrupts = <1 4>;
174a62f48deSStefan Roese			};
175a62f48deSStefan Roese
176a62f48deSStefan Roese			IIC0: i2c@ef600400 {
177a62f48deSStefan Roese				device_type = "i2c";
178a62f48deSStefan Roese				compatible = "ibm,iic-405ex", "ibm,iic";
179a62f48deSStefan Roese				reg = <ef600400 14>;
180a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
181a62f48deSStefan Roese				interrupts = <2 4>;
182a62f48deSStefan Roese			};
183a62f48deSStefan Roese
184a62f48deSStefan Roese			IIC1: i2c@ef600500 {
185a62f48deSStefan Roese				device_type = "i2c";
186a62f48deSStefan Roese				compatible = "ibm,iic-405ex", "ibm,iic";
187a62f48deSStefan Roese				reg = <ef600500 14>;
188a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
189a62f48deSStefan Roese				interrupts = <7 4>;
190a62f48deSStefan Roese			};
191a62f48deSStefan Roese
192a62f48deSStefan Roese
193a62f48deSStefan Roese			RGMII0: emac-rgmii@ef600b00 {
194a62f48deSStefan Roese				device_type = "rgmii-interface";
195a62f48deSStefan Roese				compatible = "ibm,rgmii-405ex", "ibm,rgmii";
196a62f48deSStefan Roese				reg = <ef600b00 104>;
197a62f48deSStefan Roese			};
198a62f48deSStefan Roese
199a62f48deSStefan Roese			EMAC0: ethernet@ef600900 {
200a62f48deSStefan Roese				linux,network-index = <0>;
201a62f48deSStefan Roese				device_type = "network";
202a62f48deSStefan Roese				compatible = "ibm,emac-405ex", "ibm,emac4";
203a62f48deSStefan Roese				interrupt-parent = <&EMAC0>;
204a62f48deSStefan Roese				interrupts = <0 1>;
205a62f48deSStefan Roese				#interrupt-cells = <1>;
206a62f48deSStefan Roese				#address-cells = <0>;
207a62f48deSStefan Roese				#size-cells = <0>;
208a62f48deSStefan Roese				interrupt-map = </*Status*/ 0 &UIC0 18 4
209a62f48deSStefan Roese						/*Wake*/  1 &UIC1 1d 4>;
210a62f48deSStefan Roese				reg = <ef600900 70>;
211a62f48deSStefan Roese				local-mac-address = [000000000000]; /* Filled in by U-Boot */
212a62f48deSStefan Roese				mal-device = <&MAL0>;
213a62f48deSStefan Roese				mal-tx-channel = <0>;
214a62f48deSStefan Roese				mal-rx-channel = <0>;
215a62f48deSStefan Roese				cell-index = <0>;
216a62f48deSStefan Roese				max-frame-size = <5dc>;
217a62f48deSStefan Roese				rx-fifo-size = <1000>;
218a62f48deSStefan Roese				tx-fifo-size = <800>;
219a62f48deSStefan Roese				phy-mode = "rgmii";
220a62f48deSStefan Roese				phy-map = <00000000>;
221a62f48deSStefan Roese				rgmii-device = <&RGMII0>;
222a62f48deSStefan Roese				rgmii-channel = <0>;
223a62f48deSStefan Roese			};
224a62f48deSStefan Roese
225a62f48deSStefan Roese			EMAC1: ethernet@ef600a00 {
226a62f48deSStefan Roese				linux,network-index = <1>;
227a62f48deSStefan Roese				device_type = "network";
228a62f48deSStefan Roese				compatible = "ibm,emac-405ex", "ibm,emac4";
229a62f48deSStefan Roese				interrupt-parent = <&EMAC1>;
230a62f48deSStefan Roese				interrupts = <0 1>;
231a62f48deSStefan Roese				#interrupt-cells = <1>;
232a62f48deSStefan Roese				#address-cells = <0>;
233a62f48deSStefan Roese				#size-cells = <0>;
234a62f48deSStefan Roese				interrupt-map = </*Status*/ 0 &UIC0 19 4
235a62f48deSStefan Roese						/*Wake*/  1 &UIC1 1f 4>;
236a62f48deSStefan Roese				reg = <ef600a00 70>;
237a62f48deSStefan Roese				local-mac-address = [000000000000]; /* Filled in by U-Boot */
238a62f48deSStefan Roese				mal-device = <&MAL0>;
239a62f48deSStefan Roese				mal-tx-channel = <1>;
240a62f48deSStefan Roese				mal-rx-channel = <1>;
241a62f48deSStefan Roese				cell-index = <1>;
242a62f48deSStefan Roese				max-frame-size = <5dc>;
243a62f48deSStefan Roese				rx-fifo-size = <1000>;
244a62f48deSStefan Roese				tx-fifo-size = <800>;
245a62f48deSStefan Roese				phy-mode = "rgmii";
246a62f48deSStefan Roese				phy-map = <00000000>;
247a62f48deSStefan Roese				rgmii-device = <&RGMII0>;
248a62f48deSStefan Roese				rgmii-channel = <1>;
249a62f48deSStefan Roese			};
250a62f48deSStefan Roese		};
251a62f48deSStefan Roese	};
252a62f48deSStefan Roese};
253