1a62f48deSStefan Roese/*
2a62f48deSStefan Roese * Device Tree Source for AMCC Kilauea (405EX)
3a62f48deSStefan Roese *
4a62f48deSStefan Roese * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
5a62f48deSStefan Roese *
6a62f48deSStefan Roese * This file is licensed under the terms of the GNU General Public
7a62f48deSStefan Roese * License version 2.  This program is licensed "as is" without
8a62f48deSStefan Roese * any warranty of any kind, whether express or implied.
9a62f48deSStefan Roese */
10a62f48deSStefan Roese
1171f34979SDavid Gibson/dts-v1/;
1271f34979SDavid Gibson
13a62f48deSStefan Roese/ {
14a62f48deSStefan Roese	#address-cells = <1>;
15a62f48deSStefan Roese	#size-cells = <1>;
16a62f48deSStefan Roese	model = "amcc,kilauea";
17a62f48deSStefan Roese	compatible = "amcc,kilauea";
1871f34979SDavid Gibson	dcr-parent = <&{/cpus/cpu@0}>;
19a62f48deSStefan Roese
208aaed98cSStefan Roese	aliases {
218aaed98cSStefan Roese		ethernet0 = &EMAC0;
228aaed98cSStefan Roese		ethernet1 = &EMAC1;
238aaed98cSStefan Roese		serial0 = &UART0;
248aaed98cSStefan Roese		serial1 = &UART1;
258aaed98cSStefan Roese	};
268aaed98cSStefan Roese
27a62f48deSStefan Roese	cpus {
28a62f48deSStefan Roese		#address-cells = <1>;
29a62f48deSStefan Roese		#size-cells = <0>;
30a62f48deSStefan Roese
3172fda114SJosh Boyer		cpu@0 {
32a62f48deSStefan Roese			device_type = "cpu";
3372fda114SJosh Boyer			model = "PowerPC,405EX";
3471f34979SDavid Gibson			reg = <0x00000000>;
35a62f48deSStefan Roese			clock-frequency = <0>; /* Filled in by U-Boot */
36a62f48deSStefan Roese			timebase-frequency = <0>; /* Filled in by U-Boot */
3771f34979SDavid Gibson			i-cache-line-size = <32>;
3871f34979SDavid Gibson			d-cache-line-size = <32>;
3971f34979SDavid Gibson			i-cache-size = <16384>; /* 16 kB */
4071f34979SDavid Gibson			d-cache-size = <16384>; /* 16 kB */
41a62f48deSStefan Roese			dcr-controller;
42a62f48deSStefan Roese			dcr-access-method = "native";
43a62f48deSStefan Roese		};
44a62f48deSStefan Roese	};
45a62f48deSStefan Roese
46a62f48deSStefan Roese	memory {
47a62f48deSStefan Roese		device_type = "memory";
4871f34979SDavid Gibson		reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
49a62f48deSStefan Roese	};
50a62f48deSStefan Roese
51a62f48deSStefan Roese	UIC0: interrupt-controller {
52a62f48deSStefan Roese		compatible = "ibm,uic-405ex", "ibm,uic";
53a62f48deSStefan Roese		interrupt-controller;
54a62f48deSStefan Roese		cell-index = <0>;
5571f34979SDavid Gibson		dcr-reg = <0x0c0 0x009>;
56a62f48deSStefan Roese		#address-cells = <0>;
57a62f48deSStefan Roese		#size-cells = <0>;
58a62f48deSStefan Roese		#interrupt-cells = <2>;
59a62f48deSStefan Roese	};
60a62f48deSStefan Roese
61a62f48deSStefan Roese	UIC1: interrupt-controller1 {
62a62f48deSStefan Roese		compatible = "ibm,uic-405ex","ibm,uic";
63a62f48deSStefan Roese		interrupt-controller;
64a62f48deSStefan Roese		cell-index = <1>;
6571f34979SDavid Gibson		dcr-reg = <0x0d0 0x009>;
66a62f48deSStefan Roese		#address-cells = <0>;
67a62f48deSStefan Roese		#size-cells = <0>;
68a62f48deSStefan Roese		#interrupt-cells = <2>;
6971f34979SDavid Gibson		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
70a62f48deSStefan Roese		interrupt-parent = <&UIC0>;
71a62f48deSStefan Roese	};
72a62f48deSStefan Roese
73a62f48deSStefan Roese	UIC2: interrupt-controller2 {
74a62f48deSStefan Roese		compatible = "ibm,uic-405ex","ibm,uic";
75a62f48deSStefan Roese		interrupt-controller;
76a62f48deSStefan Roese		cell-index = <2>;
7771f34979SDavid Gibson		dcr-reg = <0x0e0 0x009>;
78a62f48deSStefan Roese		#address-cells = <0>;
79a62f48deSStefan Roese		#size-cells = <0>;
80a62f48deSStefan Roese		#interrupt-cells = <2>;
8171f34979SDavid Gibson		interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
82a62f48deSStefan Roese		interrupt-parent = <&UIC0>;
83a62f48deSStefan Roese	};
84a62f48deSStefan Roese
85a62f48deSStefan Roese	plb {
86a62f48deSStefan Roese		compatible = "ibm,plb-405ex", "ibm,plb4";
87a62f48deSStefan Roese		#address-cells = <1>;
88a62f48deSStefan Roese		#size-cells = <1>;
89a62f48deSStefan Roese		ranges;
90a62f48deSStefan Roese		clock-frequency = <0>; /* Filled in by U-Boot */
91a62f48deSStefan Roese
92a62f48deSStefan Roese		SDRAM0: memory-controller {
9394ce1c58SGrant Erickson			compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
9471f34979SDavid Gibson			dcr-reg = <0x010 0x002>;
9594ce1c58SGrant Erickson			interrupt-parent = <&UIC2>;
9694ce1c58SGrant Erickson			interrupts = <0x5 0x4	/* ECC DED Error */
9794ce1c58SGrant Erickson				      0x6 0x4>;	/* ECC SEC Error */
98a62f48deSStefan Roese		};
99a62f48deSStefan Roese
100a62f48deSStefan Roese		MAL0: mcmal {
101a62f48deSStefan Roese			compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
10271f34979SDavid Gibson			dcr-reg = <0x180 0x062>;
103a62f48deSStefan Roese			num-tx-chans = <2>;
104a62f48deSStefan Roese			num-rx-chans = <2>;
105a62f48deSStefan Roese			interrupt-parent = <&MAL0>;
10671f34979SDavid Gibson			interrupts = <0x0 0x1 0x2 0x3 0x4>;
107a62f48deSStefan Roese			#interrupt-cells = <1>;
108a62f48deSStefan Roese			#address-cells = <0>;
109a62f48deSStefan Roese			#size-cells = <0>;
11071f34979SDavid Gibson			interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
11171f34979SDavid Gibson					/*RXEOB*/ 0x1 &UIC0 0xb 0x4
11271f34979SDavid Gibson					/*SERR*/  0x2 &UIC1 0x0 0x4
11371f34979SDavid Gibson					/*TXDE*/  0x3 &UIC1 0x1 0x4
11471f34979SDavid Gibson					/*RXDE*/  0x4 &UIC1 0x2 0x4>;
11571f34979SDavid Gibson			interrupt-map-mask = <0xffffffff>;
116a62f48deSStefan Roese		};
117a62f48deSStefan Roese
118a62f48deSStefan Roese		POB0: opb {
119a62f48deSStefan Roese			compatible = "ibm,opb-405ex", "ibm,opb";
120a62f48deSStefan Roese			#address-cells = <1>;
121a62f48deSStefan Roese			#size-cells = <1>;
12271f34979SDavid Gibson			ranges = <0x80000000 0x80000000 0x10000000
12371f34979SDavid Gibson				  0xef600000 0xef600000 0x00a00000
12471f34979SDavid Gibson				  0xf0000000 0xf0000000 0x10000000>;
12571f34979SDavid Gibson			dcr-reg = <0x0a0 0x005>;
126a62f48deSStefan Roese			clock-frequency = <0>; /* Filled in by U-Boot */
127a62f48deSStefan Roese
128a62f48deSStefan Roese			EBC0: ebc {
129a62f48deSStefan Roese				compatible = "ibm,ebc-405ex", "ibm,ebc";
13071f34979SDavid Gibson				dcr-reg = <0x012 0x002>;
131a62f48deSStefan Roese				#address-cells = <2>;
132a62f48deSStefan Roese				#size-cells = <1>;
133a62f48deSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
134a62f48deSStefan Roese				/* ranges property is supplied by U-Boot */
13571f34979SDavid Gibson				interrupts = <0x5 0x1>;
136a62f48deSStefan Roese				interrupt-parent = <&UIC1>;
137a62f48deSStefan Roese
138a62f48deSStefan Roese				nor_flash@0,0 {
139a62f48deSStefan Roese					compatible = "amd,s29gl512n", "cfi-flash";
140a62f48deSStefan Roese					bank-width = <2>;
14171f34979SDavid Gibson					reg = <0x00000000 0x00000000 0x04000000>;
142a62f48deSStefan Roese					#address-cells = <1>;
143a62f48deSStefan Roese					#size-cells = <1>;
144a62f48deSStefan Roese					partition@0 {
145a62f48deSStefan Roese						label = "kernel";
14671f34979SDavid Gibson						reg = <0x00000000 0x00200000>;
147a62f48deSStefan Roese					};
148a62f48deSStefan Roese					partition@200000 {
149a62f48deSStefan Roese						label = "root";
15071f34979SDavid Gibson						reg = <0x00200000 0x00200000>;
151a62f48deSStefan Roese					};
152a62f48deSStefan Roese					partition@400000 {
153a62f48deSStefan Roese						label = "user";
15471f34979SDavid Gibson						reg = <0x00400000 0x03b60000>;
155a62f48deSStefan Roese					};
156a62f48deSStefan Roese					partition@3f60000 {
157a62f48deSStefan Roese						label = "env";
15871f34979SDavid Gibson						reg = <0x03f60000 0x00040000>;
159a62f48deSStefan Roese					};
160a62f48deSStefan Roese					partition@3fa0000 {
161a62f48deSStefan Roese						label = "u-boot";
16271f34979SDavid Gibson						reg = <0x03fa0000 0x00060000>;
163a62f48deSStefan Roese					};
164a62f48deSStefan Roese				};
165a62f48deSStefan Roese			};
166a62f48deSStefan Roese
167a62f48deSStefan Roese			UART0: serial@ef600200 {
168a62f48deSStefan Roese				device_type = "serial";
169a62f48deSStefan Roese				compatible = "ns16550";
17071f34979SDavid Gibson				reg = <0xef600200 0x00000008>;
17171f34979SDavid Gibson				virtual-reg = <0xef600200>;
172a62f48deSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
173a62f48deSStefan Roese				current-speed = <0>;
174a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
17571f34979SDavid Gibson				interrupts = <0x1a 0x4>;
176a62f48deSStefan Roese			};
177a62f48deSStefan Roese
178a62f48deSStefan Roese			UART1: serial@ef600300 {
179a62f48deSStefan Roese				device_type = "serial";
180a62f48deSStefan Roese				compatible = "ns16550";
18171f34979SDavid Gibson				reg = <0xef600300 0x00000008>;
18271f34979SDavid Gibson				virtual-reg = <0xef600300>;
183a62f48deSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
184a62f48deSStefan Roese				current-speed = <0>;
185a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
18671f34979SDavid Gibson				interrupts = <0x1 0x4>;
187a62f48deSStefan Roese			};
188a62f48deSStefan Roese
189a62f48deSStefan Roese			IIC0: i2c@ef600400 {
190a62f48deSStefan Roese				compatible = "ibm,iic-405ex", "ibm,iic";
19171f34979SDavid Gibson				reg = <0xef600400 0x00000014>;
192a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
19371f34979SDavid Gibson				interrupts = <0x2 0x4>;
194a62f48deSStefan Roese			};
195a62f48deSStefan Roese
196a62f48deSStefan Roese			IIC1: i2c@ef600500 {
197a62f48deSStefan Roese				compatible = "ibm,iic-405ex", "ibm,iic";
19871f34979SDavid Gibson				reg = <0xef600500 0x00000014>;
199a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
20071f34979SDavid Gibson				interrupts = <0x7 0x4>;
201a62f48deSStefan Roese			};
202a62f48deSStefan Roese
203a62f48deSStefan Roese
204a62f48deSStefan Roese			RGMII0: emac-rgmii@ef600b00 {
205a62f48deSStefan Roese				compatible = "ibm,rgmii-405ex", "ibm,rgmii";
20671f34979SDavid Gibson				reg = <0xef600b00 0x00000104>;
2070a6ea8beSStefan Roese				has-mdio;
208a62f48deSStefan Roese			};
209a62f48deSStefan Roese
210a62f48deSStefan Roese			EMAC0: ethernet@ef600900 {
21171f34979SDavid Gibson				linux,network-index = <0x0>;
212a62f48deSStefan Roese				device_type = "network";
21305781ccdSGrant Erickson				compatible = "ibm,emac-405ex", "ibm,emac4sync";
214a62f48deSStefan Roese				interrupt-parent = <&EMAC0>;
21571f34979SDavid Gibson				interrupts = <0x0 0x1>;
216a62f48deSStefan Roese				#interrupt-cells = <1>;
217a62f48deSStefan Roese				#address-cells = <0>;
218a62f48deSStefan Roese				#size-cells = <0>;
21971f34979SDavid Gibson				interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
22071f34979SDavid Gibson						/*Wake*/  0x1 &UIC1 0x1d 0x4>;
22105781ccdSGrant Erickson				reg = <0xef600900 0x000000c4>;
222a62f48deSStefan Roese				local-mac-address = [000000000000]; /* Filled in by U-Boot */
223a62f48deSStefan Roese				mal-device = <&MAL0>;
224a62f48deSStefan Roese				mal-tx-channel = <0>;
225a62f48deSStefan Roese				mal-rx-channel = <0>;
226a62f48deSStefan Roese				cell-index = <0>;
22771f34979SDavid Gibson				max-frame-size = <9000>;
22871f34979SDavid Gibson				rx-fifo-size = <4096>;
22971f34979SDavid Gibson				tx-fifo-size = <2048>;
230a62f48deSStefan Roese				phy-mode = "rgmii";
23171f34979SDavid Gibson				phy-map = <0x00000000>;
232a62f48deSStefan Roese				rgmii-device = <&RGMII0>;
233a62f48deSStefan Roese				rgmii-channel = <0>;
2340a6ea8beSStefan Roese				has-inverted-stacr-oc;
2350a6ea8beSStefan Roese				has-new-stacr-staopc;
236a62f48deSStefan Roese			};
237a62f48deSStefan Roese
238a62f48deSStefan Roese			EMAC1: ethernet@ef600a00 {
23971f34979SDavid Gibson				linux,network-index = <0x1>;
240a62f48deSStefan Roese				device_type = "network";
24105781ccdSGrant Erickson				compatible = "ibm,emac-405ex", "ibm,emac4sync";
242a62f48deSStefan Roese				interrupt-parent = <&EMAC1>;
24371f34979SDavid Gibson				interrupts = <0x0 0x1>;
244a62f48deSStefan Roese				#interrupt-cells = <1>;
245a62f48deSStefan Roese				#address-cells = <0>;
246a62f48deSStefan Roese				#size-cells = <0>;
24771f34979SDavid Gibson				interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
24871f34979SDavid Gibson						/*Wake*/  0x1 &UIC1 0x1f 0x4>;
24905781ccdSGrant Erickson				reg = <0xef600a00 0x000000c4>;
250a62f48deSStefan Roese				local-mac-address = [000000000000]; /* Filled in by U-Boot */
251a62f48deSStefan Roese				mal-device = <&MAL0>;
252a62f48deSStefan Roese				mal-tx-channel = <1>;
253a62f48deSStefan Roese				mal-rx-channel = <1>;
254a62f48deSStefan Roese				cell-index = <1>;
25571f34979SDavid Gibson				max-frame-size = <9000>;
25671f34979SDavid Gibson				rx-fifo-size = <4096>;
25771f34979SDavid Gibson				tx-fifo-size = <2048>;
258a62f48deSStefan Roese				phy-mode = "rgmii";
25971f34979SDavid Gibson				phy-map = <0x00000000>;
260a62f48deSStefan Roese				rgmii-device = <&RGMII0>;
261a62f48deSStefan Roese				rgmii-channel = <1>;
2620a6ea8beSStefan Roese				has-inverted-stacr-oc;
2630a6ea8beSStefan Roese				has-new-stacr-staopc;
264a62f48deSStefan Roese			};
265a62f48deSStefan Roese		};
266151161c6SStefan Roese
267151161c6SStefan Roese		PCIE0: pciex@0a0000000 {
268151161c6SStefan Roese			device_type = "pci";
269151161c6SStefan Roese			#interrupt-cells = <1>;
270151161c6SStefan Roese			#size-cells = <2>;
271151161c6SStefan Roese			#address-cells = <3>;
272151161c6SStefan Roese			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
273151161c6SStefan Roese			primary;
27471f34979SDavid Gibson			port = <0x0>; /* port number */
27571f34979SDavid Gibson			reg = <0xa0000000 0x20000000	/* Config space access */
27671f34979SDavid Gibson			       0xef000000 0x00001000>;	/* Registers */
27771f34979SDavid Gibson			dcr-reg = <0x040 0x020>;
27871f34979SDavid Gibson			sdr-base = <0x400>;
279151161c6SStefan Roese
280151161c6SStefan Roese			/* Outbound ranges, one memory and one IO,
281151161c6SStefan Roese			 * later cannot be changed
282151161c6SStefan Roese			 */
28371f34979SDavid Gibson			ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
28471f34979SDavid Gibson				  0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
285151161c6SStefan Roese
286151161c6SStefan Roese			/* Inbound 2GB range starting at 0 */
28771f34979SDavid Gibson			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
288151161c6SStefan Roese
289dc88416bSStefan Roese			/* This drives busses 0x00 to 0x3f */
29071f34979SDavid Gibson			bus-range = <0x0 0x3f>;
291151161c6SStefan Roese
292151161c6SStefan Roese			/* Legacy interrupts (note the weird polarity, the bridge seems
293151161c6SStefan Roese			 * to invert PCIe legacy interrupts).
294151161c6SStefan Roese			 * We are de-swizzling here because the numbers are actually for
295151161c6SStefan Roese			 * port of the root complex virtual P2P bridge. But I want
296151161c6SStefan Roese			 * to avoid putting a node for it in the tree, so the numbers
297151161c6SStefan Roese			 * below are basically de-swizzled numbers.
298151161c6SStefan Roese			 * The real slot is on idsel 0, so the swizzling is 1:1
299151161c6SStefan Roese			 */
30071f34979SDavid Gibson			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
301151161c6SStefan Roese			interrupt-map = <
30271f34979SDavid Gibson				0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
30371f34979SDavid Gibson				0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
30471f34979SDavid Gibson				0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
30571f34979SDavid Gibson				0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
306151161c6SStefan Roese		};
307151161c6SStefan Roese
308151161c6SStefan Roese		PCIE1: pciex@0c0000000 {
309151161c6SStefan Roese			device_type = "pci";
310151161c6SStefan Roese			#interrupt-cells = <1>;
311151161c6SStefan Roese			#size-cells = <2>;
312151161c6SStefan Roese			#address-cells = <3>;
313151161c6SStefan Roese			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
314151161c6SStefan Roese			primary;
31571f34979SDavid Gibson			port = <0x1>; /* port number */
31671f34979SDavid Gibson			reg = <0xc0000000 0x20000000	/* Config space access */
31771f34979SDavid Gibson			       0xef001000 0x00001000>;	/* Registers */
31871f34979SDavid Gibson			dcr-reg = <0x060 0x020>;
31971f34979SDavid Gibson			sdr-base = <0x440>;
320151161c6SStefan Roese
321151161c6SStefan Roese			/* Outbound ranges, one memory and one IO,
322151161c6SStefan Roese			 * later cannot be changed
323151161c6SStefan Roese			 */
32471f34979SDavid Gibson			ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
32571f34979SDavid Gibson				  0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
326151161c6SStefan Roese
327151161c6SStefan Roese			/* Inbound 2GB range starting at 0 */
32871f34979SDavid Gibson			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
329151161c6SStefan Roese
330dc88416bSStefan Roese			/* This drives busses 0x40 to 0x7f */
33171f34979SDavid Gibson			bus-range = <0x40 0x7f>;
332151161c6SStefan Roese
333151161c6SStefan Roese			/* Legacy interrupts (note the weird polarity, the bridge seems
334151161c6SStefan Roese			 * to invert PCIe legacy interrupts).
335151161c6SStefan Roese			 * We are de-swizzling here because the numbers are actually for
336151161c6SStefan Roese			 * port of the root complex virtual P2P bridge. But I want
337151161c6SStefan Roese			 * to avoid putting a node for it in the tree, so the numbers
338151161c6SStefan Roese			 * below are basically de-swizzled numbers.
339151161c6SStefan Roese			 * The real slot is on idsel 0, so the swizzling is 1:1
340151161c6SStefan Roese			 */
34171f34979SDavid Gibson			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
342151161c6SStefan Roese			interrupt-map = <
34371f34979SDavid Gibson				0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
34471f34979SDavid Gibson				0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
34571f34979SDavid Gibson				0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
34671f34979SDavid Gibson				0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
347151161c6SStefan Roese		};
348a62f48deSStefan Roese	};
349a62f48deSStefan Roese};
350