1a62f48deSStefan Roese/* 2a62f48deSStefan Roese * Device Tree Source for AMCC Kilauea (405EX) 3a62f48deSStefan Roese * 4a62f48deSStefan Roese * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> 5a62f48deSStefan Roese * 6a62f48deSStefan Roese * This file is licensed under the terms of the GNU General Public 7a62f48deSStefan Roese * License version 2. This program is licensed "as is" without 8a62f48deSStefan Roese * any warranty of any kind, whether express or implied. 9a62f48deSStefan Roese */ 10a62f48deSStefan Roese 11a62f48deSStefan Roese/ { 12a62f48deSStefan Roese #address-cells = <1>; 13a62f48deSStefan Roese #size-cells = <1>; 14a62f48deSStefan Roese model = "amcc,kilauea"; 15a62f48deSStefan Roese compatible = "amcc,kilauea"; 1672fda114SJosh Boyer dcr-parent = <&/cpus/cpu@0>; 17a62f48deSStefan Roese 188aaed98cSStefan Roese aliases { 198aaed98cSStefan Roese ethernet0 = &EMAC0; 208aaed98cSStefan Roese ethernet1 = &EMAC1; 218aaed98cSStefan Roese serial0 = &UART0; 228aaed98cSStefan Roese serial1 = &UART1; 238aaed98cSStefan Roese }; 248aaed98cSStefan Roese 25a62f48deSStefan Roese cpus { 26a62f48deSStefan Roese #address-cells = <1>; 27a62f48deSStefan Roese #size-cells = <0>; 28a62f48deSStefan Roese 2972fda114SJosh Boyer cpu@0 { 30a62f48deSStefan Roese device_type = "cpu"; 3172fda114SJosh Boyer model = "PowerPC,405EX"; 32a62f48deSStefan Roese reg = <0>; 33a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 34a62f48deSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 35a62f48deSStefan Roese i-cache-line-size = <20>; 36a62f48deSStefan Roese d-cache-line-size = <20>; 37a62f48deSStefan Roese i-cache-size = <4000>; /* 16 kB */ 38a62f48deSStefan Roese d-cache-size = <4000>; /* 16 kB */ 39a62f48deSStefan Roese dcr-controller; 40a62f48deSStefan Roese dcr-access-method = "native"; 41a62f48deSStefan Roese }; 42a62f48deSStefan Roese }; 43a62f48deSStefan Roese 44a62f48deSStefan Roese memory { 45a62f48deSStefan Roese device_type = "memory"; 46a62f48deSStefan Roese reg = <0 0>; /* Filled in by U-Boot */ 47a62f48deSStefan Roese }; 48a62f48deSStefan Roese 49a62f48deSStefan Roese UIC0: interrupt-controller { 50a62f48deSStefan Roese compatible = "ibm,uic-405ex", "ibm,uic"; 51a62f48deSStefan Roese interrupt-controller; 52a62f48deSStefan Roese cell-index = <0>; 53a62f48deSStefan Roese dcr-reg = <0c0 009>; 54a62f48deSStefan Roese #address-cells = <0>; 55a62f48deSStefan Roese #size-cells = <0>; 56a62f48deSStefan Roese #interrupt-cells = <2>; 57a62f48deSStefan Roese }; 58a62f48deSStefan Roese 59a62f48deSStefan Roese UIC1: interrupt-controller1 { 60a62f48deSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 61a62f48deSStefan Roese interrupt-controller; 62a62f48deSStefan Roese cell-index = <1>; 63a62f48deSStefan Roese dcr-reg = <0d0 009>; 64a62f48deSStefan Roese #address-cells = <0>; 65a62f48deSStefan Roese #size-cells = <0>; 66a62f48deSStefan Roese #interrupt-cells = <2>; 67a62f48deSStefan Roese interrupts = <1e 4 1f 4>; /* cascade */ 68a62f48deSStefan Roese interrupt-parent = <&UIC0>; 69a62f48deSStefan Roese }; 70a62f48deSStefan Roese 71a62f48deSStefan Roese UIC2: interrupt-controller2 { 72a62f48deSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 73a62f48deSStefan Roese interrupt-controller; 74a62f48deSStefan Roese cell-index = <2>; 75a62f48deSStefan Roese dcr-reg = <0e0 009>; 76a62f48deSStefan Roese #address-cells = <0>; 77a62f48deSStefan Roese #size-cells = <0>; 78a62f48deSStefan Roese #interrupt-cells = <2>; 79a62f48deSStefan Roese interrupts = <1c 4 1d 4>; /* cascade */ 80a62f48deSStefan Roese interrupt-parent = <&UIC0>; 81a62f48deSStefan Roese }; 82a62f48deSStefan Roese 83a62f48deSStefan Roese plb { 84a62f48deSStefan Roese compatible = "ibm,plb-405ex", "ibm,plb4"; 85a62f48deSStefan Roese #address-cells = <1>; 86a62f48deSStefan Roese #size-cells = <1>; 87a62f48deSStefan Roese ranges; 88a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 89a62f48deSStefan Roese 90a62f48deSStefan Roese SDRAM0: memory-controller { 91a62f48deSStefan Roese compatible = "ibm,sdram-405ex"; 92a62f48deSStefan Roese dcr-reg = <010 2>; 93a62f48deSStefan Roese }; 94a62f48deSStefan Roese 95a62f48deSStefan Roese MAL0: mcmal { 96a62f48deSStefan Roese compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 97a62f48deSStefan Roese dcr-reg = <180 62>; 98a62f48deSStefan Roese num-tx-chans = <2>; 99a62f48deSStefan Roese num-rx-chans = <2>; 100a62f48deSStefan Roese interrupt-parent = <&MAL0>; 101a62f48deSStefan Roese interrupts = <0 1 2 3 4>; 102a62f48deSStefan Roese #interrupt-cells = <1>; 103a62f48deSStefan Roese #address-cells = <0>; 104a62f48deSStefan Roese #size-cells = <0>; 105a62f48deSStefan Roese interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 106a62f48deSStefan Roese /*RXEOB*/ 1 &UIC0 b 4 107a62f48deSStefan Roese /*SERR*/ 2 &UIC1 0 4 108a62f48deSStefan Roese /*TXDE*/ 3 &UIC1 1 4 109a62f48deSStefan Roese /*RXDE*/ 4 &UIC1 2 4>; 110a62f48deSStefan Roese interrupt-map-mask = <ffffffff>; 111a62f48deSStefan Roese }; 112a62f48deSStefan Roese 113a62f48deSStefan Roese POB0: opb { 114a62f48deSStefan Roese compatible = "ibm,opb-405ex", "ibm,opb"; 115a62f48deSStefan Roese #address-cells = <1>; 116a62f48deSStefan Roese #size-cells = <1>; 117a62f48deSStefan Roese ranges = <80000000 80000000 10000000 118a62f48deSStefan Roese ef600000 ef600000 a00000 119a62f48deSStefan Roese f0000000 f0000000 10000000>; 120a62f48deSStefan Roese dcr-reg = <0a0 5>; 121a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 122a62f48deSStefan Roese 123a62f48deSStefan Roese EBC0: ebc { 124a62f48deSStefan Roese compatible = "ibm,ebc-405ex", "ibm,ebc"; 125a62f48deSStefan Roese dcr-reg = <012 2>; 126a62f48deSStefan Roese #address-cells = <2>; 127a62f48deSStefan Roese #size-cells = <1>; 128a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 129a62f48deSStefan Roese /* ranges property is supplied by U-Boot */ 130a62f48deSStefan Roese interrupts = <5 1>; 131a62f48deSStefan Roese interrupt-parent = <&UIC1>; 132a62f48deSStefan Roese 133a62f48deSStefan Roese nor_flash@0,0 { 134a62f48deSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 135a62f48deSStefan Roese bank-width = <2>; 136a62f48deSStefan Roese reg = <0 000000 4000000>; 137a62f48deSStefan Roese #address-cells = <1>; 138a62f48deSStefan Roese #size-cells = <1>; 139a62f48deSStefan Roese partition@0 { 140a62f48deSStefan Roese label = "kernel"; 141a62f48deSStefan Roese reg = <0 200000>; 142a62f48deSStefan Roese }; 143a62f48deSStefan Roese partition@200000 { 144a62f48deSStefan Roese label = "root"; 145a62f48deSStefan Roese reg = <200000 200000>; 146a62f48deSStefan Roese }; 147a62f48deSStefan Roese partition@400000 { 148a62f48deSStefan Roese label = "user"; 149a62f48deSStefan Roese reg = <400000 3b60000>; 150a62f48deSStefan Roese }; 151a62f48deSStefan Roese partition@3f60000 { 152a62f48deSStefan Roese label = "env"; 153a62f48deSStefan Roese reg = <3f60000 40000>; 154a62f48deSStefan Roese }; 155a62f48deSStefan Roese partition@3fa0000 { 156a62f48deSStefan Roese label = "u-boot"; 157a62f48deSStefan Roese reg = <3fa0000 60000>; 158a62f48deSStefan Roese }; 159a62f48deSStefan Roese }; 160a62f48deSStefan Roese }; 161a62f48deSStefan Roese 162a62f48deSStefan Roese UART0: serial@ef600200 { 163a62f48deSStefan Roese device_type = "serial"; 164a62f48deSStefan Roese compatible = "ns16550"; 165a62f48deSStefan Roese reg = <ef600200 8>; 166a62f48deSStefan Roese virtual-reg = <ef600200>; 167a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 168a62f48deSStefan Roese current-speed = <0>; 169a62f48deSStefan Roese interrupt-parent = <&UIC0>; 170a62f48deSStefan Roese interrupts = <1a 4>; 171a62f48deSStefan Roese }; 172a62f48deSStefan Roese 173a62f48deSStefan Roese UART1: serial@ef600300 { 174a62f48deSStefan Roese device_type = "serial"; 175a62f48deSStefan Roese compatible = "ns16550"; 176a62f48deSStefan Roese reg = <ef600300 8>; 177a62f48deSStefan Roese virtual-reg = <ef600300>; 178a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 179a62f48deSStefan Roese current-speed = <0>; 180a62f48deSStefan Roese interrupt-parent = <&UIC0>; 181a62f48deSStefan Roese interrupts = <1 4>; 182a62f48deSStefan Roese }; 183a62f48deSStefan Roese 184a62f48deSStefan Roese IIC0: i2c@ef600400 { 185a62f48deSStefan Roese device_type = "i2c"; 186a62f48deSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 187a62f48deSStefan Roese reg = <ef600400 14>; 188a62f48deSStefan Roese interrupt-parent = <&UIC0>; 189a62f48deSStefan Roese interrupts = <2 4>; 190a62f48deSStefan Roese }; 191a62f48deSStefan Roese 192a62f48deSStefan Roese IIC1: i2c@ef600500 { 193a62f48deSStefan Roese device_type = "i2c"; 194a62f48deSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 195a62f48deSStefan Roese reg = <ef600500 14>; 196a62f48deSStefan Roese interrupt-parent = <&UIC0>; 197a62f48deSStefan Roese interrupts = <7 4>; 198a62f48deSStefan Roese }; 199a62f48deSStefan Roese 200a62f48deSStefan Roese 201a62f48deSStefan Roese RGMII0: emac-rgmii@ef600b00 { 202a62f48deSStefan Roese device_type = "rgmii-interface"; 203a62f48deSStefan Roese compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 204a62f48deSStefan Roese reg = <ef600b00 104>; 2050a6ea8beSStefan Roese has-mdio; 206a62f48deSStefan Roese }; 207a62f48deSStefan Roese 208a62f48deSStefan Roese EMAC0: ethernet@ef600900 { 209a62f48deSStefan Roese linux,network-index = <0>; 210a62f48deSStefan Roese device_type = "network"; 211a62f48deSStefan Roese compatible = "ibm,emac-405ex", "ibm,emac4"; 212a62f48deSStefan Roese interrupt-parent = <&EMAC0>; 213a62f48deSStefan Roese interrupts = <0 1>; 214a62f48deSStefan Roese #interrupt-cells = <1>; 215a62f48deSStefan Roese #address-cells = <0>; 216a62f48deSStefan Roese #size-cells = <0>; 217a62f48deSStefan Roese interrupt-map = </*Status*/ 0 &UIC0 18 4 218a62f48deSStefan Roese /*Wake*/ 1 &UIC1 1d 4>; 219a62f48deSStefan Roese reg = <ef600900 70>; 220a62f48deSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 221a62f48deSStefan Roese mal-device = <&MAL0>; 222a62f48deSStefan Roese mal-tx-channel = <0>; 223a62f48deSStefan Roese mal-rx-channel = <0>; 224a62f48deSStefan Roese cell-index = <0>; 225a62f48deSStefan Roese max-frame-size = <5dc>; 226a62f48deSStefan Roese rx-fifo-size = <1000>; 227a62f48deSStefan Roese tx-fifo-size = <800>; 228a62f48deSStefan Roese phy-mode = "rgmii"; 229a62f48deSStefan Roese phy-map = <00000000>; 230a62f48deSStefan Roese rgmii-device = <&RGMII0>; 231a62f48deSStefan Roese rgmii-channel = <0>; 2320a6ea8beSStefan Roese has-inverted-stacr-oc; 2330a6ea8beSStefan Roese has-new-stacr-staopc; 234a62f48deSStefan Roese }; 235a62f48deSStefan Roese 236a62f48deSStefan Roese EMAC1: ethernet@ef600a00 { 237a62f48deSStefan Roese linux,network-index = <1>; 238a62f48deSStefan Roese device_type = "network"; 239a62f48deSStefan Roese compatible = "ibm,emac-405ex", "ibm,emac4"; 240a62f48deSStefan Roese interrupt-parent = <&EMAC1>; 241a62f48deSStefan Roese interrupts = <0 1>; 242a62f48deSStefan Roese #interrupt-cells = <1>; 243a62f48deSStefan Roese #address-cells = <0>; 244a62f48deSStefan Roese #size-cells = <0>; 245a62f48deSStefan Roese interrupt-map = </*Status*/ 0 &UIC0 19 4 246a62f48deSStefan Roese /*Wake*/ 1 &UIC1 1f 4>; 247a62f48deSStefan Roese reg = <ef600a00 70>; 248a62f48deSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 249a62f48deSStefan Roese mal-device = <&MAL0>; 250a62f48deSStefan Roese mal-tx-channel = <1>; 251a62f48deSStefan Roese mal-rx-channel = <1>; 252a62f48deSStefan Roese cell-index = <1>; 253a62f48deSStefan Roese max-frame-size = <5dc>; 254a62f48deSStefan Roese rx-fifo-size = <1000>; 255a62f48deSStefan Roese tx-fifo-size = <800>; 256a62f48deSStefan Roese phy-mode = "rgmii"; 257a62f48deSStefan Roese phy-map = <00000000>; 258a62f48deSStefan Roese rgmii-device = <&RGMII0>; 259a62f48deSStefan Roese rgmii-channel = <1>; 2600a6ea8beSStefan Roese has-inverted-stacr-oc; 2610a6ea8beSStefan Roese has-new-stacr-staopc; 262a62f48deSStefan Roese }; 263a62f48deSStefan Roese }; 264151161c6SStefan Roese 265151161c6SStefan Roese PCIE0: pciex@0a0000000 { 266151161c6SStefan Roese device_type = "pci"; 267151161c6SStefan Roese #interrupt-cells = <1>; 268151161c6SStefan Roese #size-cells = <2>; 269151161c6SStefan Roese #address-cells = <3>; 270151161c6SStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 271151161c6SStefan Roese primary; 272151161c6SStefan Roese port = <0>; /* port number */ 273151161c6SStefan Roese reg = <a0000000 20000000 /* Config space access */ 274151161c6SStefan Roese ef000000 00001000>; /* Registers */ 275151161c6SStefan Roese dcr-reg = <040 020>; 276151161c6SStefan Roese sdr-base = <400>; 277151161c6SStefan Roese 278151161c6SStefan Roese /* Outbound ranges, one memory and one IO, 279151161c6SStefan Roese * later cannot be changed 280151161c6SStefan Roese */ 281151161c6SStefan Roese ranges = <02000000 0 80000000 90000000 0 08000000 282151161c6SStefan Roese 01000000 0 00000000 e0000000 0 00010000>; 283151161c6SStefan Roese 284151161c6SStefan Roese /* Inbound 2GB range starting at 0 */ 285151161c6SStefan Roese dma-ranges = <42000000 0 0 0 0 80000000>; 286151161c6SStefan Roese 287151161c6SStefan Roese /* This drives busses 0x00 to 0x0f */ 288151161c6SStefan Roese bus-range = <00 0f>; 289151161c6SStefan Roese 290151161c6SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 291151161c6SStefan Roese * to invert PCIe legacy interrupts). 292151161c6SStefan Roese * We are de-swizzling here because the numbers are actually for 293151161c6SStefan Roese * port of the root complex virtual P2P bridge. But I want 294151161c6SStefan Roese * to avoid putting a node for it in the tree, so the numbers 295151161c6SStefan Roese * below are basically de-swizzled numbers. 296151161c6SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 297151161c6SStefan Roese */ 298151161c6SStefan Roese interrupt-map-mask = <0000 0 0 7>; 299151161c6SStefan Roese interrupt-map = < 300151161c6SStefan Roese 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ 301151161c6SStefan Roese 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ 302151161c6SStefan Roese 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ 303151161c6SStefan Roese 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; 304151161c6SStefan Roese }; 305151161c6SStefan Roese 306151161c6SStefan Roese PCIE1: pciex@0c0000000 { 307151161c6SStefan Roese device_type = "pci"; 308151161c6SStefan Roese #interrupt-cells = <1>; 309151161c6SStefan Roese #size-cells = <2>; 310151161c6SStefan Roese #address-cells = <3>; 311151161c6SStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 312151161c6SStefan Roese primary; 313151161c6SStefan Roese port = <1>; /* port number */ 314151161c6SStefan Roese reg = <c0000000 20000000 /* Config space access */ 315151161c6SStefan Roese ef001000 00001000>; /* Registers */ 316151161c6SStefan Roese dcr-reg = <060 020>; 317151161c6SStefan Roese sdr-base = <440>; 318151161c6SStefan Roese 319151161c6SStefan Roese /* Outbound ranges, one memory and one IO, 320151161c6SStefan Roese * later cannot be changed 321151161c6SStefan Roese */ 322151161c6SStefan Roese ranges = <02000000 0 80000000 98000000 0 08000000 323151161c6SStefan Roese 01000000 0 00000000 e0010000 0 00010000>; 324151161c6SStefan Roese 325151161c6SStefan Roese /* Inbound 2GB range starting at 0 */ 326151161c6SStefan Roese dma-ranges = <42000000 0 0 0 0 80000000>; 327151161c6SStefan Roese 328151161c6SStefan Roese /* This drives busses 0x10 to 0x1f */ 329151161c6SStefan Roese bus-range = <10 1f>; 330151161c6SStefan Roese 331151161c6SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 332151161c6SStefan Roese * to invert PCIe legacy interrupts). 333151161c6SStefan Roese * We are de-swizzling here because the numbers are actually for 334151161c6SStefan Roese * port of the root complex virtual P2P bridge. But I want 335151161c6SStefan Roese * to avoid putting a node for it in the tree, so the numbers 336151161c6SStefan Roese * below are basically de-swizzled numbers. 337151161c6SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 338151161c6SStefan Roese */ 339151161c6SStefan Roese interrupt-map-mask = <0000 0 0 7>; 340151161c6SStefan Roese interrupt-map = < 341151161c6SStefan Roese 0000 0 0 1 &UIC2 b 4 /* swizzled int A */ 342151161c6SStefan Roese 0000 0 0 2 &UIC2 c 4 /* swizzled int B */ 343151161c6SStefan Roese 0000 0 0 3 &UIC2 d 4 /* swizzled int C */ 344151161c6SStefan Roese 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>; 345151161c6SStefan Roese }; 346a62f48deSStefan Roese }; 347a62f48deSStefan Roese}; 348