1a62f48deSStefan Roese/*
2a62f48deSStefan Roese * Device Tree Source for AMCC Kilauea (405EX)
3a62f48deSStefan Roese *
4a62f48deSStefan Roese * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
5a62f48deSStefan Roese *
6a62f48deSStefan Roese * This file is licensed under the terms of the GNU General Public
7a62f48deSStefan Roese * License version 2.  This program is licensed "as is" without
8a62f48deSStefan Roese * any warranty of any kind, whether express or implied.
9a62f48deSStefan Roese */
10a62f48deSStefan Roese
11a62f48deSStefan Roese/ {
12a62f48deSStefan Roese	#address-cells = <1>;
13a62f48deSStefan Roese	#size-cells = <1>;
14a62f48deSStefan Roese	model = "amcc,kilauea";
15a62f48deSStefan Roese	compatible = "amcc,kilauea";
1672fda114SJosh Boyer	dcr-parent = <&/cpus/cpu@0>;
17a62f48deSStefan Roese
18a62f48deSStefan Roese	cpus {
19a62f48deSStefan Roese		#address-cells = <1>;
20a62f48deSStefan Roese		#size-cells = <0>;
21a62f48deSStefan Roese
2272fda114SJosh Boyer		cpu@0 {
23a62f48deSStefan Roese			device_type = "cpu";
2472fda114SJosh Boyer			model = "PowerPC,405EX";
25a62f48deSStefan Roese			reg = <0>;
26a62f48deSStefan Roese			clock-frequency = <0>; /* Filled in by U-Boot */
27a62f48deSStefan Roese			timebase-frequency = <0>; /* Filled in by U-Boot */
28a62f48deSStefan Roese			i-cache-line-size = <20>;
29a62f48deSStefan Roese			d-cache-line-size = <20>;
30a62f48deSStefan Roese			i-cache-size = <4000>; /* 16 kB */
31a62f48deSStefan Roese			d-cache-size = <4000>; /* 16 kB */
32a62f48deSStefan Roese			dcr-controller;
33a62f48deSStefan Roese			dcr-access-method = "native";
34a62f48deSStefan Roese		};
35a62f48deSStefan Roese	};
36a62f48deSStefan Roese
37a62f48deSStefan Roese	memory {
38a62f48deSStefan Roese		device_type = "memory";
39a62f48deSStefan Roese		reg = <0 0>; /* Filled in by U-Boot */
40a62f48deSStefan Roese	};
41a62f48deSStefan Roese
42a62f48deSStefan Roese	UIC0: interrupt-controller {
43a62f48deSStefan Roese		compatible = "ibm,uic-405ex", "ibm,uic";
44a62f48deSStefan Roese		interrupt-controller;
45a62f48deSStefan Roese		cell-index = <0>;
46a62f48deSStefan Roese		dcr-reg = <0c0 009>;
47a62f48deSStefan Roese		#address-cells = <0>;
48a62f48deSStefan Roese		#size-cells = <0>;
49a62f48deSStefan Roese		#interrupt-cells = <2>;
50a62f48deSStefan Roese	};
51a62f48deSStefan Roese
52a62f48deSStefan Roese	UIC1: interrupt-controller1 {
53a62f48deSStefan Roese		compatible = "ibm,uic-405ex","ibm,uic";
54a62f48deSStefan Roese		interrupt-controller;
55a62f48deSStefan Roese		cell-index = <1>;
56a62f48deSStefan Roese		dcr-reg = <0d0 009>;
57a62f48deSStefan Roese		#address-cells = <0>;
58a62f48deSStefan Roese		#size-cells = <0>;
59a62f48deSStefan Roese		#interrupt-cells = <2>;
60a62f48deSStefan Roese		interrupts = <1e 4 1f 4>; /* cascade */
61a62f48deSStefan Roese		interrupt-parent = <&UIC0>;
62a62f48deSStefan Roese	};
63a62f48deSStefan Roese
64a62f48deSStefan Roese	UIC2: interrupt-controller2 {
65a62f48deSStefan Roese		compatible = "ibm,uic-405ex","ibm,uic";
66a62f48deSStefan Roese		interrupt-controller;
67a62f48deSStefan Roese		cell-index = <2>;
68a62f48deSStefan Roese		dcr-reg = <0e0 009>;
69a62f48deSStefan Roese		#address-cells = <0>;
70a62f48deSStefan Roese		#size-cells = <0>;
71a62f48deSStefan Roese		#interrupt-cells = <2>;
72a62f48deSStefan Roese		interrupts = <1c 4 1d 4>; /* cascade */
73a62f48deSStefan Roese		interrupt-parent = <&UIC0>;
74a62f48deSStefan Roese	};
75a62f48deSStefan Roese
76a62f48deSStefan Roese	plb {
77a62f48deSStefan Roese		compatible = "ibm,plb-405ex", "ibm,plb4";
78a62f48deSStefan Roese		#address-cells = <1>;
79a62f48deSStefan Roese		#size-cells = <1>;
80a62f48deSStefan Roese		ranges;
81a62f48deSStefan Roese		clock-frequency = <0>; /* Filled in by U-Boot */
82a62f48deSStefan Roese
83a62f48deSStefan Roese		SDRAM0: memory-controller {
84a62f48deSStefan Roese			compatible = "ibm,sdram-405ex";
85a62f48deSStefan Roese			dcr-reg = <010 2>;
86a62f48deSStefan Roese		};
87a62f48deSStefan Roese
88a62f48deSStefan Roese		MAL0: mcmal {
89a62f48deSStefan Roese			compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
90a62f48deSStefan Roese			dcr-reg = <180 62>;
91a62f48deSStefan Roese			num-tx-chans = <2>;
92a62f48deSStefan Roese			num-rx-chans = <2>;
93a62f48deSStefan Roese			interrupt-parent = <&MAL0>;
94a62f48deSStefan Roese			interrupts = <0 1 2 3 4>;
95a62f48deSStefan Roese			#interrupt-cells = <1>;
96a62f48deSStefan Roese			#address-cells = <0>;
97a62f48deSStefan Roese			#size-cells = <0>;
98a62f48deSStefan Roese			interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
99a62f48deSStefan Roese					/*RXEOB*/ 1 &UIC0 b 4
100a62f48deSStefan Roese					/*SERR*/  2 &UIC1 0 4
101a62f48deSStefan Roese					/*TXDE*/  3 &UIC1 1 4
102a62f48deSStefan Roese					/*RXDE*/  4 &UIC1 2 4>;
103a62f48deSStefan Roese			interrupt-map-mask = <ffffffff>;
104a62f48deSStefan Roese		};
105a62f48deSStefan Roese
106a62f48deSStefan Roese		POB0: opb {
107a62f48deSStefan Roese			compatible = "ibm,opb-405ex", "ibm,opb";
108a62f48deSStefan Roese			#address-cells = <1>;
109a62f48deSStefan Roese			#size-cells = <1>;
110a62f48deSStefan Roese			ranges = <80000000 80000000 10000000
111a62f48deSStefan Roese				  ef600000 ef600000 a00000
112a62f48deSStefan Roese				  f0000000 f0000000 10000000>;
113a62f48deSStefan Roese			dcr-reg = <0a0 5>;
114a62f48deSStefan Roese			clock-frequency = <0>; /* Filled in by U-Boot */
115a62f48deSStefan Roese
116a62f48deSStefan Roese			EBC0: ebc {
117a62f48deSStefan Roese				compatible = "ibm,ebc-405ex", "ibm,ebc";
118a62f48deSStefan Roese				dcr-reg = <012 2>;
119a62f48deSStefan Roese				#address-cells = <2>;
120a62f48deSStefan Roese				#size-cells = <1>;
121a62f48deSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
122a62f48deSStefan Roese				/* ranges property is supplied by U-Boot */
123a62f48deSStefan Roese				interrupts = <5 1>;
124a62f48deSStefan Roese				interrupt-parent = <&UIC1>;
125a62f48deSStefan Roese
126a62f48deSStefan Roese				nor_flash@0,0 {
127a62f48deSStefan Roese					compatible = "amd,s29gl512n", "cfi-flash";
128a62f48deSStefan Roese					bank-width = <2>;
129a62f48deSStefan Roese					reg = <0 000000 4000000>;
130a62f48deSStefan Roese					#address-cells = <1>;
131a62f48deSStefan Roese					#size-cells = <1>;
132a62f48deSStefan Roese					partition@0 {
133a62f48deSStefan Roese						label = "kernel";
134a62f48deSStefan Roese						reg = <0 200000>;
135a62f48deSStefan Roese					};
136a62f48deSStefan Roese					partition@200000 {
137a62f48deSStefan Roese						label = "root";
138a62f48deSStefan Roese						reg = <200000 200000>;
139a62f48deSStefan Roese					};
140a62f48deSStefan Roese					partition@400000 {
141a62f48deSStefan Roese						label = "user";
142a62f48deSStefan Roese						reg = <400000 3b60000>;
143a62f48deSStefan Roese					};
144a62f48deSStefan Roese					partition@3f60000 {
145a62f48deSStefan Roese						label = "env";
146a62f48deSStefan Roese						reg = <3f60000 40000>;
147a62f48deSStefan Roese					};
148a62f48deSStefan Roese					partition@3fa0000 {
149a62f48deSStefan Roese						label = "u-boot";
150a62f48deSStefan Roese						reg = <3fa0000 60000>;
151a62f48deSStefan Roese					};
152a62f48deSStefan Roese				};
153a62f48deSStefan Roese			};
154a62f48deSStefan Roese
155a62f48deSStefan Roese			UART0: serial@ef600200 {
156a62f48deSStefan Roese				device_type = "serial";
157a62f48deSStefan Roese				compatible = "ns16550";
158a62f48deSStefan Roese				reg = <ef600200 8>;
159a62f48deSStefan Roese				virtual-reg = <ef600200>;
160a62f48deSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
161a62f48deSStefan Roese				current-speed = <0>;
162a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
163a62f48deSStefan Roese				interrupts = <1a 4>;
164a62f48deSStefan Roese			};
165a62f48deSStefan Roese
166a62f48deSStefan Roese			UART1: serial@ef600300 {
167a62f48deSStefan Roese				device_type = "serial";
168a62f48deSStefan Roese				compatible = "ns16550";
169a62f48deSStefan Roese				reg = <ef600300 8>;
170a62f48deSStefan Roese				virtual-reg = <ef600300>;
171a62f48deSStefan Roese				clock-frequency = <0>; /* Filled in by U-Boot */
172a62f48deSStefan Roese				current-speed = <0>;
173a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
174a62f48deSStefan Roese				interrupts = <1 4>;
175a62f48deSStefan Roese			};
176a62f48deSStefan Roese
177a62f48deSStefan Roese			IIC0: i2c@ef600400 {
178a62f48deSStefan Roese				device_type = "i2c";
179a62f48deSStefan Roese				compatible = "ibm,iic-405ex", "ibm,iic";
180a62f48deSStefan Roese				reg = <ef600400 14>;
181a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
182a62f48deSStefan Roese				interrupts = <2 4>;
183a62f48deSStefan Roese			};
184a62f48deSStefan Roese
185a62f48deSStefan Roese			IIC1: i2c@ef600500 {
186a62f48deSStefan Roese				device_type = "i2c";
187a62f48deSStefan Roese				compatible = "ibm,iic-405ex", "ibm,iic";
188a62f48deSStefan Roese				reg = <ef600500 14>;
189a62f48deSStefan Roese				interrupt-parent = <&UIC0>;
190a62f48deSStefan Roese				interrupts = <7 4>;
191a62f48deSStefan Roese			};
192a62f48deSStefan Roese
193a62f48deSStefan Roese
194a62f48deSStefan Roese			RGMII0: emac-rgmii@ef600b00 {
195a62f48deSStefan Roese				device_type = "rgmii-interface";
196a62f48deSStefan Roese				compatible = "ibm,rgmii-405ex", "ibm,rgmii";
197a62f48deSStefan Roese				reg = <ef600b00 104>;
1980a6ea8beSStefan Roese				has-mdio;
199a62f48deSStefan Roese			};
200a62f48deSStefan Roese
201a62f48deSStefan Roese			EMAC0: ethernet@ef600900 {
202a62f48deSStefan Roese				linux,network-index = <0>;
203a62f48deSStefan Roese				device_type = "network";
204a62f48deSStefan Roese				compatible = "ibm,emac-405ex", "ibm,emac4";
205a62f48deSStefan Roese				interrupt-parent = <&EMAC0>;
206a62f48deSStefan Roese				interrupts = <0 1>;
207a62f48deSStefan Roese				#interrupt-cells = <1>;
208a62f48deSStefan Roese				#address-cells = <0>;
209a62f48deSStefan Roese				#size-cells = <0>;
210a62f48deSStefan Roese				interrupt-map = </*Status*/ 0 &UIC0 18 4
211a62f48deSStefan Roese						/*Wake*/  1 &UIC1 1d 4>;
212a62f48deSStefan Roese				reg = <ef600900 70>;
213a62f48deSStefan Roese				local-mac-address = [000000000000]; /* Filled in by U-Boot */
214a62f48deSStefan Roese				mal-device = <&MAL0>;
215a62f48deSStefan Roese				mal-tx-channel = <0>;
216a62f48deSStefan Roese				mal-rx-channel = <0>;
217a62f48deSStefan Roese				cell-index = <0>;
218a62f48deSStefan Roese				max-frame-size = <5dc>;
219a62f48deSStefan Roese				rx-fifo-size = <1000>;
220a62f48deSStefan Roese				tx-fifo-size = <800>;
221a62f48deSStefan Roese				phy-mode = "rgmii";
222a62f48deSStefan Roese				phy-map = <00000000>;
223a62f48deSStefan Roese				rgmii-device = <&RGMII0>;
224a62f48deSStefan Roese				rgmii-channel = <0>;
2250a6ea8beSStefan Roese				has-inverted-stacr-oc;
2260a6ea8beSStefan Roese				has-new-stacr-staopc;
227a62f48deSStefan Roese			};
228a62f48deSStefan Roese
229a62f48deSStefan Roese			EMAC1: ethernet@ef600a00 {
230a62f48deSStefan Roese				linux,network-index = <1>;
231a62f48deSStefan Roese				device_type = "network";
232a62f48deSStefan Roese				compatible = "ibm,emac-405ex", "ibm,emac4";
233a62f48deSStefan Roese				interrupt-parent = <&EMAC1>;
234a62f48deSStefan Roese				interrupts = <0 1>;
235a62f48deSStefan Roese				#interrupt-cells = <1>;
236a62f48deSStefan Roese				#address-cells = <0>;
237a62f48deSStefan Roese				#size-cells = <0>;
238a62f48deSStefan Roese				interrupt-map = </*Status*/ 0 &UIC0 19 4
239a62f48deSStefan Roese						/*Wake*/  1 &UIC1 1f 4>;
240a62f48deSStefan Roese				reg = <ef600a00 70>;
241a62f48deSStefan Roese				local-mac-address = [000000000000]; /* Filled in by U-Boot */
242a62f48deSStefan Roese				mal-device = <&MAL0>;
243a62f48deSStefan Roese				mal-tx-channel = <1>;
244a62f48deSStefan Roese				mal-rx-channel = <1>;
245a62f48deSStefan Roese				cell-index = <1>;
246a62f48deSStefan Roese				max-frame-size = <5dc>;
247a62f48deSStefan Roese				rx-fifo-size = <1000>;
248a62f48deSStefan Roese				tx-fifo-size = <800>;
249a62f48deSStefan Roese				phy-mode = "rgmii";
250a62f48deSStefan Roese				phy-map = <00000000>;
251a62f48deSStefan Roese				rgmii-device = <&RGMII0>;
252a62f48deSStefan Roese				rgmii-channel = <1>;
2530a6ea8beSStefan Roese				has-inverted-stacr-oc;
2540a6ea8beSStefan Roese				has-new-stacr-staopc;
255a62f48deSStefan Roese			};
256a62f48deSStefan Roese		};
257151161c6SStefan Roese
258151161c6SStefan Roese		PCIE0: pciex@0a0000000 {
259151161c6SStefan Roese			device_type = "pci";
260151161c6SStefan Roese			#interrupt-cells = <1>;
261151161c6SStefan Roese			#size-cells = <2>;
262151161c6SStefan Roese			#address-cells = <3>;
263151161c6SStefan Roese			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
264151161c6SStefan Roese			primary;
265151161c6SStefan Roese			port = <0>; /* port number */
266151161c6SStefan Roese			reg = <a0000000 20000000	/* Config space access */
267151161c6SStefan Roese			       ef000000 00001000>;	/* Registers */
268151161c6SStefan Roese			dcr-reg = <040 020>;
269151161c6SStefan Roese			sdr-base = <400>;
270151161c6SStefan Roese
271151161c6SStefan Roese			/* Outbound ranges, one memory and one IO,
272151161c6SStefan Roese			 * later cannot be changed
273151161c6SStefan Roese			 */
274151161c6SStefan Roese			ranges = <02000000 0 80000000 90000000 0 08000000
275151161c6SStefan Roese				  01000000 0 00000000 e0000000 0 00010000>;
276151161c6SStefan Roese
277151161c6SStefan Roese			/* Inbound 2GB range starting at 0 */
278151161c6SStefan Roese			dma-ranges = <42000000 0 0 0 0 80000000>;
279151161c6SStefan Roese
280151161c6SStefan Roese			/* This drives busses 0x00 to 0x0f */
281151161c6SStefan Roese			bus-range = <00 0f>;
282151161c6SStefan Roese
283151161c6SStefan Roese			/* Legacy interrupts (note the weird polarity, the bridge seems
284151161c6SStefan Roese			 * to invert PCIe legacy interrupts).
285151161c6SStefan Roese			 * We are de-swizzling here because the numbers are actually for
286151161c6SStefan Roese			 * port of the root complex virtual P2P bridge. But I want
287151161c6SStefan Roese			 * to avoid putting a node for it in the tree, so the numbers
288151161c6SStefan Roese			 * below are basically de-swizzled numbers.
289151161c6SStefan Roese			 * The real slot is on idsel 0, so the swizzling is 1:1
290151161c6SStefan Roese			 */
291151161c6SStefan Roese			interrupt-map-mask = <0000 0 0 7>;
292151161c6SStefan Roese			interrupt-map = <
293151161c6SStefan Roese				0000 0 0 1 &UIC2 0 4 /* swizzled int A */
294151161c6SStefan Roese				0000 0 0 2 &UIC2 1 4 /* swizzled int B */
295151161c6SStefan Roese				0000 0 0 3 &UIC2 2 4 /* swizzled int C */
296151161c6SStefan Roese				0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
297151161c6SStefan Roese		};
298151161c6SStefan Roese
299151161c6SStefan Roese		PCIE1: pciex@0c0000000 {
300151161c6SStefan Roese			device_type = "pci";
301151161c6SStefan Roese			#interrupt-cells = <1>;
302151161c6SStefan Roese			#size-cells = <2>;
303151161c6SStefan Roese			#address-cells = <3>;
304151161c6SStefan Roese			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
305151161c6SStefan Roese			primary;
306151161c6SStefan Roese			port = <1>; /* port number */
307151161c6SStefan Roese			reg = <c0000000 20000000	/* Config space access */
308151161c6SStefan Roese			       ef001000 00001000>;	/* Registers */
309151161c6SStefan Roese			dcr-reg = <060 020>;
310151161c6SStefan Roese			sdr-base = <440>;
311151161c6SStefan Roese
312151161c6SStefan Roese			/* Outbound ranges, one memory and one IO,
313151161c6SStefan Roese			 * later cannot be changed
314151161c6SStefan Roese			 */
315151161c6SStefan Roese			ranges = <02000000 0 80000000 98000000 0 08000000
316151161c6SStefan Roese				  01000000 0 00000000 e0010000 0 00010000>;
317151161c6SStefan Roese
318151161c6SStefan Roese			/* Inbound 2GB range starting at 0 */
319151161c6SStefan Roese			dma-ranges = <42000000 0 0 0 0 80000000>;
320151161c6SStefan Roese
321151161c6SStefan Roese			/* This drives busses 0x10 to 0x1f */
322151161c6SStefan Roese			bus-range = <10 1f>;
323151161c6SStefan Roese
324151161c6SStefan Roese			/* Legacy interrupts (note the weird polarity, the bridge seems
325151161c6SStefan Roese			 * to invert PCIe legacy interrupts).
326151161c6SStefan Roese			 * We are de-swizzling here because the numbers are actually for
327151161c6SStefan Roese			 * port of the root complex virtual P2P bridge. But I want
328151161c6SStefan Roese			 * to avoid putting a node for it in the tree, so the numbers
329151161c6SStefan Roese			 * below are basically de-swizzled numbers.
330151161c6SStefan Roese			 * The real slot is on idsel 0, so the swizzling is 1:1
331151161c6SStefan Roese			 */
332151161c6SStefan Roese			interrupt-map-mask = <0000 0 0 7>;
333151161c6SStefan Roese			interrupt-map = <
334151161c6SStefan Roese				0000 0 0 1 &UIC2 b 4 /* swizzled int A */
335151161c6SStefan Roese				0000 0 0 2 &UIC2 c 4 /* swizzled int B */
336151161c6SStefan Roese				0000 0 0 3 &UIC2 d 4 /* swizzled int C */
337151161c6SStefan Roese				0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
338151161c6SStefan Roese		};
339a62f48deSStefan Roese	};
340a62f48deSStefan Roese};
341