1a62f48deSStefan Roese/* 2a62f48deSStefan Roese * Device Tree Source for AMCC Kilauea (405EX) 3a62f48deSStefan Roese * 413ae564fSStefan Roese * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de> 5a62f48deSStefan Roese * 6a62f48deSStefan Roese * This file is licensed under the terms of the GNU General Public 7a62f48deSStefan Roese * License version 2. This program is licensed "as is" without 8a62f48deSStefan Roese * any warranty of any kind, whether express or implied. 9a62f48deSStefan Roese */ 10a62f48deSStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 13a62f48deSStefan Roese/ { 14a62f48deSStefan Roese #address-cells = <1>; 15a62f48deSStefan Roese #size-cells = <1>; 16a62f48deSStefan Roese model = "amcc,kilauea"; 17a62f48deSStefan Roese compatible = "amcc,kilauea"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 19a62f48deSStefan Roese 208aaed98cSStefan Roese aliases { 218aaed98cSStefan Roese ethernet0 = &EMAC0; 228aaed98cSStefan Roese ethernet1 = &EMAC1; 238aaed98cSStefan Roese serial0 = &UART0; 248aaed98cSStefan Roese serial1 = &UART1; 258aaed98cSStefan Roese }; 268aaed98cSStefan Roese 27a62f48deSStefan Roese cpus { 28a62f48deSStefan Roese #address-cells = <1>; 29a62f48deSStefan Roese #size-cells = <0>; 30a62f48deSStefan Roese 3172fda114SJosh Boyer cpu@0 { 32a62f48deSStefan Roese device_type = "cpu"; 3372fda114SJosh Boyer model = "PowerPC,405EX"; 3471f34979SDavid Gibson reg = <0x00000000>; 35a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 36a62f48deSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3771f34979SDavid Gibson i-cache-line-size = <32>; 3871f34979SDavid Gibson d-cache-line-size = <32>; 3971f34979SDavid Gibson i-cache-size = <16384>; /* 16 kB */ 4071f34979SDavid Gibson d-cache-size = <16384>; /* 16 kB */ 41a62f48deSStefan Roese dcr-controller; 42a62f48deSStefan Roese dcr-access-method = "native"; 43a62f48deSStefan Roese }; 44a62f48deSStefan Roese }; 45a62f48deSStefan Roese 46a62f48deSStefan Roese memory { 47a62f48deSStefan Roese device_type = "memory"; 4871f34979SDavid Gibson reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ 49a62f48deSStefan Roese }; 50a62f48deSStefan Roese 51a62f48deSStefan Roese UIC0: interrupt-controller { 52a62f48deSStefan Roese compatible = "ibm,uic-405ex", "ibm,uic"; 53a62f48deSStefan Roese interrupt-controller; 54a62f48deSStefan Roese cell-index = <0>; 5571f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 56a62f48deSStefan Roese #address-cells = <0>; 57a62f48deSStefan Roese #size-cells = <0>; 58a62f48deSStefan Roese #interrupt-cells = <2>; 59a62f48deSStefan Roese }; 60a62f48deSStefan Roese 61a62f48deSStefan Roese UIC1: interrupt-controller1 { 62a62f48deSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 63a62f48deSStefan Roese interrupt-controller; 64a62f48deSStefan Roese cell-index = <1>; 6571f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 66a62f48deSStefan Roese #address-cells = <0>; 67a62f48deSStefan Roese #size-cells = <0>; 68a62f48deSStefan Roese #interrupt-cells = <2>; 6971f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 70a62f48deSStefan Roese interrupt-parent = <&UIC0>; 71a62f48deSStefan Roese }; 72a62f48deSStefan Roese 73a62f48deSStefan Roese UIC2: interrupt-controller2 { 74a62f48deSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 75a62f48deSStefan Roese interrupt-controller; 76a62f48deSStefan Roese cell-index = <2>; 7771f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 78a62f48deSStefan Roese #address-cells = <0>; 79a62f48deSStefan Roese #size-cells = <0>; 80a62f48deSStefan Roese #interrupt-cells = <2>; 8171f34979SDavid Gibson interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ 82a62f48deSStefan Roese interrupt-parent = <&UIC0>; 83a62f48deSStefan Roese }; 84a62f48deSStefan Roese 85a62f48deSStefan Roese plb { 86a62f48deSStefan Roese compatible = "ibm,plb-405ex", "ibm,plb4"; 87a62f48deSStefan Roese #address-cells = <1>; 88a62f48deSStefan Roese #size-cells = <1>; 89a62f48deSStefan Roese ranges; 90a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 91a62f48deSStefan Roese 92a62f48deSStefan Roese SDRAM0: memory-controller { 9394ce1c58SGrant Erickson compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2"; 9471f34979SDavid Gibson dcr-reg = <0x010 0x002>; 9594ce1c58SGrant Erickson interrupt-parent = <&UIC2>; 9694ce1c58SGrant Erickson interrupts = <0x5 0x4 /* ECC DED Error */ 9794ce1c58SGrant Erickson 0x6 0x4>; /* ECC SEC Error */ 98a62f48deSStefan Roese }; 99a62f48deSStefan Roese 100049359d6SJames Hsiao CRYPTO: crypto@ef700000 { 101049359d6SJames Hsiao compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto"; 102049359d6SJames Hsiao reg = <0xef700000 0x80400>; 103049359d6SJames Hsiao interrupt-parent = <&UIC0>; 104049359d6SJames Hsiao interrupts = <0x17 0x2>; 105049359d6SJames Hsiao }; 106049359d6SJames Hsiao 107a62f48deSStefan Roese MAL0: mcmal { 108a62f48deSStefan Roese compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 10971f34979SDavid Gibson dcr-reg = <0x180 0x062>; 110a62f48deSStefan Roese num-tx-chans = <2>; 111a62f48deSStefan Roese num-rx-chans = <2>; 112a62f48deSStefan Roese interrupt-parent = <&MAL0>; 11371f34979SDavid Gibson interrupts = <0x0 0x1 0x2 0x3 0x4>; 114a62f48deSStefan Roese #interrupt-cells = <1>; 115a62f48deSStefan Roese #address-cells = <0>; 116a62f48deSStefan Roese #size-cells = <0>; 11771f34979SDavid Gibson interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 11871f34979SDavid Gibson /*RXEOB*/ 0x1 &UIC0 0xb 0x4 11971f34979SDavid Gibson /*SERR*/ 0x2 &UIC1 0x0 0x4 12071f34979SDavid Gibson /*TXDE*/ 0x3 &UIC1 0x1 0x4 12171f34979SDavid Gibson /*RXDE*/ 0x4 &UIC1 0x2 0x4>; 12271f34979SDavid Gibson interrupt-map-mask = <0xffffffff>; 123a62f48deSStefan Roese }; 124a62f48deSStefan Roese 125a62f48deSStefan Roese POB0: opb { 126a62f48deSStefan Roese compatible = "ibm,opb-405ex", "ibm,opb"; 127a62f48deSStefan Roese #address-cells = <1>; 128a62f48deSStefan Roese #size-cells = <1>; 12971f34979SDavid Gibson ranges = <0x80000000 0x80000000 0x10000000 13071f34979SDavid Gibson 0xef600000 0xef600000 0x00a00000 13171f34979SDavid Gibson 0xf0000000 0xf0000000 0x10000000>; 13271f34979SDavid Gibson dcr-reg = <0x0a0 0x005>; 133a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 134a62f48deSStefan Roese 135a62f48deSStefan Roese EBC0: ebc { 136a62f48deSStefan Roese compatible = "ibm,ebc-405ex", "ibm,ebc"; 13771f34979SDavid Gibson dcr-reg = <0x012 0x002>; 138a62f48deSStefan Roese #address-cells = <2>; 139a62f48deSStefan Roese #size-cells = <1>; 140a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 141a62f48deSStefan Roese /* ranges property is supplied by U-Boot */ 14271f34979SDavid Gibson interrupts = <0x5 0x1>; 143a62f48deSStefan Roese interrupt-parent = <&UIC1>; 144a62f48deSStefan Roese 145a62f48deSStefan Roese nor_flash@0,0 { 146a62f48deSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 147a62f48deSStefan Roese bank-width = <2>; 14871f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 149a62f48deSStefan Roese #address-cells = <1>; 150a62f48deSStefan Roese #size-cells = <1>; 151a62f48deSStefan Roese partition@0 { 152a62f48deSStefan Roese label = "kernel"; 15313ae564fSStefan Roese reg = <0x00000000 0x001e0000>; 15413ae564fSStefan Roese }; 15513ae564fSStefan Roese partition@1e0000 { 15613ae564fSStefan Roese label = "dtb"; 15713ae564fSStefan Roese reg = <0x001e0000 0x00020000>; 158a62f48deSStefan Roese }; 159a62f48deSStefan Roese partition@200000 { 160a62f48deSStefan Roese label = "root"; 16171f34979SDavid Gibson reg = <0x00200000 0x00200000>; 162a62f48deSStefan Roese }; 163a62f48deSStefan Roese partition@400000 { 164a62f48deSStefan Roese label = "user"; 16571f34979SDavid Gibson reg = <0x00400000 0x03b60000>; 166a62f48deSStefan Roese }; 167a62f48deSStefan Roese partition@3f60000 { 168a62f48deSStefan Roese label = "env"; 16971f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 170a62f48deSStefan Roese }; 171a62f48deSStefan Roese partition@3fa0000 { 172a62f48deSStefan Roese label = "u-boot"; 17371f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 174a62f48deSStefan Roese }; 175a62f48deSStefan Roese }; 17613ae564fSStefan Roese 17713ae564fSStefan Roese ndfc@1,0 { 17813ae564fSStefan Roese compatible = "ibm,ndfc"; 17913ae564fSStefan Roese reg = <0x00000001 0x00000000 0x00002000>; 18013ae564fSStefan Roese ccr = <0x00001000>; 18113ae564fSStefan Roese bank-settings = <0x80002222>; 18213ae564fSStefan Roese #address-cells = <1>; 18313ae564fSStefan Roese #size-cells = <1>; 18413ae564fSStefan Roese 18513ae564fSStefan Roese nand { 18613ae564fSStefan Roese #address-cells = <1>; 18713ae564fSStefan Roese #size-cells = <1>; 18813ae564fSStefan Roese 18913ae564fSStefan Roese partition@0 { 19013ae564fSStefan Roese label = "u-boot"; 19113ae564fSStefan Roese reg = <0x00000000 0x00100000>; 19213ae564fSStefan Roese }; 19313ae564fSStefan Roese partition@100000 { 19413ae564fSStefan Roese label = "user"; 19513ae564fSStefan Roese reg = <0x00000000 0x03f00000>; 19613ae564fSStefan Roese }; 19713ae564fSStefan Roese }; 19813ae564fSStefan Roese }; 199a62f48deSStefan Roese }; 200a62f48deSStefan Roese 201a62f48deSStefan Roese UART0: serial@ef600200 { 202a62f48deSStefan Roese device_type = "serial"; 203a62f48deSStefan Roese compatible = "ns16550"; 20471f34979SDavid Gibson reg = <0xef600200 0x00000008>; 20571f34979SDavid Gibson virtual-reg = <0xef600200>; 206a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 207a62f48deSStefan Roese current-speed = <0>; 208a62f48deSStefan Roese interrupt-parent = <&UIC0>; 20971f34979SDavid Gibson interrupts = <0x1a 0x4>; 210a62f48deSStefan Roese }; 211a62f48deSStefan Roese 212a62f48deSStefan Roese UART1: serial@ef600300 { 213a62f48deSStefan Roese device_type = "serial"; 214a62f48deSStefan Roese compatible = "ns16550"; 21571f34979SDavid Gibson reg = <0xef600300 0x00000008>; 21671f34979SDavid Gibson virtual-reg = <0xef600300>; 217a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 218a62f48deSStefan Roese current-speed = <0>; 219a62f48deSStefan Roese interrupt-parent = <&UIC0>; 22071f34979SDavid Gibson interrupts = <0x1 0x4>; 221a62f48deSStefan Roese }; 222a62f48deSStefan Roese 223a62f48deSStefan Roese IIC0: i2c@ef600400 { 224a62f48deSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 22571f34979SDavid Gibson reg = <0xef600400 0x00000014>; 226a62f48deSStefan Roese interrupt-parent = <&UIC0>; 22771f34979SDavid Gibson interrupts = <0x2 0x4>; 22813ae564fSStefan Roese #address-cells = <1>; 22913ae564fSStefan Roese #size-cells = <0>; 23013ae564fSStefan Roese 23113ae564fSStefan Roese rtc@68 { 23213ae564fSStefan Roese compatible = "dallas,ds1338"; 23313ae564fSStefan Roese reg = <0x68>; 23413ae564fSStefan Roese }; 23513ae564fSStefan Roese 23613ae564fSStefan Roese dtt@48 { 23713ae564fSStefan Roese compatible = "dallas,ds1775"; 23813ae564fSStefan Roese reg = <0x48>; 23913ae564fSStefan Roese }; 240a62f48deSStefan Roese }; 241a62f48deSStefan Roese 242a62f48deSStefan Roese IIC1: i2c@ef600500 { 243a62f48deSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 24471f34979SDavid Gibson reg = <0xef600500 0x00000014>; 245a62f48deSStefan Roese interrupt-parent = <&UIC0>; 24671f34979SDavid Gibson interrupts = <0x7 0x4>; 247a62f48deSStefan Roese }; 248a62f48deSStefan Roese 249a62f48deSStefan Roese RGMII0: emac-rgmii@ef600b00 { 250a62f48deSStefan Roese compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 25171f34979SDavid Gibson reg = <0xef600b00 0x00000104>; 2520a6ea8beSStefan Roese has-mdio; 253a62f48deSStefan Roese }; 254a62f48deSStefan Roese 255a62f48deSStefan Roese EMAC0: ethernet@ef600900 { 25671f34979SDavid Gibson linux,network-index = <0x0>; 257a62f48deSStefan Roese device_type = "network"; 25805781ccdSGrant Erickson compatible = "ibm,emac-405ex", "ibm,emac4sync"; 259a62f48deSStefan Roese interrupt-parent = <&EMAC0>; 26071f34979SDavid Gibson interrupts = <0x0 0x1>; 261a62f48deSStefan Roese #interrupt-cells = <1>; 262a62f48deSStefan Roese #address-cells = <0>; 263a62f48deSStefan Roese #size-cells = <0>; 26471f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 26571f34979SDavid Gibson /*Wake*/ 0x1 &UIC1 0x1d 0x4>; 26605781ccdSGrant Erickson reg = <0xef600900 0x000000c4>; 267a62f48deSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 268a62f48deSStefan Roese mal-device = <&MAL0>; 269a62f48deSStefan Roese mal-tx-channel = <0>; 270a62f48deSStefan Roese mal-rx-channel = <0>; 271a62f48deSStefan Roese cell-index = <0>; 27271f34979SDavid Gibson max-frame-size = <9000>; 27371f34979SDavid Gibson rx-fifo-size = <4096>; 27471f34979SDavid Gibson tx-fifo-size = <2048>; 275a62f48deSStefan Roese phy-mode = "rgmii"; 27671f34979SDavid Gibson phy-map = <0x00000000>; 277a62f48deSStefan Roese rgmii-device = <&RGMII0>; 278a62f48deSStefan Roese rgmii-channel = <0>; 2790a6ea8beSStefan Roese has-inverted-stacr-oc; 2800a6ea8beSStefan Roese has-new-stacr-staopc; 281a62f48deSStefan Roese }; 282a62f48deSStefan Roese 283a62f48deSStefan Roese EMAC1: ethernet@ef600a00 { 28471f34979SDavid Gibson linux,network-index = <0x1>; 285a62f48deSStefan Roese device_type = "network"; 28605781ccdSGrant Erickson compatible = "ibm,emac-405ex", "ibm,emac4sync"; 287a62f48deSStefan Roese interrupt-parent = <&EMAC1>; 28871f34979SDavid Gibson interrupts = <0x0 0x1>; 289a62f48deSStefan Roese #interrupt-cells = <1>; 290a62f48deSStefan Roese #address-cells = <0>; 291a62f48deSStefan Roese #size-cells = <0>; 29271f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4 29371f34979SDavid Gibson /*Wake*/ 0x1 &UIC1 0x1f 0x4>; 29405781ccdSGrant Erickson reg = <0xef600a00 0x000000c4>; 295a62f48deSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 296a62f48deSStefan Roese mal-device = <&MAL0>; 297a62f48deSStefan Roese mal-tx-channel = <1>; 298a62f48deSStefan Roese mal-rx-channel = <1>; 299a62f48deSStefan Roese cell-index = <1>; 30071f34979SDavid Gibson max-frame-size = <9000>; 30171f34979SDavid Gibson rx-fifo-size = <4096>; 30271f34979SDavid Gibson tx-fifo-size = <2048>; 303a62f48deSStefan Roese phy-mode = "rgmii"; 30471f34979SDavid Gibson phy-map = <0x00000000>; 305a62f48deSStefan Roese rgmii-device = <&RGMII0>; 306a62f48deSStefan Roese rgmii-channel = <1>; 3070a6ea8beSStefan Roese has-inverted-stacr-oc; 3080a6ea8beSStefan Roese has-new-stacr-staopc; 309a62f48deSStefan Roese }; 310a62f48deSStefan Roese }; 311151161c6SStefan Roese 312151161c6SStefan Roese PCIE0: pciex@0a0000000 { 313151161c6SStefan Roese device_type = "pci"; 314151161c6SStefan Roese #interrupt-cells = <1>; 315151161c6SStefan Roese #size-cells = <2>; 316151161c6SStefan Roese #address-cells = <3>; 317151161c6SStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 318151161c6SStefan Roese primary; 31971f34979SDavid Gibson port = <0x0>; /* port number */ 32071f34979SDavid Gibson reg = <0xa0000000 0x20000000 /* Config space access */ 32171f34979SDavid Gibson 0xef000000 0x00001000>; /* Registers */ 32271f34979SDavid Gibson dcr-reg = <0x040 0x020>; 32371f34979SDavid Gibson sdr-base = <0x400>; 324151161c6SStefan Roese 325151161c6SStefan Roese /* Outbound ranges, one memory and one IO, 326151161c6SStefan Roese * later cannot be changed 327151161c6SStefan Roese */ 32871f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 32971f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; 330151161c6SStefan Roese 331151161c6SStefan Roese /* Inbound 2GB range starting at 0 */ 33271f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 333151161c6SStefan Roese 334dc88416bSStefan Roese /* This drives busses 0x00 to 0x3f */ 33571f34979SDavid Gibson bus-range = <0x0 0x3f>; 336151161c6SStefan Roese 337151161c6SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 338151161c6SStefan Roese * to invert PCIe legacy interrupts). 339151161c6SStefan Roese * We are de-swizzling here because the numbers are actually for 340151161c6SStefan Roese * port of the root complex virtual P2P bridge. But I want 341151161c6SStefan Roese * to avoid putting a node for it in the tree, so the numbers 342151161c6SStefan Roese * below are basically de-swizzled numbers. 343151161c6SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 344151161c6SStefan Roese */ 34571f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 346151161c6SStefan Roese interrupt-map = < 34771f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ 34871f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ 34971f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ 35071f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; 351151161c6SStefan Roese }; 352151161c6SStefan Roese 353151161c6SStefan Roese PCIE1: pciex@0c0000000 { 354151161c6SStefan Roese device_type = "pci"; 355151161c6SStefan Roese #interrupt-cells = <1>; 356151161c6SStefan Roese #size-cells = <2>; 357151161c6SStefan Roese #address-cells = <3>; 358151161c6SStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 359151161c6SStefan Roese primary; 36071f34979SDavid Gibson port = <0x1>; /* port number */ 36171f34979SDavid Gibson reg = <0xc0000000 0x20000000 /* Config space access */ 36271f34979SDavid Gibson 0xef001000 0x00001000>; /* Registers */ 36371f34979SDavid Gibson dcr-reg = <0x060 0x020>; 36471f34979SDavid Gibson sdr-base = <0x440>; 365151161c6SStefan Roese 366151161c6SStefan Roese /* Outbound ranges, one memory and one IO, 367151161c6SStefan Roese * later cannot be changed 368151161c6SStefan Roese */ 36971f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 37071f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; 371151161c6SStefan Roese 372151161c6SStefan Roese /* Inbound 2GB range starting at 0 */ 37371f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 374151161c6SStefan Roese 375dc88416bSStefan Roese /* This drives busses 0x40 to 0x7f */ 37671f34979SDavid Gibson bus-range = <0x40 0x7f>; 377151161c6SStefan Roese 378151161c6SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 379151161c6SStefan Roese * to invert PCIe legacy interrupts). 380151161c6SStefan Roese * We are de-swizzling here because the numbers are actually for 381151161c6SStefan Roese * port of the root complex virtual P2P bridge. But I want 382151161c6SStefan Roese * to avoid putting a node for it in the tree, so the numbers 383151161c6SStefan Roese * below are basically de-swizzled numbers. 384151161c6SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 385151161c6SStefan Roese */ 38671f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 387151161c6SStefan Roese interrupt-map = < 38871f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ 38971f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ 39071f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ 39171f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; 392151161c6SStefan Roese }; 393a62f48deSStefan Roese }; 394a62f48deSStefan Roese}; 395