1a62f48deSStefan Roese/* 2a62f48deSStefan Roese * Device Tree Source for AMCC Kilauea (405EX) 3a62f48deSStefan Roese * 413ae564fSStefan Roese * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de> 5a62f48deSStefan Roese * 6a62f48deSStefan Roese * This file is licensed under the terms of the GNU General Public 7a62f48deSStefan Roese * License version 2. This program is licensed "as is" without 8a62f48deSStefan Roese * any warranty of any kind, whether express or implied. 9a62f48deSStefan Roese */ 10a62f48deSStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 13a62f48deSStefan Roese/ { 14a62f48deSStefan Roese #address-cells = <1>; 15a62f48deSStefan Roese #size-cells = <1>; 16a62f48deSStefan Roese model = "amcc,kilauea"; 17a62f48deSStefan Roese compatible = "amcc,kilauea"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 19a62f48deSStefan Roese 208aaed98cSStefan Roese aliases { 218aaed98cSStefan Roese ethernet0 = &EMAC0; 228aaed98cSStefan Roese ethernet1 = &EMAC1; 238aaed98cSStefan Roese serial0 = &UART0; 248aaed98cSStefan Roese serial1 = &UART1; 258aaed98cSStefan Roese }; 268aaed98cSStefan Roese 27a62f48deSStefan Roese cpus { 28a62f48deSStefan Roese #address-cells = <1>; 29a62f48deSStefan Roese #size-cells = <0>; 30a62f48deSStefan Roese 3172fda114SJosh Boyer cpu@0 { 32a62f48deSStefan Roese device_type = "cpu"; 3372fda114SJosh Boyer model = "PowerPC,405EX"; 3471f34979SDavid Gibson reg = <0x00000000>; 35a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 36a62f48deSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3771f34979SDavid Gibson i-cache-line-size = <32>; 3871f34979SDavid Gibson d-cache-line-size = <32>; 3971f34979SDavid Gibson i-cache-size = <16384>; /* 16 kB */ 4071f34979SDavid Gibson d-cache-size = <16384>; /* 16 kB */ 41a62f48deSStefan Roese dcr-controller; 42a62f48deSStefan Roese dcr-access-method = "native"; 43a62f48deSStefan Roese }; 44a62f48deSStefan Roese }; 45a62f48deSStefan Roese 46a62f48deSStefan Roese memory { 47a62f48deSStefan Roese device_type = "memory"; 4871f34979SDavid Gibson reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ 49a62f48deSStefan Roese }; 50a62f48deSStefan Roese 51a62f48deSStefan Roese UIC0: interrupt-controller { 52a62f48deSStefan Roese compatible = "ibm,uic-405ex", "ibm,uic"; 53a62f48deSStefan Roese interrupt-controller; 54a62f48deSStefan Roese cell-index = <0>; 5571f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 56a62f48deSStefan Roese #address-cells = <0>; 57a62f48deSStefan Roese #size-cells = <0>; 58a62f48deSStefan Roese #interrupt-cells = <2>; 59a62f48deSStefan Roese }; 60a62f48deSStefan Roese 61a62f48deSStefan Roese UIC1: interrupt-controller1 { 62a62f48deSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 63a62f48deSStefan Roese interrupt-controller; 64a62f48deSStefan Roese cell-index = <1>; 6571f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 66a62f48deSStefan Roese #address-cells = <0>; 67a62f48deSStefan Roese #size-cells = <0>; 68a62f48deSStefan Roese #interrupt-cells = <2>; 6971f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 70a62f48deSStefan Roese interrupt-parent = <&UIC0>; 71a62f48deSStefan Roese }; 72a62f48deSStefan Roese 73a62f48deSStefan Roese UIC2: interrupt-controller2 { 74a62f48deSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 75a62f48deSStefan Roese interrupt-controller; 76a62f48deSStefan Roese cell-index = <2>; 7771f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 78a62f48deSStefan Roese #address-cells = <0>; 79a62f48deSStefan Roese #size-cells = <0>; 80a62f48deSStefan Roese #interrupt-cells = <2>; 8171f34979SDavid Gibson interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ 82a62f48deSStefan Roese interrupt-parent = <&UIC0>; 83a62f48deSStefan Roese }; 84a62f48deSStefan Roese 8505ed6087SVictor Gallardo CPM0: cpm { 8605ed6087SVictor Gallardo compatible = "ibm,cpm"; 8705ed6087SVictor Gallardo dcr-access-method = "native"; 8805ed6087SVictor Gallardo dcr-reg = <0x0b0 0x003>; 8905ed6087SVictor Gallardo unused-units = <0x00000000>; 9005ed6087SVictor Gallardo idle-doze = <0x02000000>; 9105ed6087SVictor Gallardo standby = <0xe3e74800>; 9205ed6087SVictor Gallardo }; 9305ed6087SVictor Gallardo 94a62f48deSStefan Roese plb { 95a62f48deSStefan Roese compatible = "ibm,plb-405ex", "ibm,plb4"; 96a62f48deSStefan Roese #address-cells = <1>; 97a62f48deSStefan Roese #size-cells = <1>; 98a62f48deSStefan Roese ranges; 99a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 100a62f48deSStefan Roese 101a62f48deSStefan Roese SDRAM0: memory-controller { 10294ce1c58SGrant Erickson compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2"; 10371f34979SDavid Gibson dcr-reg = <0x010 0x002>; 10494ce1c58SGrant Erickson interrupt-parent = <&UIC2>; 10594ce1c58SGrant Erickson interrupts = <0x5 0x4 /* ECC DED Error */ 10694ce1c58SGrant Erickson 0x6 0x4>; /* ECC SEC Error */ 107a62f48deSStefan Roese }; 108a62f48deSStefan Roese 109049359d6SJames Hsiao CRYPTO: crypto@ef700000 { 110049359d6SJames Hsiao compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto"; 111049359d6SJames Hsiao reg = <0xef700000 0x80400>; 112049359d6SJames Hsiao interrupt-parent = <&UIC0>; 113049359d6SJames Hsiao interrupts = <0x17 0x2>; 114049359d6SJames Hsiao }; 115049359d6SJames Hsiao 116a62f48deSStefan Roese MAL0: mcmal { 117a62f48deSStefan Roese compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 11871f34979SDavid Gibson dcr-reg = <0x180 0x062>; 119a62f48deSStefan Roese num-tx-chans = <2>; 120a62f48deSStefan Roese num-rx-chans = <2>; 121a62f48deSStefan Roese interrupt-parent = <&MAL0>; 12271f34979SDavid Gibson interrupts = <0x0 0x1 0x2 0x3 0x4>; 123a62f48deSStefan Roese #interrupt-cells = <1>; 124a62f48deSStefan Roese #address-cells = <0>; 125a62f48deSStefan Roese #size-cells = <0>; 12671f34979SDavid Gibson interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 12771f34979SDavid Gibson /*RXEOB*/ 0x1 &UIC0 0xb 0x4 12871f34979SDavid Gibson /*SERR*/ 0x2 &UIC1 0x0 0x4 12971f34979SDavid Gibson /*TXDE*/ 0x3 &UIC1 0x1 0x4 13071f34979SDavid Gibson /*RXDE*/ 0x4 &UIC1 0x2 0x4>; 13171f34979SDavid Gibson interrupt-map-mask = <0xffffffff>; 132a62f48deSStefan Roese }; 133a62f48deSStefan Roese 134a62f48deSStefan Roese POB0: opb { 135a62f48deSStefan Roese compatible = "ibm,opb-405ex", "ibm,opb"; 136a62f48deSStefan Roese #address-cells = <1>; 137a62f48deSStefan Roese #size-cells = <1>; 13871f34979SDavid Gibson ranges = <0x80000000 0x80000000 0x10000000 13971f34979SDavid Gibson 0xef600000 0xef600000 0x00a00000 14071f34979SDavid Gibson 0xf0000000 0xf0000000 0x10000000>; 14171f34979SDavid Gibson dcr-reg = <0x0a0 0x005>; 142a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 143a62f48deSStefan Roese 144a62f48deSStefan Roese EBC0: ebc { 145a62f48deSStefan Roese compatible = "ibm,ebc-405ex", "ibm,ebc"; 14671f34979SDavid Gibson dcr-reg = <0x012 0x002>; 147a62f48deSStefan Roese #address-cells = <2>; 148a62f48deSStefan Roese #size-cells = <1>; 149a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 150a62f48deSStefan Roese /* ranges property is supplied by U-Boot */ 15171f34979SDavid Gibson interrupts = <0x5 0x1>; 152a62f48deSStefan Roese interrupt-parent = <&UIC1>; 153a62f48deSStefan Roese 154a62f48deSStefan Roese nor_flash@0,0 { 155a62f48deSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 156a62f48deSStefan Roese bank-width = <2>; 15771f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 158a62f48deSStefan Roese #address-cells = <1>; 159a62f48deSStefan Roese #size-cells = <1>; 160a62f48deSStefan Roese partition@0 { 161a62f48deSStefan Roese label = "kernel"; 16213ae564fSStefan Roese reg = <0x00000000 0x001e0000>; 16313ae564fSStefan Roese }; 16413ae564fSStefan Roese partition@1e0000 { 16513ae564fSStefan Roese label = "dtb"; 16613ae564fSStefan Roese reg = <0x001e0000 0x00020000>; 167a62f48deSStefan Roese }; 168a62f48deSStefan Roese partition@200000 { 169a62f48deSStefan Roese label = "root"; 17071f34979SDavid Gibson reg = <0x00200000 0x00200000>; 171a62f48deSStefan Roese }; 172a62f48deSStefan Roese partition@400000 { 173a62f48deSStefan Roese label = "user"; 17471f34979SDavid Gibson reg = <0x00400000 0x03b60000>; 175a62f48deSStefan Roese }; 176a62f48deSStefan Roese partition@3f60000 { 177a62f48deSStefan Roese label = "env"; 17871f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 179a62f48deSStefan Roese }; 180a62f48deSStefan Roese partition@3fa0000 { 181a62f48deSStefan Roese label = "u-boot"; 18271f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 183a62f48deSStefan Roese }; 184a62f48deSStefan Roese }; 18513ae564fSStefan Roese 18613ae564fSStefan Roese ndfc@1,0 { 18713ae564fSStefan Roese compatible = "ibm,ndfc"; 18813ae564fSStefan Roese reg = <0x00000001 0x00000000 0x00002000>; 18913ae564fSStefan Roese ccr = <0x00001000>; 19013ae564fSStefan Roese bank-settings = <0x80002222>; 19113ae564fSStefan Roese #address-cells = <1>; 19213ae564fSStefan Roese #size-cells = <1>; 19313ae564fSStefan Roese 19413ae564fSStefan Roese nand { 19513ae564fSStefan Roese #address-cells = <1>; 19613ae564fSStefan Roese #size-cells = <1>; 19713ae564fSStefan Roese 19813ae564fSStefan Roese partition@0 { 19913ae564fSStefan Roese label = "u-boot"; 20013ae564fSStefan Roese reg = <0x00000000 0x00100000>; 20113ae564fSStefan Roese }; 20213ae564fSStefan Roese partition@100000 { 20313ae564fSStefan Roese label = "user"; 20413ae564fSStefan Roese reg = <0x00000000 0x03f00000>; 20513ae564fSStefan Roese }; 20613ae564fSStefan Roese }; 20713ae564fSStefan Roese }; 208a62f48deSStefan Roese }; 209a62f48deSStefan Roese 210a62f48deSStefan Roese UART0: serial@ef600200 { 211a62f48deSStefan Roese device_type = "serial"; 212a62f48deSStefan Roese compatible = "ns16550"; 21371f34979SDavid Gibson reg = <0xef600200 0x00000008>; 21471f34979SDavid Gibson virtual-reg = <0xef600200>; 215a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 216a62f48deSStefan Roese current-speed = <0>; 217a62f48deSStefan Roese interrupt-parent = <&UIC0>; 21871f34979SDavid Gibson interrupts = <0x1a 0x4>; 219a62f48deSStefan Roese }; 220a62f48deSStefan Roese 221a62f48deSStefan Roese UART1: serial@ef600300 { 222a62f48deSStefan Roese device_type = "serial"; 223a62f48deSStefan Roese compatible = "ns16550"; 22471f34979SDavid Gibson reg = <0xef600300 0x00000008>; 22571f34979SDavid Gibson virtual-reg = <0xef600300>; 226a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 227a62f48deSStefan Roese current-speed = <0>; 228a62f48deSStefan Roese interrupt-parent = <&UIC0>; 22971f34979SDavid Gibson interrupts = <0x1 0x4>; 230a62f48deSStefan Roese }; 231a62f48deSStefan Roese 232a62f48deSStefan Roese IIC0: i2c@ef600400 { 233a62f48deSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 23471f34979SDavid Gibson reg = <0xef600400 0x00000014>; 235a62f48deSStefan Roese interrupt-parent = <&UIC0>; 23671f34979SDavid Gibson interrupts = <0x2 0x4>; 23713ae564fSStefan Roese #address-cells = <1>; 23813ae564fSStefan Roese #size-cells = <0>; 23913ae564fSStefan Roese 24013ae564fSStefan Roese rtc@68 { 24113ae564fSStefan Roese compatible = "dallas,ds1338"; 24213ae564fSStefan Roese reg = <0x68>; 24313ae564fSStefan Roese }; 24413ae564fSStefan Roese 24513ae564fSStefan Roese dtt@48 { 24613ae564fSStefan Roese compatible = "dallas,ds1775"; 24713ae564fSStefan Roese reg = <0x48>; 24813ae564fSStefan Roese }; 249a62f48deSStefan Roese }; 250a62f48deSStefan Roese 251a62f48deSStefan Roese IIC1: i2c@ef600500 { 252a62f48deSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 25371f34979SDavid Gibson reg = <0xef600500 0x00000014>; 254a62f48deSStefan Roese interrupt-parent = <&UIC0>; 25571f34979SDavid Gibson interrupts = <0x7 0x4>; 256a62f48deSStefan Roese }; 257a62f48deSStefan Roese 258a62f48deSStefan Roese RGMII0: emac-rgmii@ef600b00 { 259a62f48deSStefan Roese compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 26071f34979SDavid Gibson reg = <0xef600b00 0x00000104>; 2610a6ea8beSStefan Roese has-mdio; 262a62f48deSStefan Roese }; 263a62f48deSStefan Roese 264a62f48deSStefan Roese EMAC0: ethernet@ef600900 { 26571f34979SDavid Gibson linux,network-index = <0x0>; 266a62f48deSStefan Roese device_type = "network"; 26705781ccdSGrant Erickson compatible = "ibm,emac-405ex", "ibm,emac4sync"; 268a62f48deSStefan Roese interrupt-parent = <&EMAC0>; 26971f34979SDavid Gibson interrupts = <0x0 0x1>; 270a62f48deSStefan Roese #interrupt-cells = <1>; 271a62f48deSStefan Roese #address-cells = <0>; 272a62f48deSStefan Roese #size-cells = <0>; 27371f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 27471f34979SDavid Gibson /*Wake*/ 0x1 &UIC1 0x1d 0x4>; 27505781ccdSGrant Erickson reg = <0xef600900 0x000000c4>; 276a62f48deSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 277a62f48deSStefan Roese mal-device = <&MAL0>; 278a62f48deSStefan Roese mal-tx-channel = <0>; 279a62f48deSStefan Roese mal-rx-channel = <0>; 280a62f48deSStefan Roese cell-index = <0>; 28171f34979SDavid Gibson max-frame-size = <9000>; 28271f34979SDavid Gibson rx-fifo-size = <4096>; 28371f34979SDavid Gibson tx-fifo-size = <2048>; 284835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 285835ad8e7SDave Mitchell tx-fifo-size-gige = <16384>; 286a62f48deSStefan Roese phy-mode = "rgmii"; 28771f34979SDavid Gibson phy-map = <0x00000000>; 288a62f48deSStefan Roese rgmii-device = <&RGMII0>; 289a62f48deSStefan Roese rgmii-channel = <0>; 2900a6ea8beSStefan Roese has-inverted-stacr-oc; 2910a6ea8beSStefan Roese has-new-stacr-staopc; 292a62f48deSStefan Roese }; 293a62f48deSStefan Roese 294a62f48deSStefan Roese EMAC1: ethernet@ef600a00 { 29571f34979SDavid Gibson linux,network-index = <0x1>; 296a62f48deSStefan Roese device_type = "network"; 29705781ccdSGrant Erickson compatible = "ibm,emac-405ex", "ibm,emac4sync"; 298a62f48deSStefan Roese interrupt-parent = <&EMAC1>; 29971f34979SDavid Gibson interrupts = <0x0 0x1>; 300a62f48deSStefan Roese #interrupt-cells = <1>; 301a62f48deSStefan Roese #address-cells = <0>; 302a62f48deSStefan Roese #size-cells = <0>; 30371f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4 30471f34979SDavid Gibson /*Wake*/ 0x1 &UIC1 0x1f 0x4>; 30505781ccdSGrant Erickson reg = <0xef600a00 0x000000c4>; 306a62f48deSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 307a62f48deSStefan Roese mal-device = <&MAL0>; 308a62f48deSStefan Roese mal-tx-channel = <1>; 309a62f48deSStefan Roese mal-rx-channel = <1>; 310a62f48deSStefan Roese cell-index = <1>; 31171f34979SDavid Gibson max-frame-size = <9000>; 31271f34979SDavid Gibson rx-fifo-size = <4096>; 31371f34979SDavid Gibson tx-fifo-size = <2048>; 314835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 315835ad8e7SDave Mitchell tx-fifo-size-gige = <16384>; 316a62f48deSStefan Roese phy-mode = "rgmii"; 31771f34979SDavid Gibson phy-map = <0x00000000>; 318a62f48deSStefan Roese rgmii-device = <&RGMII0>; 319a62f48deSStefan Roese rgmii-channel = <1>; 3200a6ea8beSStefan Roese has-inverted-stacr-oc; 3210a6ea8beSStefan Roese has-new-stacr-staopc; 322a62f48deSStefan Roese }; 323a62f48deSStefan Roese }; 324151161c6SStefan Roese 325151161c6SStefan Roese PCIE0: pciex@0a0000000 { 326151161c6SStefan Roese device_type = "pci"; 327151161c6SStefan Roese #interrupt-cells = <1>; 328151161c6SStefan Roese #size-cells = <2>; 329151161c6SStefan Roese #address-cells = <3>; 330151161c6SStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 331151161c6SStefan Roese primary; 33271f34979SDavid Gibson port = <0x0>; /* port number */ 33371f34979SDavid Gibson reg = <0xa0000000 0x20000000 /* Config space access */ 33471f34979SDavid Gibson 0xef000000 0x00001000>; /* Registers */ 33571f34979SDavid Gibson dcr-reg = <0x040 0x020>; 33671f34979SDavid Gibson sdr-base = <0x400>; 337151161c6SStefan Roese 338151161c6SStefan Roese /* Outbound ranges, one memory and one IO, 339151161c6SStefan Roese * later cannot be changed 340151161c6SStefan Roese */ 34171f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 34271f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; 343151161c6SStefan Roese 344151161c6SStefan Roese /* Inbound 2GB range starting at 0 */ 34571f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 346151161c6SStefan Roese 347dc88416bSStefan Roese /* This drives busses 0x00 to 0x3f */ 34871f34979SDavid Gibson bus-range = <0x0 0x3f>; 349151161c6SStefan Roese 350151161c6SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 351151161c6SStefan Roese * to invert PCIe legacy interrupts). 352151161c6SStefan Roese * We are de-swizzling here because the numbers are actually for 353151161c6SStefan Roese * port of the root complex virtual P2P bridge. But I want 354151161c6SStefan Roese * to avoid putting a node for it in the tree, so the numbers 355151161c6SStefan Roese * below are basically de-swizzled numbers. 356151161c6SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 357151161c6SStefan Roese */ 35871f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 359151161c6SStefan Roese interrupt-map = < 36071f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ 36171f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ 36271f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ 36371f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; 364151161c6SStefan Roese }; 365151161c6SStefan Roese 366151161c6SStefan Roese PCIE1: pciex@0c0000000 { 367151161c6SStefan Roese device_type = "pci"; 368151161c6SStefan Roese #interrupt-cells = <1>; 369151161c6SStefan Roese #size-cells = <2>; 370151161c6SStefan Roese #address-cells = <3>; 371151161c6SStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 372151161c6SStefan Roese primary; 37371f34979SDavid Gibson port = <0x1>; /* port number */ 37471f34979SDavid Gibson reg = <0xc0000000 0x20000000 /* Config space access */ 37571f34979SDavid Gibson 0xef001000 0x00001000>; /* Registers */ 37671f34979SDavid Gibson dcr-reg = <0x060 0x020>; 37771f34979SDavid Gibson sdr-base = <0x440>; 378151161c6SStefan Roese 379151161c6SStefan Roese /* Outbound ranges, one memory and one IO, 380151161c6SStefan Roese * later cannot be changed 381151161c6SStefan Roese */ 38271f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 38371f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; 384151161c6SStefan Roese 385151161c6SStefan Roese /* Inbound 2GB range starting at 0 */ 38671f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 387151161c6SStefan Roese 388dc88416bSStefan Roese /* This drives busses 0x40 to 0x7f */ 38971f34979SDavid Gibson bus-range = <0x40 0x7f>; 390151161c6SStefan Roese 391151161c6SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 392151161c6SStefan Roese * to invert PCIe legacy interrupts). 393151161c6SStefan Roese * We are de-swizzling here because the numbers are actually for 394151161c6SStefan Roese * port of the root complex virtual P2P bridge. But I want 395151161c6SStefan Roese * to avoid putting a node for it in the tree, so the numbers 396151161c6SStefan Roese * below are basically de-swizzled numbers. 397151161c6SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 398151161c6SStefan Roese */ 39971f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 400151161c6SStefan Roese interrupt-map = < 40171f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ 40271f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ 40371f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ 40471f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; 405151161c6SStefan Roese }; 406a62f48deSStefan Roese }; 407a62f48deSStefan Roese}; 408