1a62f48deSStefan Roese/* 2a62f48deSStefan Roese * Device Tree Source for AMCC Kilauea (405EX) 3a62f48deSStefan Roese * 4a62f48deSStefan Roese * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> 5a62f48deSStefan Roese * 6a62f48deSStefan Roese * This file is licensed under the terms of the GNU General Public 7a62f48deSStefan Roese * License version 2. This program is licensed "as is" without 8a62f48deSStefan Roese * any warranty of any kind, whether express or implied. 9a62f48deSStefan Roese */ 10a62f48deSStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 13a62f48deSStefan Roese/ { 14a62f48deSStefan Roese #address-cells = <1>; 15a62f48deSStefan Roese #size-cells = <1>; 16a62f48deSStefan Roese model = "amcc,kilauea"; 17a62f48deSStefan Roese compatible = "amcc,kilauea"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 19a62f48deSStefan Roese 208aaed98cSStefan Roese aliases { 218aaed98cSStefan Roese ethernet0 = &EMAC0; 228aaed98cSStefan Roese ethernet1 = &EMAC1; 238aaed98cSStefan Roese serial0 = &UART0; 248aaed98cSStefan Roese serial1 = &UART1; 258aaed98cSStefan Roese }; 268aaed98cSStefan Roese 27a62f48deSStefan Roese cpus { 28a62f48deSStefan Roese #address-cells = <1>; 29a62f48deSStefan Roese #size-cells = <0>; 30a62f48deSStefan Roese 3172fda114SJosh Boyer cpu@0 { 32a62f48deSStefan Roese device_type = "cpu"; 3372fda114SJosh Boyer model = "PowerPC,405EX"; 3471f34979SDavid Gibson reg = <0x00000000>; 35a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 36a62f48deSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3771f34979SDavid Gibson i-cache-line-size = <32>; 3871f34979SDavid Gibson d-cache-line-size = <32>; 3971f34979SDavid Gibson i-cache-size = <16384>; /* 16 kB */ 4071f34979SDavid Gibson d-cache-size = <16384>; /* 16 kB */ 41a62f48deSStefan Roese dcr-controller; 42a62f48deSStefan Roese dcr-access-method = "native"; 43a62f48deSStefan Roese }; 44a62f48deSStefan Roese }; 45a62f48deSStefan Roese 46a62f48deSStefan Roese memory { 47a62f48deSStefan Roese device_type = "memory"; 4871f34979SDavid Gibson reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ 49a62f48deSStefan Roese }; 50a62f48deSStefan Roese 51a62f48deSStefan Roese UIC0: interrupt-controller { 52a62f48deSStefan Roese compatible = "ibm,uic-405ex", "ibm,uic"; 53a62f48deSStefan Roese interrupt-controller; 54a62f48deSStefan Roese cell-index = <0>; 5571f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 56a62f48deSStefan Roese #address-cells = <0>; 57a62f48deSStefan Roese #size-cells = <0>; 58a62f48deSStefan Roese #interrupt-cells = <2>; 59a62f48deSStefan Roese }; 60a62f48deSStefan Roese 61a62f48deSStefan Roese UIC1: interrupt-controller1 { 62a62f48deSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 63a62f48deSStefan Roese interrupt-controller; 64a62f48deSStefan Roese cell-index = <1>; 6571f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 66a62f48deSStefan Roese #address-cells = <0>; 67a62f48deSStefan Roese #size-cells = <0>; 68a62f48deSStefan Roese #interrupt-cells = <2>; 6971f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 70a62f48deSStefan Roese interrupt-parent = <&UIC0>; 71a62f48deSStefan Roese }; 72a62f48deSStefan Roese 73a62f48deSStefan Roese UIC2: interrupt-controller2 { 74a62f48deSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 75a62f48deSStefan Roese interrupt-controller; 76a62f48deSStefan Roese cell-index = <2>; 7771f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 78a62f48deSStefan Roese #address-cells = <0>; 79a62f48deSStefan Roese #size-cells = <0>; 80a62f48deSStefan Roese #interrupt-cells = <2>; 8171f34979SDavid Gibson interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ 82a62f48deSStefan Roese interrupt-parent = <&UIC0>; 83a62f48deSStefan Roese }; 84a62f48deSStefan Roese 85a62f48deSStefan Roese plb { 86a62f48deSStefan Roese compatible = "ibm,plb-405ex", "ibm,plb4"; 87a62f48deSStefan Roese #address-cells = <1>; 88a62f48deSStefan Roese #size-cells = <1>; 89a62f48deSStefan Roese ranges; 90a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 91a62f48deSStefan Roese 92a62f48deSStefan Roese SDRAM0: memory-controller { 93a62f48deSStefan Roese compatible = "ibm,sdram-405ex"; 9471f34979SDavid Gibson dcr-reg = <0x010 0x002>; 95a62f48deSStefan Roese }; 96a62f48deSStefan Roese 97a62f48deSStefan Roese MAL0: mcmal { 98a62f48deSStefan Roese compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 9971f34979SDavid Gibson dcr-reg = <0x180 0x062>; 100a62f48deSStefan Roese num-tx-chans = <2>; 101a62f48deSStefan Roese num-rx-chans = <2>; 102a62f48deSStefan Roese interrupt-parent = <&MAL0>; 10371f34979SDavid Gibson interrupts = <0x0 0x1 0x2 0x3 0x4>; 104a62f48deSStefan Roese #interrupt-cells = <1>; 105a62f48deSStefan Roese #address-cells = <0>; 106a62f48deSStefan Roese #size-cells = <0>; 10771f34979SDavid Gibson interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 10871f34979SDavid Gibson /*RXEOB*/ 0x1 &UIC0 0xb 0x4 10971f34979SDavid Gibson /*SERR*/ 0x2 &UIC1 0x0 0x4 11071f34979SDavid Gibson /*TXDE*/ 0x3 &UIC1 0x1 0x4 11171f34979SDavid Gibson /*RXDE*/ 0x4 &UIC1 0x2 0x4>; 11271f34979SDavid Gibson interrupt-map-mask = <0xffffffff>; 113a62f48deSStefan Roese }; 114a62f48deSStefan Roese 115a62f48deSStefan Roese POB0: opb { 116a62f48deSStefan Roese compatible = "ibm,opb-405ex", "ibm,opb"; 117a62f48deSStefan Roese #address-cells = <1>; 118a62f48deSStefan Roese #size-cells = <1>; 11971f34979SDavid Gibson ranges = <0x80000000 0x80000000 0x10000000 12071f34979SDavid Gibson 0xef600000 0xef600000 0x00a00000 12171f34979SDavid Gibson 0xf0000000 0xf0000000 0x10000000>; 12271f34979SDavid Gibson dcr-reg = <0x0a0 0x005>; 123a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 124a62f48deSStefan Roese 125a62f48deSStefan Roese EBC0: ebc { 126a62f48deSStefan Roese compatible = "ibm,ebc-405ex", "ibm,ebc"; 12771f34979SDavid Gibson dcr-reg = <0x012 0x002>; 128a62f48deSStefan Roese #address-cells = <2>; 129a62f48deSStefan Roese #size-cells = <1>; 130a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 131a62f48deSStefan Roese /* ranges property is supplied by U-Boot */ 13271f34979SDavid Gibson interrupts = <0x5 0x1>; 133a62f48deSStefan Roese interrupt-parent = <&UIC1>; 134a62f48deSStefan Roese 135a62f48deSStefan Roese nor_flash@0,0 { 136a62f48deSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 137a62f48deSStefan Roese bank-width = <2>; 13871f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 139a62f48deSStefan Roese #address-cells = <1>; 140a62f48deSStefan Roese #size-cells = <1>; 141a62f48deSStefan Roese partition@0 { 142a62f48deSStefan Roese label = "kernel"; 14371f34979SDavid Gibson reg = <0x00000000 0x00200000>; 144a62f48deSStefan Roese }; 145a62f48deSStefan Roese partition@200000 { 146a62f48deSStefan Roese label = "root"; 14771f34979SDavid Gibson reg = <0x00200000 0x00200000>; 148a62f48deSStefan Roese }; 149a62f48deSStefan Roese partition@400000 { 150a62f48deSStefan Roese label = "user"; 15171f34979SDavid Gibson reg = <0x00400000 0x03b60000>; 152a62f48deSStefan Roese }; 153a62f48deSStefan Roese partition@3f60000 { 154a62f48deSStefan Roese label = "env"; 15571f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 156a62f48deSStefan Roese }; 157a62f48deSStefan Roese partition@3fa0000 { 158a62f48deSStefan Roese label = "u-boot"; 15971f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 160a62f48deSStefan Roese }; 161a62f48deSStefan Roese }; 162a62f48deSStefan Roese }; 163a62f48deSStefan Roese 164a62f48deSStefan Roese UART0: serial@ef600200 { 165a62f48deSStefan Roese device_type = "serial"; 166a62f48deSStefan Roese compatible = "ns16550"; 16771f34979SDavid Gibson reg = <0xef600200 0x00000008>; 16871f34979SDavid Gibson virtual-reg = <0xef600200>; 169a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 170a62f48deSStefan Roese current-speed = <0>; 171a62f48deSStefan Roese interrupt-parent = <&UIC0>; 17271f34979SDavid Gibson interrupts = <0x1a 0x4>; 173a62f48deSStefan Roese }; 174a62f48deSStefan Roese 175a62f48deSStefan Roese UART1: serial@ef600300 { 176a62f48deSStefan Roese device_type = "serial"; 177a62f48deSStefan Roese compatible = "ns16550"; 17871f34979SDavid Gibson reg = <0xef600300 0x00000008>; 17971f34979SDavid Gibson virtual-reg = <0xef600300>; 180a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 181a62f48deSStefan Roese current-speed = <0>; 182a62f48deSStefan Roese interrupt-parent = <&UIC0>; 18371f34979SDavid Gibson interrupts = <0x1 0x4>; 184a62f48deSStefan Roese }; 185a62f48deSStefan Roese 186a62f48deSStefan Roese IIC0: i2c@ef600400 { 187a62f48deSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 18871f34979SDavid Gibson reg = <0xef600400 0x00000014>; 189a62f48deSStefan Roese interrupt-parent = <&UIC0>; 19071f34979SDavid Gibson interrupts = <0x2 0x4>; 191a62f48deSStefan Roese }; 192a62f48deSStefan Roese 193a62f48deSStefan Roese IIC1: i2c@ef600500 { 194a62f48deSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 19571f34979SDavid Gibson reg = <0xef600500 0x00000014>; 196a62f48deSStefan Roese interrupt-parent = <&UIC0>; 19771f34979SDavid Gibson interrupts = <0x7 0x4>; 198a62f48deSStefan Roese }; 199a62f48deSStefan Roese 200a62f48deSStefan Roese 201a62f48deSStefan Roese RGMII0: emac-rgmii@ef600b00 { 202a62f48deSStefan Roese compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 20371f34979SDavid Gibson reg = <0xef600b00 0x00000104>; 2040a6ea8beSStefan Roese has-mdio; 205a62f48deSStefan Roese }; 206a62f48deSStefan Roese 207a62f48deSStefan Roese EMAC0: ethernet@ef600900 { 20871f34979SDavid Gibson linux,network-index = <0x0>; 209a62f48deSStefan Roese device_type = "network"; 21005781ccdSGrant Erickson compatible = "ibm,emac-405ex", "ibm,emac4sync"; 211a62f48deSStefan Roese interrupt-parent = <&EMAC0>; 21271f34979SDavid Gibson interrupts = <0x0 0x1>; 213a62f48deSStefan Roese #interrupt-cells = <1>; 214a62f48deSStefan Roese #address-cells = <0>; 215a62f48deSStefan Roese #size-cells = <0>; 21671f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 21771f34979SDavid Gibson /*Wake*/ 0x1 &UIC1 0x1d 0x4>; 21805781ccdSGrant Erickson reg = <0xef600900 0x000000c4>; 219a62f48deSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 220a62f48deSStefan Roese mal-device = <&MAL0>; 221a62f48deSStefan Roese mal-tx-channel = <0>; 222a62f48deSStefan Roese mal-rx-channel = <0>; 223a62f48deSStefan Roese cell-index = <0>; 22471f34979SDavid Gibson max-frame-size = <9000>; 22571f34979SDavid Gibson rx-fifo-size = <4096>; 22671f34979SDavid Gibson tx-fifo-size = <2048>; 227a62f48deSStefan Roese phy-mode = "rgmii"; 22871f34979SDavid Gibson phy-map = <0x00000000>; 229a62f48deSStefan Roese rgmii-device = <&RGMII0>; 230a62f48deSStefan Roese rgmii-channel = <0>; 2310a6ea8beSStefan Roese has-inverted-stacr-oc; 2320a6ea8beSStefan Roese has-new-stacr-staopc; 233a62f48deSStefan Roese }; 234a62f48deSStefan Roese 235a62f48deSStefan Roese EMAC1: ethernet@ef600a00 { 23671f34979SDavid Gibson linux,network-index = <0x1>; 237a62f48deSStefan Roese device_type = "network"; 23805781ccdSGrant Erickson compatible = "ibm,emac-405ex", "ibm,emac4sync"; 239a62f48deSStefan Roese interrupt-parent = <&EMAC1>; 24071f34979SDavid Gibson interrupts = <0x0 0x1>; 241a62f48deSStefan Roese #interrupt-cells = <1>; 242a62f48deSStefan Roese #address-cells = <0>; 243a62f48deSStefan Roese #size-cells = <0>; 24471f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4 24571f34979SDavid Gibson /*Wake*/ 0x1 &UIC1 0x1f 0x4>; 24605781ccdSGrant Erickson reg = <0xef600a00 0x000000c4>; 247a62f48deSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 248a62f48deSStefan Roese mal-device = <&MAL0>; 249a62f48deSStefan Roese mal-tx-channel = <1>; 250a62f48deSStefan Roese mal-rx-channel = <1>; 251a62f48deSStefan Roese cell-index = <1>; 25271f34979SDavid Gibson max-frame-size = <9000>; 25371f34979SDavid Gibson rx-fifo-size = <4096>; 25471f34979SDavid Gibson tx-fifo-size = <2048>; 255a62f48deSStefan Roese phy-mode = "rgmii"; 25671f34979SDavid Gibson phy-map = <0x00000000>; 257a62f48deSStefan Roese rgmii-device = <&RGMII0>; 258a62f48deSStefan Roese rgmii-channel = <1>; 2590a6ea8beSStefan Roese has-inverted-stacr-oc; 2600a6ea8beSStefan Roese has-new-stacr-staopc; 261a62f48deSStefan Roese }; 262a62f48deSStefan Roese }; 263151161c6SStefan Roese 264151161c6SStefan Roese PCIE0: pciex@0a0000000 { 265151161c6SStefan Roese device_type = "pci"; 266151161c6SStefan Roese #interrupt-cells = <1>; 267151161c6SStefan Roese #size-cells = <2>; 268151161c6SStefan Roese #address-cells = <3>; 269151161c6SStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 270151161c6SStefan Roese primary; 27171f34979SDavid Gibson port = <0x0>; /* port number */ 27271f34979SDavid Gibson reg = <0xa0000000 0x20000000 /* Config space access */ 27371f34979SDavid Gibson 0xef000000 0x00001000>; /* Registers */ 27471f34979SDavid Gibson dcr-reg = <0x040 0x020>; 27571f34979SDavid Gibson sdr-base = <0x400>; 276151161c6SStefan Roese 277151161c6SStefan Roese /* Outbound ranges, one memory and one IO, 278151161c6SStefan Roese * later cannot be changed 279151161c6SStefan Roese */ 28071f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 28171f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; 282151161c6SStefan Roese 283151161c6SStefan Roese /* Inbound 2GB range starting at 0 */ 28471f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 285151161c6SStefan Roese 286dc88416bSStefan Roese /* This drives busses 0x00 to 0x3f */ 28771f34979SDavid Gibson bus-range = <0x0 0x3f>; 288151161c6SStefan Roese 289151161c6SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 290151161c6SStefan Roese * to invert PCIe legacy interrupts). 291151161c6SStefan Roese * We are de-swizzling here because the numbers are actually for 292151161c6SStefan Roese * port of the root complex virtual P2P bridge. But I want 293151161c6SStefan Roese * to avoid putting a node for it in the tree, so the numbers 294151161c6SStefan Roese * below are basically de-swizzled numbers. 295151161c6SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 296151161c6SStefan Roese */ 29771f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 298151161c6SStefan Roese interrupt-map = < 29971f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ 30071f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ 30171f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ 30271f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; 303151161c6SStefan Roese }; 304151161c6SStefan Roese 305151161c6SStefan Roese PCIE1: pciex@0c0000000 { 306151161c6SStefan Roese device_type = "pci"; 307151161c6SStefan Roese #interrupt-cells = <1>; 308151161c6SStefan Roese #size-cells = <2>; 309151161c6SStefan Roese #address-cells = <3>; 310151161c6SStefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 311151161c6SStefan Roese primary; 31271f34979SDavid Gibson port = <0x1>; /* port number */ 31371f34979SDavid Gibson reg = <0xc0000000 0x20000000 /* Config space access */ 31471f34979SDavid Gibson 0xef001000 0x00001000>; /* Registers */ 31571f34979SDavid Gibson dcr-reg = <0x060 0x020>; 31671f34979SDavid Gibson sdr-base = <0x440>; 317151161c6SStefan Roese 318151161c6SStefan Roese /* Outbound ranges, one memory and one IO, 319151161c6SStefan Roese * later cannot be changed 320151161c6SStefan Roese */ 32171f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 32271f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; 323151161c6SStefan Roese 324151161c6SStefan Roese /* Inbound 2GB range starting at 0 */ 32571f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 326151161c6SStefan Roese 327dc88416bSStefan Roese /* This drives busses 0x40 to 0x7f */ 32871f34979SDavid Gibson bus-range = <0x40 0x7f>; 329151161c6SStefan Roese 330151161c6SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 331151161c6SStefan Roese * to invert PCIe legacy interrupts). 332151161c6SStefan Roese * We are de-swizzling here because the numbers are actually for 333151161c6SStefan Roese * port of the root complex virtual P2P bridge. But I want 334151161c6SStefan Roese * to avoid putting a node for it in the tree, so the numbers 335151161c6SStefan Roese * below are basically de-swizzled numbers. 336151161c6SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 337151161c6SStefan Roese */ 33871f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 339151161c6SStefan Roese interrupt-map = < 34071f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ 34171f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ 34271f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ 34371f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; 344151161c6SStefan Roese }; 345a62f48deSStefan Roese }; 346a62f48deSStefan Roese}; 347