1a89eda26SStefan Roese/* 2a89eda26SStefan Roese * Device Tree Source for Mosaix Technologies, Inc. ICON board 3a89eda26SStefan Roese * 4a89eda26SStefan Roese * Copyright 2010 DENX Software Engineering, Stefan Roese <sr@denx.de> 5a89eda26SStefan Roese * 6a89eda26SStefan Roese * This file is licensed under the terms of the GNU General Public 7a89eda26SStefan Roese * License version 2. This program is licensed "as is" without 8a89eda26SStefan Roese * any warranty of any kind, whether express or implied. 9a89eda26SStefan Roese */ 10a89eda26SStefan Roese 11a89eda26SStefan Roese/dts-v1/; 12a89eda26SStefan Roese 13a89eda26SStefan Roese/ { 14a89eda26SStefan Roese #address-cells = <2>; 15a89eda26SStefan Roese #size-cells = <2>; 16a89eda26SStefan Roese model = "mosaixtech,icon"; 17a89eda26SStefan Roese compatible = "mosaixtech,icon"; 18a89eda26SStefan Roese dcr-parent = <&{/cpus/cpu@0}>; 19a89eda26SStefan Roese 20a89eda26SStefan Roese aliases { 21a89eda26SStefan Roese ethernet0 = &EMAC0; 22a89eda26SStefan Roese serial0 = &UART0; 23a89eda26SStefan Roese serial1 = &UART1; 24a89eda26SStefan Roese serial2 = &UART2; 25a89eda26SStefan Roese }; 26a89eda26SStefan Roese 27a89eda26SStefan Roese cpus { 28a89eda26SStefan Roese #address-cells = <1>; 29a89eda26SStefan Roese #size-cells = <0>; 30a89eda26SStefan Roese 31a89eda26SStefan Roese cpu@0 { 32a89eda26SStefan Roese device_type = "cpu"; 33a89eda26SStefan Roese model = "PowerPC,440SPe"; 34a89eda26SStefan Roese reg = <0x00000000>; 35a89eda26SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 36a89eda26SStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 37a89eda26SStefan Roese i-cache-line-size = <32>; 38a89eda26SStefan Roese d-cache-line-size = <32>; 39a89eda26SStefan Roese i-cache-size = <32768>; 40a89eda26SStefan Roese d-cache-size = <32768>; 41a89eda26SStefan Roese dcr-controller; 42a89eda26SStefan Roese dcr-access-method = "native"; 43a89eda26SStefan Roese reset-type = <2>; /* Use chip-reset */ 44a89eda26SStefan Roese }; 45a89eda26SStefan Roese }; 46a89eda26SStefan Roese 47a89eda26SStefan Roese memory { 48a89eda26SStefan Roese device_type = "memory"; 49a89eda26SStefan Roese reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */ 50a89eda26SStefan Roese }; 51a89eda26SStefan Roese 52a89eda26SStefan Roese UIC0: interrupt-controller0 { 53a89eda26SStefan Roese compatible = "ibm,uic-440spe","ibm,uic"; 54a89eda26SStefan Roese interrupt-controller; 55a89eda26SStefan Roese cell-index = <0>; 56a89eda26SStefan Roese dcr-reg = <0x0c0 0x009>; 57a89eda26SStefan Roese #address-cells = <0>; 58a89eda26SStefan Roese #size-cells = <0>; 59a89eda26SStefan Roese #interrupt-cells = <2>; 60a89eda26SStefan Roese }; 61a89eda26SStefan Roese 62a89eda26SStefan Roese UIC1: interrupt-controller1 { 63a89eda26SStefan Roese compatible = "ibm,uic-440spe","ibm,uic"; 64a89eda26SStefan Roese interrupt-controller; 65a89eda26SStefan Roese cell-index = <1>; 66a89eda26SStefan Roese dcr-reg = <0x0d0 0x009>; 67a89eda26SStefan Roese #address-cells = <0>; 68a89eda26SStefan Roese #size-cells = <0>; 69a89eda26SStefan Roese #interrupt-cells = <2>; 70a89eda26SStefan Roese interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 71a89eda26SStefan Roese interrupt-parent = <&UIC0>; 72a89eda26SStefan Roese }; 73a89eda26SStefan Roese 74a89eda26SStefan Roese UIC2: interrupt-controller2 { 75a89eda26SStefan Roese compatible = "ibm,uic-440spe","ibm,uic"; 76a89eda26SStefan Roese interrupt-controller; 77a89eda26SStefan Roese cell-index = <2>; 78a89eda26SStefan Roese dcr-reg = <0x0e0 0x009>; 79a89eda26SStefan Roese #address-cells = <0>; 80a89eda26SStefan Roese #size-cells = <0>; 81a89eda26SStefan Roese #interrupt-cells = <2>; 82a89eda26SStefan Roese interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 83a89eda26SStefan Roese interrupt-parent = <&UIC0>; 84a89eda26SStefan Roese }; 85a89eda26SStefan Roese 86a89eda26SStefan Roese UIC3: interrupt-controller3 { 87a89eda26SStefan Roese compatible = "ibm,uic-440spe","ibm,uic"; 88a89eda26SStefan Roese interrupt-controller; 89a89eda26SStefan Roese cell-index = <3>; 90a89eda26SStefan Roese dcr-reg = <0x0f0 0x009>; 91a89eda26SStefan Roese #address-cells = <0>; 92a89eda26SStefan Roese #size-cells = <0>; 93a89eda26SStefan Roese #interrupt-cells = <2>; 94a89eda26SStefan Roese interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 95a89eda26SStefan Roese interrupt-parent = <&UIC0>; 96a89eda26SStefan Roese }; 97a89eda26SStefan Roese 98a89eda26SStefan Roese SDR0: sdr { 99a89eda26SStefan Roese compatible = "ibm,sdr-440spe"; 100a89eda26SStefan Roese dcr-reg = <0x00e 0x002>; 101a89eda26SStefan Roese }; 102a89eda26SStefan Roese 103a89eda26SStefan Roese CPR0: cpr { 104a89eda26SStefan Roese compatible = "ibm,cpr-440spe"; 105a89eda26SStefan Roese dcr-reg = <0x00c 0x002>; 106a89eda26SStefan Roese }; 107a89eda26SStefan Roese 108a89eda26SStefan Roese MQ0: mq { 109a89eda26SStefan Roese compatible = "ibm,mq-440spe"; 110a89eda26SStefan Roese dcr-reg = <0x040 0x020>; 111a89eda26SStefan Roese }; 112a89eda26SStefan Roese 113a89eda26SStefan Roese plb { 114a89eda26SStefan Roese compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4"; 115a89eda26SStefan Roese #address-cells = <2>; 116a89eda26SStefan Roese #size-cells = <1>; 117a89eda26SStefan Roese /* addr-child addr-parent size */ 118a89eda26SStefan Roese ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000 119a89eda26SStefan Roese 0x4 0x00200000 0x4 0x00200000 0x00000400 120a89eda26SStefan Roese 0x4 0xe0000000 0x4 0xe0000000 0x20000000 121a89eda26SStefan Roese 0xc 0x00000000 0xc 0x00000000 0x20000000 122a89eda26SStefan Roese 0xd 0x00000000 0xd 0x00000000 0x80000000 123a89eda26SStefan Roese 0xd 0x80000000 0xd 0x80000000 0x80000000 124a89eda26SStefan Roese 0xe 0x00000000 0xe 0x00000000 0x80000000 125a89eda26SStefan Roese 0xe 0x80000000 0xe 0x80000000 0x80000000 126a89eda26SStefan Roese 0xf 0x00000000 0xf 0x00000000 0x80000000 127a89eda26SStefan Roese 0xf 0x80000000 0xf 0x80000000 0x80000000>; 128a89eda26SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 129a89eda26SStefan Roese 130a89eda26SStefan Roese SDRAM0: sdram { 131a89eda26SStefan Roese compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; 132a89eda26SStefan Roese dcr-reg = <0x010 0x002>; 133a89eda26SStefan Roese }; 134a89eda26SStefan Roese 135a89eda26SStefan Roese MAL0: mcmal { 136a89eda26SStefan Roese compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; 137a89eda26SStefan Roese dcr-reg = <0x180 0x062>; 138a89eda26SStefan Roese num-tx-chans = <2>; 139a89eda26SStefan Roese num-rx-chans = <1>; 140a89eda26SStefan Roese interrupt-parent = <&MAL0>; 141a89eda26SStefan Roese interrupts = <0x0 0x1 0x2 0x3 0x4>; 142a89eda26SStefan Roese #interrupt-cells = <1>; 143a89eda26SStefan Roese #address-cells = <0>; 144a89eda26SStefan Roese #size-cells = <0>; 145a89eda26SStefan Roese interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4 146a89eda26SStefan Roese /*RXEOB*/ 0x1 &UIC1 0x7 0x4 147a89eda26SStefan Roese /*SERR*/ 0x2 &UIC1 0x1 0x4 148a89eda26SStefan Roese /*TXDE*/ 0x3 &UIC1 0x2 0x4 149a89eda26SStefan Roese /*RXDE*/ 0x4 &UIC1 0x3 0x4>; 150a89eda26SStefan Roese }; 151a89eda26SStefan Roese 152a89eda26SStefan Roese POB0: opb { 153a89eda26SStefan Roese compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; 154a89eda26SStefan Roese #address-cells = <1>; 155a89eda26SStefan Roese #size-cells = <1>; 156a89eda26SStefan Roese ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>; 157a89eda26SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 158a89eda26SStefan Roese 159a89eda26SStefan Roese EBC0: ebc { 160a89eda26SStefan Roese compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; 161a89eda26SStefan Roese dcr-reg = <0x012 0x002>; 162a89eda26SStefan Roese #address-cells = <2>; 163a89eda26SStefan Roese #size-cells = <1>; 164a89eda26SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 165a89eda26SStefan Roese /* ranges property is supplied by U-Boot */ 166a89eda26SStefan Roese interrupts = <0x5 0x1>; 167a89eda26SStefan Roese interrupt-parent = <&UIC1>; 168a89eda26SStefan Roese 169a89eda26SStefan Roese nor_flash@0,0 { 170a89eda26SStefan Roese compatible = "cfi-flash"; 171a89eda26SStefan Roese bank-width = <2>; 172a89eda26SStefan Roese reg = <0x00000000 0x00000000 0x01000000>; 173a89eda26SStefan Roese #address-cells = <1>; 174a89eda26SStefan Roese #size-cells = <1>; 175a89eda26SStefan Roese partition@0 { 176a89eda26SStefan Roese label = "kernel"; 177a89eda26SStefan Roese reg = <0x00000000 0x001e0000>; 178a89eda26SStefan Roese }; 179a89eda26SStefan Roese partition@1e0000 { 180a89eda26SStefan Roese label = "dtb"; 181a89eda26SStefan Roese reg = <0x001e0000 0x00020000>; 182a89eda26SStefan Roese }; 183a89eda26SStefan Roese partition@200000 { 184a89eda26SStefan Roese label = "root"; 185a89eda26SStefan Roese reg = <0x00200000 0x00200000>; 186a89eda26SStefan Roese }; 187a89eda26SStefan Roese partition@400000 { 188a89eda26SStefan Roese label = "user"; 189a89eda26SStefan Roese reg = <0x00400000 0x00b60000>; 190a89eda26SStefan Roese }; 191a89eda26SStefan Roese partition@f60000 { 192a89eda26SStefan Roese label = "env"; 193a89eda26SStefan Roese reg = <0x00f60000 0x00040000>; 194a89eda26SStefan Roese }; 195a89eda26SStefan Roese partition@fa0000 { 196a89eda26SStefan Roese label = "u-boot"; 197a89eda26SStefan Roese reg = <0x00fa0000 0x00060000>; 198a89eda26SStefan Roese }; 199a89eda26SStefan Roese }; 200a89eda26SStefan Roese 201a89eda26SStefan Roese SysACE_CompactFlash: sysace@1,0 { 202a89eda26SStefan Roese compatible = "xlnx,sysace"; 203a89eda26SStefan Roese interrupt-parent = <&UIC2>; 204a89eda26SStefan Roese interrupts = <24 0x4>; 205a89eda26SStefan Roese reg = <0x00000001 0x00000000 0x10000>; 206a89eda26SStefan Roese }; 207a89eda26SStefan Roese }; 208a89eda26SStefan Roese 209a89eda26SStefan Roese UART0: serial@f0000200 { 210a89eda26SStefan Roese device_type = "serial"; 211a89eda26SStefan Roese compatible = "ns16550"; 212a89eda26SStefan Roese reg = <0xf0000200 0x00000008>; 213a89eda26SStefan Roese virtual-reg = <0xa0000200>; 214a89eda26SStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 215a89eda26SStefan Roese current-speed = <115200>; 216a89eda26SStefan Roese interrupt-parent = <&UIC0>; 217a89eda26SStefan Roese interrupts = <0x0 0x4>; 218a89eda26SStefan Roese }; 219a89eda26SStefan Roese 220a89eda26SStefan Roese UART1: serial@f0000300 { 221a89eda26SStefan Roese device_type = "serial"; 222a89eda26SStefan Roese compatible = "ns16550"; 223a89eda26SStefan Roese reg = <0xf0000300 0x00000008>; 224a89eda26SStefan Roese virtual-reg = <0xa0000300>; 225a89eda26SStefan Roese clock-frequency = <0>; 226a89eda26SStefan Roese current-speed = <0>; 227a89eda26SStefan Roese interrupt-parent = <&UIC0>; 228a89eda26SStefan Roese interrupts = <0x1 0x4>; 229a89eda26SStefan Roese }; 230a89eda26SStefan Roese 231a89eda26SStefan Roese 232a89eda26SStefan Roese UART2: serial@f0000600 { 233a89eda26SStefan Roese device_type = "serial"; 234a89eda26SStefan Roese compatible = "ns16550"; 235a89eda26SStefan Roese reg = <0xf0000600 0x00000008>; 236a89eda26SStefan Roese virtual-reg = <0xa0000600>; 237a89eda26SStefan Roese clock-frequency = <0>; 238a89eda26SStefan Roese current-speed = <0>; 239a89eda26SStefan Roese interrupt-parent = <&UIC1>; 240a89eda26SStefan Roese interrupts = <0x5 0x4>; 241a89eda26SStefan Roese }; 242a89eda26SStefan Roese 243a89eda26SStefan Roese IIC0: i2c@f0000400 { 244a89eda26SStefan Roese compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; 245a89eda26SStefan Roese reg = <0xf0000400 0x00000014>; 246a89eda26SStefan Roese interrupt-parent = <&UIC0>; 247a89eda26SStefan Roese interrupts = <0x2 0x4>; 248a89eda26SStefan Roese }; 249a89eda26SStefan Roese 250a89eda26SStefan Roese IIC1: i2c@f0000500 { 251a89eda26SStefan Roese compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; 252a89eda26SStefan Roese reg = <0xf0000500 0x00000014>; 253a89eda26SStefan Roese interrupt-parent = <&UIC0>; 254a89eda26SStefan Roese interrupts = <0x3 0x4>; 255a89eda26SStefan Roese #address-cells = <1>; 256a89eda26SStefan Roese #size-cells = <0>; 257a89eda26SStefan Roese 258a89eda26SStefan Roese rtc@68 { 2595edc2aaeSStefan Agner compatible = "st,m41t00"; 260a89eda26SStefan Roese reg = <0x68>; 261a89eda26SStefan Roese }; 262a89eda26SStefan Roese }; 263a89eda26SStefan Roese 264a89eda26SStefan Roese EMAC0: ethernet@f0000800 { 265a89eda26SStefan Roese linux,network-index = <0x0>; 266a89eda26SStefan Roese device_type = "network"; 267a89eda26SStefan Roese compatible = "ibm,emac-440spe", "ibm,emac4"; 268a89eda26SStefan Roese interrupt-parent = <&UIC1>; 269a89eda26SStefan Roese interrupts = <0x1c 0x4 0x1d 0x4>; 270a89eda26SStefan Roese reg = <0xf0000800 0x00000074>; 271a89eda26SStefan Roese local-mac-address = [000000000000]; 272a89eda26SStefan Roese mal-device = <&MAL0>; 273a89eda26SStefan Roese mal-tx-channel = <0>; 274a89eda26SStefan Roese mal-rx-channel = <0>; 275a89eda26SStefan Roese cell-index = <0>; 276a89eda26SStefan Roese max-frame-size = <9000>; 277a89eda26SStefan Roese rx-fifo-size = <4096>; 278a89eda26SStefan Roese tx-fifo-size = <2048>; 279a89eda26SStefan Roese phy-mode = "gmii"; 280a89eda26SStefan Roese phy-map = <0x00000000>; 281a89eda26SStefan Roese has-inverted-stacr-oc; 282a89eda26SStefan Roese has-new-stacr-staopc; 283a89eda26SStefan Roese }; 284a89eda26SStefan Roese }; 285a89eda26SStefan Roese 286a89eda26SStefan Roese PCIX0: pci@c0ec00000 { 287a89eda26SStefan Roese device_type = "pci"; 288a89eda26SStefan Roese #interrupt-cells = <1>; 289a89eda26SStefan Roese #size-cells = <2>; 290a89eda26SStefan Roese #address-cells = <3>; 291a89eda26SStefan Roese compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix"; 292a89eda26SStefan Roese primary; 293a89eda26SStefan Roese large-inbound-windows; 294a89eda26SStefan Roese enable-msi-hole; 295a89eda26SStefan Roese reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 296a89eda26SStefan Roese 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 297a89eda26SStefan Roese 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 298a89eda26SStefan Roese 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 299a89eda26SStefan Roese 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 300a89eda26SStefan Roese 301a89eda26SStefan Roese /* Outbound ranges, one memory and one IO, 302a89eda26SStefan Roese * later cannot be changed 303a89eda26SStefan Roese */ 304a89eda26SStefan Roese ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 305a89eda26SStefan Roese 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 306a89eda26SStefan Roese 307a89eda26SStefan Roese /* Inbound 4GB range starting at 0 */ 308a89eda26SStefan Roese dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; 309a89eda26SStefan Roese 310a89eda26SStefan Roese /* This drives busses 0 to 0xf */ 311a89eda26SStefan Roese bus-range = <0x0 0xf>; 312a89eda26SStefan Roese 313a89eda26SStefan Roese /* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */ 314a89eda26SStefan Roese interrupt-map-mask = <0x0 0x0 0x0 0x0>; 315a89eda26SStefan Roese interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>; 316a89eda26SStefan Roese }; 317a89eda26SStefan Roese 318a89eda26SStefan Roese PCIE0: pciex@d00000000 { 319a89eda26SStefan Roese device_type = "pci"; 320a89eda26SStefan Roese #interrupt-cells = <1>; 321a89eda26SStefan Roese #size-cells = <2>; 322a89eda26SStefan Roese #address-cells = <3>; 323a89eda26SStefan Roese compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; 324a89eda26SStefan Roese primary; 325a89eda26SStefan Roese port = <0x0>; /* port number */ 326a89eda26SStefan Roese reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 327a89eda26SStefan Roese 0x0000000c 0x10000000 0x00001000>; /* Registers */ 328a89eda26SStefan Roese dcr-reg = <0x100 0x020>; 329a89eda26SStefan Roese sdr-base = <0x300>; 330a89eda26SStefan Roese 331a89eda26SStefan Roese /* Outbound ranges, one memory and one IO, 332a89eda26SStefan Roese * later cannot be changed 333a89eda26SStefan Roese */ 334a89eda26SStefan Roese ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 335a89eda26SStefan Roese 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 336a89eda26SStefan Roese 337a89eda26SStefan Roese /* Inbound 4GB range starting at 0 */ 338a89eda26SStefan Roese dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; 339a89eda26SStefan Roese 340a89eda26SStefan Roese /* This drives busses 0x10 to 0x1f */ 341a89eda26SStefan Roese bus-range = <0x10 0x1f>; 342a89eda26SStefan Roese 343a89eda26SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 344a89eda26SStefan Roese * to invert PCIe legacy interrupts). 345a89eda26SStefan Roese * We are de-swizzling here because the numbers are actually for 346a89eda26SStefan Roese * port of the root complex virtual P2P bridge. But I want 347a89eda26SStefan Roese * to avoid putting a node for it in the tree, so the numbers 348a89eda26SStefan Roese * below are basically de-swizzled numbers. 349a89eda26SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 350a89eda26SStefan Roese */ 351a89eda26SStefan Roese interrupt-map-mask = <0x0 0x0 0x0 0x7>; 352a89eda26SStefan Roese interrupt-map = < 353a89eda26SStefan Roese 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */ 354a89eda26SStefan Roese 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */ 355a89eda26SStefan Roese 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */ 356a89eda26SStefan Roese 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>; 357a89eda26SStefan Roese }; 358a89eda26SStefan Roese 359a89eda26SStefan Roese PCIE1: pciex@d20000000 { 360a89eda26SStefan Roese device_type = "pci"; 361a89eda26SStefan Roese #interrupt-cells = <1>; 362a89eda26SStefan Roese #size-cells = <2>; 363a89eda26SStefan Roese #address-cells = <3>; 364a89eda26SStefan Roese compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; 365a89eda26SStefan Roese primary; 366a89eda26SStefan Roese port = <0x1>; /* port number */ 367a89eda26SStefan Roese reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 368a89eda26SStefan Roese 0x0000000c 0x10001000 0x00001000>; /* Registers */ 369a89eda26SStefan Roese dcr-reg = <0x120 0x020>; 370a89eda26SStefan Roese sdr-base = <0x340>; 371a89eda26SStefan Roese 372a89eda26SStefan Roese /* Outbound ranges, one memory and one IO, 373a89eda26SStefan Roese * later cannot be changed 374a89eda26SStefan Roese */ 375a89eda26SStefan Roese ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 376a89eda26SStefan Roese 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 377a89eda26SStefan Roese 378a89eda26SStefan Roese /* Inbound 4GB range starting at 0 */ 379a89eda26SStefan Roese dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; 380a89eda26SStefan Roese 381a89eda26SStefan Roese /* This drives busses 0x20 to 0x2f */ 382a89eda26SStefan Roese bus-range = <0x20 0x2f>; 383a89eda26SStefan Roese 384a89eda26SStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 385a89eda26SStefan Roese * to invert PCIe legacy interrupts). 386a89eda26SStefan Roese * We are de-swizzling here because the numbers are actually for 387a89eda26SStefan Roese * port of the root complex virtual P2P bridge. But I want 388a89eda26SStefan Roese * to avoid putting a node for it in the tree, so the numbers 389a89eda26SStefan Roese * below are basically de-swizzled numbers. 390a89eda26SStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 391a89eda26SStefan Roese */ 392a89eda26SStefan Roese interrupt-map-mask = <0x0 0x0 0x0 0x7>; 393a89eda26SStefan Roese interrupt-map = < 394a89eda26SStefan Roese 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */ 395a89eda26SStefan Roese 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */ 396a89eda26SStefan Roese 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */ 397a89eda26SStefan Roese 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>; 398a89eda26SStefan Roese }; 399a89eda26SStefan Roese 400a89eda26SStefan Roese I2O: i2o@400100000 { 401a89eda26SStefan Roese compatible = "ibm,i2o-440spe"; 402a89eda26SStefan Roese reg = <0x00000004 0x00100000 0x100>; 403a89eda26SStefan Roese dcr-reg = <0x060 0x020>; 404a89eda26SStefan Roese }; 405a89eda26SStefan Roese 406a89eda26SStefan Roese DMA0: dma0@400100100 { 407a89eda26SStefan Roese compatible = "ibm,dma-440spe"; 408a89eda26SStefan Roese cell-index = <0>; 409a89eda26SStefan Roese reg = <0x00000004 0x00100100 0x100>; 410a89eda26SStefan Roese dcr-reg = <0x060 0x020>; 411a89eda26SStefan Roese interrupt-parent = <&DMA0>; 412a89eda26SStefan Roese interrupts = <0 1>; 413a89eda26SStefan Roese #interrupt-cells = <1>; 414a89eda26SStefan Roese #address-cells = <0>; 415a89eda26SStefan Roese #size-cells = <0>; 416a89eda26SStefan Roese interrupt-map = < 417a89eda26SStefan Roese 0 &UIC0 0x14 4 418a89eda26SStefan Roese 1 &UIC1 0x16 4>; 419a89eda26SStefan Roese }; 420a89eda26SStefan Roese 421a89eda26SStefan Roese DMA1: dma1@400100200 { 422a89eda26SStefan Roese compatible = "ibm,dma-440spe"; 423a89eda26SStefan Roese cell-index = <1>; 424a89eda26SStefan Roese reg = <0x00000004 0x00100200 0x100>; 425a89eda26SStefan Roese dcr-reg = <0x060 0x020>; 426a89eda26SStefan Roese interrupt-parent = <&DMA1>; 427a89eda26SStefan Roese interrupts = <0 1>; 428a89eda26SStefan Roese #interrupt-cells = <1>; 429a89eda26SStefan Roese #address-cells = <0>; 430a89eda26SStefan Roese #size-cells = <0>; 431a89eda26SStefan Roese interrupt-map = < 432a89eda26SStefan Roese 0 &UIC0 0x16 4 433a89eda26SStefan Roese 1 &UIC1 0x16 4>; 434a89eda26SStefan Roese }; 435a89eda26SStefan Roese 436a89eda26SStefan Roese xor-accel@400200000 { 437a89eda26SStefan Roese compatible = "amcc,xor-accelerator"; 438a89eda26SStefan Roese reg = <0x00000004 0x00200000 0x400>; 439a89eda26SStefan Roese interrupt-parent = <&UIC1>; 440a89eda26SStefan Roese interrupts = <0x1f 4>; 441a89eda26SStefan Roese }; 442a89eda26SStefan Roese }; 443a89eda26SStefan Roese 444a89eda26SStefan Roese chosen { 44578e5dfeaSRob Herring stdout-path = "/plb/opb/serial@f0000200"; 446a89eda26SStefan Roese }; 447a89eda26SStefan Roese}; 448